JPH06103101A - Built-in self-testing circuit of integrated circuit and its evaluating method and designing method - Google Patents

Abstract

PURPOSE:To provide the built-in self-testing circuit to a network type integrated circuit in which plural integrated circuits are coupled by a data path, and the evaluating method and the designing method which can estimate its circuit at a low cost and with high efficiency, and also, a fault detection rate with high precision. CONSTITUTION:In the case of executing a test of the whole network type integrated circuit in which plural pieces of logical arithmetic circuits 105-110 are coupled by a data path 12 by a built-in self-testing circuit in which a pseudo random number pattern generator is used as a pattern generator 101, with respect to the number of random number test patterns generated from the pattern generator 101 of the built-in self-testing circuit, which becomes necessary in order to attain a fault detection rate being a target, evaluation of each logical arithmetic circuit 105-110 being a component of a network type integrated circuit 104, and evaluation to a network constitution for coupling each logical arithmetic circuit thereof are executed separately, and its result is synthesized and derived.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a built-in self test circuit for a network type integrated circuit in which a plurality of logical operation circuits are connected by a data path, and an evaluation method and design method thereof. .

[0002]

2. Description of the Related Art As a conventional technique for evaluating a built-in self-test circuit of an integrated circuit, a random number pattern generated from a pattern generator of the built-in self-test circuit is used as a test pattern to cause a failure of the entire integrated circuit to be tested. There is a method of calculating a failure detection rate by performing a failure simulation using a simulator. The evaluation method using this fault simulation assumes that a logic fault model (often a single stuck-at fault) is assumed for the circuit under test, and whether the fault can be detected by simulation using the test pattern actually given to the circuit under test. This is a method for investigating, and it is possible to obtain an accurate value of the detection rate for an assumed failure. Since this method requires a huge amount of calculation, various algorithms have been devised to speed it up. However, even if the most advanced algorithm is used, the simulation time is 1.5 times the circuit scale. Therefore, a large amount of simulation time is required for a large-scale circuit.

[0003]

This is a typical example of a network type integrated circuit in which a plurality of logical operation circuits to which the present invention is applied are connected by a data path by using the above-described evaluation method using failure simulation. LIS for signal processing
When the built-in self-test is evaluated for this data path unit, a large-scale pattern (tens of thousands of patterns) of failure simulation needs to be performed for the entire data path unit (tens of k gates scale). There is a problem that an expensive hardware simulation engine that can handle a circuit and a sequential circuit must be occupied for a long time, and a large computer cost is required. Further, since the net list of the entire data path unit is required, there is a problem that the evaluation of the built-in self-test circuit cannot be started until the final data path of the data path unit is determined. Further, it is necessary to redo the evaluation from the beginning every time the data path is changed or the configuration of the built-in self-test circuit is changed, which is inefficient.

The present invention has been made in order to solve the above-mentioned problems, and provides a built-in self-test circuit for a network type integrated circuit in which a plurality of integrated circuits are connected by a data path and a low cost for the circuit. Another object of the present invention is to provide an evaluation method and a design method capable of estimating a failure detection rate with high efficiency and high accuracy.

[0005]

In order to achieve the above object, the present invention provides a built-in self-test circuit using a pseudo random number pattern generator as a pattern generator, whereby a plurality of logical operation circuits are connected by a data path. The number of random number test patterns generated from the pattern generator of the above built-in self-test circuit, which is necessary to achieve the target fault detection rate, when testing the entire network integrated circuit The evaluation of each logical operation circuit, which is a constituent element of the circuit, and the evaluation of the network configuration connecting the respective logical operation circuits are separately performed, and the results are comprehensively obtained.

That is, for each logical operation circuit which is a constituent element of the network type integrated circuit, a random number test pattern is used to determine how many random number patterns are given to the single integrated circuit to obtain a desired fault coverage. The validity of the test was evaluated, and when the self-test circuit was built in the entire network type integrated circuit for the network configuration connecting the logical operation circuits, the number of patterns given to the input of the network type integrated circuit Evaluate the effectiveness of the test using a random number test pattern based on the probability of what percentage will be an effective pattern in each logical operation circuit, and compare the evaluation results of both to determine the number of random number test patterns above. Decide

In the above-mentioned divisional evaluation, each logical operation circuit which is a constituent element of the network type integrated circuit is evaluated by using a fault simulation which is a conventional method. In this case, the simulation target is a small-scale logical operation circuit (several hundreds to several KG scale), and the computer cost is reduced as compared with the case where the failure simulation is performed on the entire network type integrated circuit. If you want to further reduce the calculation cost by the evaluation method using a failure simulator, you may consider using a testability measure that gives a failure detection probability. This method is also referred to in the literature
(SKJain, et al., "STAFAN: An Alternative to Fault S
imulation, "21nd Design Automat. Conf., pp.18-23 (19
84).

Further, according to the present invention, the number of random number patterns necessary for obtaining the target detection rate obtained as a result of the evaluation of each logic operation circuit described above is made into a database to form a new data path unit. The method used for evaluation is provided.

Further, according to the present invention, in the evaluation of the network configuration connecting the logical operation circuits, the functional description of the network type integrated circuit is used and a random number pattern is given to the input of the network type integrated circuit to perform the function simulation. , The pattern type appearing at the input / output of the logical operation circuit forming the network type integrated circuit is examined, and in each logical operation circuit, the probability that the pattern given to the input of the network type integrated circuit is propagated to each logical operation circuit as a different pattern ( Random controllability) is calculated by the following formula,

[0010]

[Formula 1] Probability of how many random numbers pass through each logical operation circuit without degeneration (random number transmission probability)
Is calculated by the following formula,

[0011]

[Formula 2] In each logical operation circuit, the probability (random number observable probability) of not being overlooked during the influence of a fault occurring in each logical operation circuit and propagating to the output of the network type integrated circuit is expressed by the following equation. From the output to the output of the network type integrated circuit to all the logical operation circuit that exists on the path, by multiplying the random number transmission probability obtained above,

[0012]

[Formula 3] In each logical operation circuit, when a self-test circuit is built in the whole network type integrated circuit, what percentage of the number of patterns given to the input of the network type integrated circuit is a valid pattern (random number Propagation probability) is calculated by the following formula,

[0013]

[Formula 4] The random number propagation probability is obtained in advance by a failure simulation or the like at the time of evaluating each logical operation circuit that is a component, and the number of patterns for each logical operation circuit (a random number pattern In the built-in self-test circuit of the entire network type integrated circuit, an evaluation method for determining how many patterns are necessary to achieve the target detection rate is provided.

Further, according to the present invention, the pseudo random number pattern generator and the pattern compressor of the built-in self-test circuit are
Using a counter etc., when a random number pattern of the number of patterns determined by the above-mentioned built-in test evaluation method is generated, a control mechanism for terminating the operation (pattern generation, pattern compression) of the built-in self-test circuit is provided for a short time. It is possible to realize a built-in self-test circuit that can be tested with and reduces external control.

Further, according to the present invention, when the logical operation circuit which is a constituent element of the network type integrated circuit is not suitable for the random number test, a control point and an observation point are added in the logical operation circuit,
A logical operation circuit that can obtain a high detection rate with a small number of patterns can be designed.

Further, according to the present invention, when the network configuration connecting the logical operation circuits is not suitable for the random number test, the register in the database unit is incorporated into the self-test register (pattern generator, pattern compressor). By replacing, it is possible to provide a built-in self-test circuit in which the controllability and observability are improved in the effectiveness of the test by the random number test pattern.

[0017]

According to the present invention, the evaluation of each logical operation circuit that is a constituent element of the network integrated circuit and the evaluation of the network configuration connecting the logical operation circuits are separately performed and the divided evaluation is performed. The problem of the conventional method of evaluating the whole at once using a failure simulator, etc., that a failure simulation for a large-scale circuit is necessary and a large computer cost is required,
Also, it is possible to avoid two problems that the evaluation cannot be started until the whole circuit is completed and the efficiency is low,
Highly efficient evaluation is possible at low cost.

Further, by making a database of the evaluation results of the respective logic operation circuits and reusing them, it becomes possible to evaluate the built-in self-test circuit having a new network configuration with high efficiency.

Further, the pattern generator of the built-in self-test circuit according to the present invention is premised on a pseudo-random number generator, and the test pattern is a random number pattern independent of the target circuit, so that the logical operation circuits are connected with each other. The evaluation of the combined network configuration can be replaced with an evaluation of how random numbers propagate in the network type integrated circuit. As a result, the failure detection rate can be accurately obtained by obtaining the random number propagation probability as described above.

Further, a control mechanism for terminating the operation of the pattern generator and the pattern compressor with a specific pattern number is added to the built-in self-test circuit, so that only the start signal of the built-in test circuit is supplied from the outside of the integrated circuit to install the pattern. The test becomes feasible.

As a result of the built-in self-test evaluation, if the desired fault coverage cannot be obtained with a realistic number of patterns (test time), the built-in self-test circuit needs to be improved. According to the invention, the evaluation of each logical operation circuit which is a constituent element of the network type integrated circuit and the evaluation of the network configuration connecting the logical operation circuits are separately performed, so that it is easy to specify the place to be improved. Is.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings.

The built-in self-test circuit of the data path unit of the image processing DSP is evaluated using the present invention. FIG. 1 shows the configuration of the data path unit section which is the circuit to be tested and the configuration of the built-in self-test circuit. As shown in FIG. 1, the data path unit (104) includes two adder / subtractors (105) and (109), two barrel shifters (106) and (110), and one arithmetic logic operation unit (107). , One multiplier (108), register (11
1) and a data path (1
12). The built-in self-test circuit
A pseudo random number pattern generator (101) for giving a test pattern to the input part of the data path unit (104),
The pattern compressor (113) for compressing the data output from the output section of the data path unit (104), the pattern generation of the pattern generator (101) with a specific number of patterns, and the pattern compression of the pattern compressor (113). Built-in self-test control circuit (counter, etc.) to terminate (10
2) and a control line (103). The number of patterns of the built-in self-test control circuit (102) is determined by the evaluation method described later.

As shown in FIG. 2, first of all, each arithmetic unit (105), which is a constituent element of the data path unit (104),
It is necessary to determine how many patterns are required to obtain a desired fault coverage in each of the six arithmetic units shown in the above as the evaluation (21) of (110) by performing the fault simulation and the like. A random number pattern (NP) is calculated, and the required number of random number patterns is stored in a database and used for evaluation when constructing a new data path unit.

Next, as an evaluation (22) for the network configuration (112) connecting the arithmetic units, the functional description of the data path unit (104) is used to input a random number pattern (RP) to the data path unit (104). ) Is given and a functional simulation is performed, and random number controllability probability (RC), random number transparency probability (RT), random number observability (RO), random number propagation probability ( RM).

The calculation method of this random number propagation probability (RM) is
The arithmetic logic operation unit (107) of the data path unit (104) will be described in detail with reference to FIG.
A random number pattern (RP) is given to the input part (32) of the data path unit (107) to perform a functional simulation to check the pattern type appearing at the input / output part of the arithmetic logic operation unit (107). (Input part (32) ... M1 pattern, output part (33) ... M2 pattern). The random number controllable probability (RC) is calculated by M1 ÷ RP (35). The random number transmission probability (RT) is calculated by M2 ÷ RP (35) (MO = RP). The multiplier (108) and the adder-subtractor 1 are provided on the path from the output (33) of the arithmetic logic operation unit (107) to the output (34) of the data path unit (104).
(109), since there are three arithmetic units of the barrel shifter 1 (110), the random number observable probability (RO) is the random number transmission probability of the multiplier (108), the random number transmission probability of the adder / subtractor 1 (109), and the barrel shifter. It is calculated (35) by the product of the random number transmission probabilities of 1 (110). The random number propagation probability (RM) is calculated by the product of the random number controllable probability and the random number observable probability (35).

Next, the product of the random number patterns (RP) is calculated for the random number propagation rate RM of each arithmetic unit, and in each arithmetic unit, the percentage of the number of patterns given to the input of the data path unit is effective. The number of patterns (EP) is calculated. For each arithmetic unit, the necessary random number pattern (NP) obtained by the evaluation of each arithmetic unit that is a constituent element is compared with the number of effective patterns (EP), and if NP ≦ EP in all cases, the evaluation is performed. finish. In this case, the target fault coverage is obtained by the built-in self-test circuit for the data path unit with the random number pattern (RP). In the above comparison, when there is at least one computing unit satisfying NP ≦ EP, the random number pattern (RP) is increased, the functional simulation is performed again, the random number propagation probability calculation, and the comparison with the necessary random number pattern (NP) are performed. The process described above is repeated.

The effectiveness when the random number propagation probability is used as an evaluation of the network configuration between the arithmetic units will be shown. Table 1 shows the result of obtaining the random number propagation probability for each arithmetic unit with the random number pattern RP = 2000 patterns.

[0029]

[Table 1] As shown in Table 1, the random number propagation probability (RM) is 0.3 to
It shows 0.9. Effective pattern EP in each arithmetic unit
(How many patterns does it correspond to when tested alone)
Is a value obtained by multiplying this value by the random number pattern number 2000. Although these values are generally high, this is because the data path unit taken as an example has a single-flow data path configuration, so even in a sequential circuit, an output sequence is fed back to the input. It is thought that this is because the degree of propagation of randomness is higher than that of the thing.

Next, the accuracy of the random number propagation probability will be evaluated. As described above, (RM) indicates, in the case where the built-in self-test circuit is configured by the entire data path unit, what percentage of the pattern given to the input of the data path unit has each arithmetic unit tested. Therefore, assuming that (RM) indicates an accurate index, the fault coverage in each arithmetic unit when the entire data path unit is tested with 2000 patterns, and the fault detection rate in each arithmetic unit when tested with 2000 × RM pattern The fault coverage should match. Table 2 shows the comparison results of the fault detection rates of the entire data path unit and the individual computing units.

[0031]

[Table 2] At the time of the above comparison, there are various processes such as those in which the fault coverage still rises, those that are already close to the convergence value, but the differences in fault coverage are ± 0.1
It is within 5%, and it can be confirmed that it has sufficient accuracy as an alternative method of failure simulation.

As a result of the evaluation, if the desired fault coverage cannot be obtained with a realistic number of patterns (test time), it is necessary to make some modifications to the configuration of the built-in self-test circuit. In the present invention, since the arithmetic unit which is an individual element and its network configuration are separately evaluated, the correction can be easily performed. That is, as a result of the evaluation of the arithmetic unit which is an individual element, when it is found that a certain arithmetic unit (for example, the multiplier (108) in FIG. 4) is not suitable for the random number test, the control point is increased in order to improve the overcontrol by the random number pattern. In order to improve the observability of (41) by the random number pattern, an observation point (43) is added to the arithmetic unit to improve the circuit configuration of the arithmetic unit for a random number test.
Is a control line, and (44) is an observation line.

Further, when it is found as a result of the evaluation of the network configuration that the random number propagation probability of a certain computing unit (for example, the multiplier (108) in FIG. 5 is bad, the computing unit (108 ) Preceding register (11
1a) and (111b) are replaced with built-in self-test registers (pattern generators), and registers (111c) in the latter stage of the arithmetic unit (108) are built-in self-test registers (pattern compressors) in order to improve random number observability. ) To improve the network configuration for random number tests.

[0034]

As described above, according to the present invention, the divided evaluation is performed by dividing the evaluation of each logical operation circuit which is a constituent element of the network type integrated circuit and the evaluation of the network configuration connecting the logical operation circuits. By doing so, failure simulation for a large-scale sequential circuit becomes unnecessary, and the computer cost can be reduced. In addition, as each logical operation circuit is completed, evaluation can be started sequentially, so the entire data path design and evaluation data of the built-in self-test circuit are made into a database together with the design data to design a new network-type integrated circuit. Is available when
From this point as well, the efficiency of evaluation can be improved.

Further, since the random number propagation probability used for evaluation of the network configuration connecting the logical operation circuits can be calculated by the functional simulation using the functional description of the network type integrated circuit, the computer cost can be reduced. The value of the random number propagation probability is suitable for representing the effectiveness of the built-in self-test circuit using the pseudo-random number generator that tests with the random number test pattern independent of the target circuit, which is the premise of the present invention. Therefore, highly accurate evaluation is possible. This is also confirmed by the evaluation result using the actual circuit as described above.

The number of test patterns when the above evaluation method is used can be set to a value close to the minimum number of patterns required to obtain a target fault coverage, and the number of built-in self-patterns can be set according to the number of patterns. The test time can be shortened by providing a mechanism for ending the operation of the test circuit.

Further, since the evaluation of each logical operation circuit, which is a constituent element of the network type integrated circuit, and the evaluation of the network configuration connecting the logical operation circuits are separately performed, the divided evaluation is performed, so that it is not suitable for the random number test. Is easy to identify, and it is easy to improve the built-in self-test circuit when a desired fault coverage cannot be obtained with a realistic number of patterns (test time).

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data path unit section of an image processing DSP and a configuration of a built-in self-test circuit.

FIG. 2 is a diagram showing an evaluation process of a built-in self-test circuit of a data path unit using the present invention.

FIG. 3 is a diagram showing a procedure for obtaining a random number propagation probability with respect to an arithmetic operation section of a data path unit section of an image processing DSP.

FIG. 4 is a diagram showing an improvement (addition of control points and observation points in the logic operation circuit) when the logic operation circuit is not suitable for a random number test.

FIG. 5 is a diagram showing an improvement (replacement of a self-test register by incorporating a register in a data path unit) when the network configuration is not suitable for a random number test.

[Explanation of symbols]

101 ... Pseudo-random number pattern generator of built-in self-test circuit, 102 ... Control circuit of built-in self-test circuit, 103
... control line of built-in self-test circuit, 104 ... network type integrated circuit (data path unit), 105 ... logical operation circuit (adder / subtractor 0), 106 ... logical operation circuit (barrel shifter 0), 107 ... logical operation circuit (arithmetic logic) Arithmetic unit), 108 ... logical operation circuit (multiplier), 109 ... logical operation circuit (adder / subtractor 1), 110 ... logical operation circuit (barrel shifter 1), 111 ... register, 112 ... data path connecting logical operation circuits, 113 ... Pattern compressor for built-in self-test circuit.

Claims (6)

[Claims] 1. A built-in self-test circuit using a pseudo random number pattern generator is constructed for a network type integrated circuit in which a plurality of logical operation circuits are connected by a data path, and the built-in self-test circuit is evaluated. A first step of calculating the number of random number test patterns required to obtain a target fault coverage for each logical operation circuit that is a constituent element of the network-type integrated circuit; A target is obtained from the second step of calculating the effectiveness (random number propagation probability) of the test by the random number test pattern for the network configuration connecting the circuits, and the evaluation results of the first step and the second step. Evaluation of a built-in self-test circuit of an integrated circuit, characterized in that it has a third step of determining the number of random number test patterns required to achieve the fault coverage. Valuation method. 2. A pattern appearing at the input and output of each logical operation circuit that constitutes the network type integrated circuit, using the functional description of the network type integrated circuit, performing a functional simulation by giving a random number pattern to the input of the network type integrated circuit. The pattern given to the input of the network type integrated circuit is different by examining the type and dividing the pattern type appearing at the input of the logical type operation circuit by the number of random number patterns given to the input of the network type integrated circuit in each logic operation circuit. By obtaining the probability (random number controllable probability) of propagating to each single integrated circuit as a pattern, and dividing the pattern type appearing in the output of the logical operation circuit by the pattern type appearing in the input of the single integrated circuit in each logical operation circuit, Whether the random number pattern is transparent in each logical operation circuit without degeneration The ratio (random number transmission probability) is calculated, and in each logical operation circuit, the random number transmission calculated above for all logical operation circuits existing on the path from the output of the logical operation circuit to the output of the network type integrated circuit By multiplying the probabilities, the probability (random number observable probability) of propagating to the output of the network type integrated circuit without being overlooked by the logical operation circuit on the way, the influence of the fault occurring in each logical operation circuit is obtained, and each logical operation circuit is calculated. When a self-test circuit is built in the whole network type integrated circuit by multiplying the above random number controllable probability and the above random number observable probability, what% of the number of patterns given to the input of the network type integrated circuit 2. A method for evaluating a self-test circuit of an integrated circuit according to claim 1, wherein a probability (random number propagation probability) of whether or not becomes an effective pattern is obtained. . 3. The number of random number test patterns obtained for each logical operation circuit in the first step according to claim 1 is stored in a database and used for evaluation when forming a new data path unit. The method for evaluating a built-in self-test circuit for an integrated circuit according to claim 1. 4. The logical operation circuit, which is a constituent element of the network integrated circuit according to claim 1, is necessary for adding a control point and an observation point in the logical operation circuit to obtain a target fault coverage. A method for designing a logical operation circuit, characterized by reducing the number of random number test patterns. 5. In a built-in self-test circuit of an integrated circuit comprising a pseudo random number pattern generator and a pattern compressor, when a random number test pattern of the number determined in claim 1 or 2 is generated, pattern generation and pattern compression operation are performed. A built-in self-test circuit for an integrated circuit, which has a control mechanism for terminating the circuit. 6. A register in a data path unit is used as a pattern generator or a pattern compressor in order to improve the effectiveness of a test by a random number test pattern for a network configuration connecting logical operation circuits according to claim 1. 6. The built-in self-test circuit for an integrated circuit according to claim 5, wherein the built-in self-test circuit is replaced with the built-in self-test register.