JPH059996B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex data transmission system, and in particular to a fail-safe system suitable for improving reliability when performing multiplex data transmission between a master station and a slave station. This article relates to an integrated wiring system for automobiles equipped with a safety function.

[Prior Art] Automobiles are equipped with electrical components such as various lamps and motors, and electronic devices such as various switches and sensors (hereinafter, the former is referred to as load-type electrical equipment and the latter as signal-generating electrical equipment). The total number of these items continues to increase with the advent of car electronics, and it is no longer unusual for cars to have hundreds of items.

Therefore, if each electrical component was individually wired, it would cause major problems in terms of space and installation work.To solve this problem, various integrated wiring systems have been proposed. It is starting to be put into practical use.

As described in Japanese Patent Application Laid-Open No. 55-105490, the conventional centralized wiring system connects a central control unit CCU and multiple terminal processing units LCU with an information transmission line, and the CCU is connected to a microcomputer and transmission control. Provides circuits and controls the entire system.
LCUs control a large number of electrical and electronic devices installed in automobiles, such as various switches, meters, lamps, and sensors, and for this reason, they are installed dispersedly near these devices.

[Problems to be Solved by the Invention] The above conventional technology does not take into account fail-safe data. For example, when an information transmission line or connectors break down, control commands are not transmitted from the CCU to the LCU, and the LCU There was a problem where the various switches, meters, lamps, and sensors connected to the system became inoperable.

An object of the present invention is to provide an integrated wiring system that can supply appropriate fail-safe data to each electric/electronic device even when a data transmission abnormality occurs due to a failure in a transmission path or the like.

[Means for Solving the Problems] The above object is to provide at least one of the slave stations with data storage means for sequentially updating and holding control data received from the master station, and when a transmission abnormality occurs, the data storage means This is achieved by supplying the data read from the load-type transmission equipment as fail-safe data for controlling the load-type transmission equipment.

To explain this in detail based on one example,
After the LCU sends data to the CCU, the LCU again
Equipped with a response time measurement circuit using a counter etc. to measure the time until data is received from the CCU, a fail-safe memory that holds external device control information, and a fail-safe register that controls this fail-safe memory. During normal transmission, the values in the fail-safe memory are constantly updated with device control information, and during abnormal transmission, each device is controlled by the values in the fail-safe memory. Furthermore, when the abnormal state returns to the normal state, the output of the fail-safe memory is turned off by clearing the fail-safe register, and this is achieved by controlling based on control information from the master station.

[Operation] When a transmission abnormality occurs, the data in the data storage means is no longer updated, so the data storage means retains the control data received from the master station immediately before. Therefore, by using this data as fail-safe data, stable control is possible even when a transmission abnormality occurs.

To explain this in detail in accordance with one embodiment, the response time measuring circuit has a counter and operates based on a reference clock. During normal operation of this counter, a frame reception signal is generated after one frame of received data is received, and the counter is cleared. However, when an abnormality occurs, the counter continues to operate, and when it overflows, the fail-safe register is set, so that the value in the fail-safe memory becomes the control data for the external device, and the external device is controlled. Also, when the abnormality recovers normally,
The failsafe register is cleared by the frame reception signal and normal operation resumes.

[Example] An example of the present invention will be described below with reference to FIGS. 1 and 2. Figure 1 is a block diagram of the transmission control device CIM1, which includes an input/output buffer 11, a fail-safe memory 12, a shift register 13, and a synchronous circuit 1.
4. Transmission control circuit 2, address check circuit 15
Consisted of. FIG. 2 is a detailed block diagram of the transmission control circuit 2, in which the shift clock synchronization circuit 21,
It consists of a response time measuring circuit 22, a fail-safe register 23, and an AND circuit 24.

Next, details of the operation of this embodiment will be explained based on the flowcharts of FIGS. 3 and 4.

FIG. 3 shows the main flow of the operation of this embodiment.

31 CIM1 monitors the reception terminal, and when a reception signal is input, it moves to processing 35), and when there is no input, it goes to processing
32).

32 The synchronization circuit 14 generates a shift clock A105 and sends it to the AND circuit 25 and response time measurement circuit 22. The response time measurement circuit 22
It has a multistage counter that measures time longer than the data transmission interval between the CCU and LCU, and updates the counter value by inputting the shift clock A105.

33 The counter value in the response time measurement circuit is
Compare with the predetermined value required for transmission and reception with the LCU. If the value does not match the predetermined value, the process returns to step 31).

34 If it matches the predetermined value, it means that no data is coming from the CCU, and the fail-safe register 23 is set, thereby setting the value in the fail-safe memory 12 as the control information for the input/output buffer 11, and the input/output terminals are set to this value. Controlled by control information. When the above-described process is completed, the process returns to process 31).

35 This is data reception processing and will be explained in detail below based on FIG. After the process is completed, return to process 31).
FIG. 4 is a reception processing flow.

41 When received data is input to CIM1 from the reception terminal, CIM1 uses the synchronization circuit 14 to extract the start bit of the input data.

42 The synchronization circuit 14 generates a synchronization signal 1 for extracting each bit of input data based on the start bit.
07 is sent. The synchronization signal 107 turns on the AND circuit 25 and enables the shift clock A105 to be sent to the transmission control circuit 2.

43 In transmission control circuit 2, this shift clock
A105 is input to a shift clock synchronization circuit 21, which generates a shift clock B104 for the shift register 13, and upon receiving this shift clock B104, the shift register 13 reads 1-bit data.

44 Also, in transmission control circuit 2, the shift clock
A105 is divided and also input to the response time measurement circuit 22 to update a counter in the response time measurement circuit 22.

45 Repeat processes 43) and 44) until data of a predetermined bit length is read into the shift register 13.

46 When data of a predetermined bit length is read into the shift register 13, the address part of this read data is compared with the self address set in the address check circuit 15.

47 If the comparison results match in step 46), the address check circuit 15 outputs an address match signal 106 to the transmission control circuit 2. Also, a frame reception signal 10 consisting of a shift register 13
3 is output to the transmission control circuit 2, and a counter clear signal is input to the response time measurement circuit 22 and fail-safe register 23 via the AND circuit 24 in the transmission control circuit 2. The counter in the response time measuring circuit 22 is initialized by this counter clear signal, and the fail safe register 23 is cleared. Then, the received control data is set in the input/output buffer 11 and the fail-safe memory 12 by this counter clear signal.

The input/output terminals are controlled by this control data.

As described above, according to this embodiment, the data transmission interval is always measured within the response time measurement circuit, and if data reception is interrupted due to a transmission error, the immediately preceding data is retained as fail-safe data. This allows the equipment to operate continuously and has the effect of avoiding deadlock of the equipment due to transmission abnormalities. In addition, since the receiving state is constantly monitored, when data is received in an abnormal state, the receiving operation is performed and the normal state can be automatically restored, which has the advantage of not requiring any external operation.

[Effects of the Invention] According to the present invention, even if a transmission abnormality occurs, the equipment affected by the abnormality can maintain its current state, thereby improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram of the transmission control circuit, FIG. 3 is an operation flow diagram, and FIG. 4 is a reception operation flow diagram. 1... Transmission control device, 2... Transmission control circuit, 11...
Input/output buffer, 12...fail safe memory,
13...Shift register, 14...Synchronization circuit, 15...
Address check circuit, 21...shift clock synchronization circuit, 22...response time measurement circuit, 23...fail safe register.

Claims (1)

[Claims] 1. A vehicle equipped with a master station for transmission control and capable of sequentially importing data from signal-generating electrical devices such as sensors and transmitting control data to load-type electrical devices via multiple slave stations. In an integrated wiring system for internal signal transmission, data storage means holds control data received from the master station, and means updates the data storage means with the control data only when transmission is being performed normally. is provided in at least one of the slave stations,
An integrated wiring system characterized in that, when a transmission abnormality occurs, data read from the data storage means is supplied as control data to the load-type electrical equipment.