JPH0595101A - Semiconductor photoelectric conversion device - Google Patents

Abstract

PURPOSE:To detect accurately how much electric charge is stored by incidnet light in an image region by providing a photoelectric conversion means, a semiconductor charge storage region, a storage gate electrode, a storage electric potential detecting means and a means to generate a control signal. CONSTITUTION:A photoelectric conversion means 3 for generating electric charge in accordance with injected light and a semiconductor charge storage region ST which can elclose circumference with a potential barrier for storing charge generated in the photoelectric conversion means 3 are provided. A storage gate electrode which is capacity-combined with a semiconductor charge storage region ST and storage potential detecting means M1 to M4, CMP for detecting electric potential of the storage gate electrode are provided. Means 4, 5 for generating a control signal for controlling charge stored in the semiconductor charge storage region ST based on electric potential of the storage gate electrode are provided. Thereby, accurate detection of stored charge becomes possible by directly reading an amount of charge stored in a charge storage region of a photo sensor through a capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photoelectric conversion device, and more particularly to a semiconductor photoelectric conversion device capable of detecting how much charge generated by incident light is accumulated in an accumulation region.

[0002]

2. Description of the Related Art When light having a photon energy larger than the band gap is incident on a semiconductor, the light is absorbed and electron-hole pairs are generated. When a potential gradient is formed in the semiconductor, electrons and holes are accelerated in opposite directions, so that photoexcited charges can be collected and accumulated.

An image sensor (including line sensor) can be formed by arranging a plurality of photodiodes or CCD (including MOS capacitor) photocells on the surface of a semiconductor substrate. Charges are accumulated according to the amount of light incident on each photocell to form an image signal.

In order to obtain a good image signal, it is necessary to consider the dynamic range of the photocell. Since each photocell cannot store more than a predetermined amount of electric charge, if the integrated incident light amount becomes too large, the stored electric charge will be saturated and overflow to the surroundings will occur. If such a state is continued, for example, the image becomes a uniform white area and the image information is lost.

If the stored charge is too small, the signal level will be low, and therefore the S / N ratio will be small and the accuracy will be low. Therefore, it is desired to detect how much charge is accumulated as image information.

FIG. 7 shows a configuration example of an automatic focus detection (autofocus) device according to a conventional technique. This automatic focus detection device observes the same subject from two line sensors arranged apart from each other, and calculates the distance to the subject from the angle at which the subject is viewed, based on the principle of triangulation.

FIG. 7A schematically shows an example of the structure after the line sensor lens. The standard line sensor 55 and the reference line sensor 56 are arranged with their optical axes aligned with the distance measuring lenses 53 and 54, respectively, which are separated by the base line length.

When the subject is at infinity, the distance measuring lenses 53 and 54 refer to the subject as the reference line sensor 5.
5, images are formed on the optical axis regions of the reference line sensor 56. When the subject approaches the camera, the light incident on the distance measuring lenses 53 and 54 from the subject changes so as to incline vertically.

That is, as the subject approaches the camera, the standard line sensor 55 and the reference line sensor 56.
The images formed on top of one another gradually separate. By detecting the distance between the image on the reference line sensor 55 and the image on the reference line sensor 56, the distance from the camera to the object can be measured by the principle of triangulation. A phase difference detection method is used to detect the distance between the images.

That is, the image signal B (k) is read out from each pixel of the reference line sensor 55 in a fixed phase, a predetermined phase difference m is set from the reference line sensor 56, and the image signal R (k + m) is read out. .. If these images are the same, B (k) -R (k + m) will be zero. The image reading area is set to n pixels, and this calculation is performed for each of the image signals read from the corresponding n pixels, and the correlation degree H (m) that is the sum of them is obtained.

H (m) = Σ (k = 1 to n) | B (k) −R (k + m) | (1) where Σ (k = 1 to n) is a function in which k is from 1 to n. Represents the sum of. The degree of correlation H (m) indicates the degree of coincidence between the image on the standard line sensor 55 and the image on the reference line sensor 56 at the phase m.

The phase m is sequentially changed, the correlation H (m) for each case is obtained, and the correlation curve is drawn. Then, the position where the correlation curve has the minimum value is the phase at which the image on the standard line sensor 55 and the image on the reference line sensor 56 are most in agreement. By detecting this phase, the distance from the camera to the subject can be measured.

The signal processing circuit 57 is an A / D converter 59 for converting a signal from the line sensor from an analog amount to a digital amount, and a RAM (Random Access Memory) which is a temporary storage device for storing the digitally converted image signal. Including 61. CPU using the image signal stored in the RAM 61
(Central Processing Unit) 60 performs the above-described calculation of the degree of correlation to detect the phase with the smallest degree of correlation.

In the focus detection device shown in FIG. 7A, the charge accumulated in the photosensor is directly converted into a voltage to form a detection signal, which is then converted into a digital signal and RA.
The calculation is performed by storing in M61 and reading out this signal.

The present applicant has proposed a line sensor that non-destructively reads out electric charges accumulated by irradiating light, and directly performs arithmetic processing with the analog amount as it is.

FIG. 7B shows a configuration example of such an optical sensor section. The photodetection portion is formed by forming a p-type well 66 on the surface of the n ⁻ -type silicon substrate 64, forming an n ⁺ -type region 68 in a part of the p-type well 66, and forming a pn junction 69. When light is incident on the vicinity of the pn junction 69, electron-hole pairs are formed, the electrons and holes are separated according to the potential gradient around the pn junction, and the electrons are accumulated.

In the figure, p extending to the left of the pn junction 69 is shown.
Insulated polysilicon gate electrodes 71 to 74 and 76 are formed on the mold well 66. Here, a barrier portion including a gate electrode 71 is formed adjacent to the photodiode, and a gate electrode 72 is formed next to the barrier portion.
Is formed. The broken line in the figure indicates the depletion layer.

When a charge corresponding to the light incident on the light receiving portion is generated, it is stored in the storage portion from the vicinity of the pn junction 69 through the barrier portion. The storage portion is a transfer gate electrode 73.
Through the gate electrode 74, and the shift register portion is continuous with the region below the floating gate electrode 76 having the bias applying aluminum electrode 75 thereon.

An overflow drain 82 in the n ⁺ type region is formed on the right side of the photodiode via an overflow gate 81.

That is, when an electron-hole pair is formed in response to light incident on the photodiode portion, carriers are accumulated in the accumulation portion below the gate electrode 72 beyond the barrier portion, and further transferred to the transfer gate electrode 73. It is transferred over and under the gate electrode 74 of the shift register.

The charges accumulated under the gate electrode 74 of the shift register section are transferred to the bottom of the floating gate electrode 76 depending on the voltage of the gate electrode 75. Electric charges corresponding to the transferred electric charges are induced in the floating gate electrode 76, and the incident light amount is read nondestructively by the electric charge amount.

When an optical sensor as shown in FIG. 7 (B) is used, the switched capacitor integration circuit can be used to perform the calculation of the equation (1) while keeping the charge at an analog amount.

When the amount of light incident on the photodiode becomes large, the photodiode and the storage section become full of the ability to store the charge, and the charge is overflow gate 81.
The potential of the overflow drain 82 is crossed over the lower potential barrier. When it is detected that the charge overflows into the overflow drain 82, the charge accumulation operation is terminated.

An example of a circuit for detecting an overflow from such a photodiode is shown in FIG. 7 (C). The diode formed of the p-type region 66 and the n-type region 82 accumulates in the n-type region 82 electrons overflowing from the photodiode formed by the p-type region 66 and the n-type region 68 shown in FIG. 7B.

The p-type region 66 and the n-types 68 and 82
Can be viewed as a diode, but can also be viewed as the source and drain of an FET connected through the overflow gate 81. Therefore, the n-type region 82
Name the overflow drain.

The overflow drain 82 is connected to the inverting input terminal of the operational amplifier 51. Also, operational amplifier 5
The reference voltage VOFD is applied to the non-inverting input terminal of No. 1. A parallel circuit of an analog switch 52 and a capacitance 53 is connected between the output terminal and the inverting input terminal of the operational amplifier 51.

Before the charge accumulation is started in the photodiode, the analog switch 52 is turned on and the operational amplifier 51 is turned on.
The potentials of the inverting input terminal and the output terminal of are the same as VOFD.

Simultaneously with the start of charge accumulation, the analog switch 52 is also turned off. When charges are accumulated in the photodiode and electrons flow into the overflow drain 82 through the potential barrier under the overflow gate, the electrons are accumulated in the capacitance 53. By changing the potential of the output terminal of the operational amplifier 51, the voltage of the inverting input terminal of the operational amplifier 51 is kept the same as the voltage VOFD of the non-inverting input terminal.

In this way, the overflow drain 8
As electrons are accumulated in 2, the potential of the output terminal of the operational amplifier 51 changes. By detecting the potential change at the output terminal of the operational amplifier 51, it is possible to detect the overflow, and thus the charge storage state of the charge storage region.

When an overflow is detected, the charge storage operation is terminated, the charge is transferred from the storage section to the shift register section in the configuration of FIG. 7B, and the signal corresponding to the stored charge is read from the floating gate electrode. ..

[0031]

For example, in the above-described automatic focus detection device and the like, the exposure level in the entire image pickup area is important for highly accurate focus detection. For example,
When only a part of the image has a very bright area such as sunlight, overflow easily occurs in such a bright area.

When such overflow is detected and the charge accumulation is terminated, the image information in the important object region is accumulated at an extremely low level. Therefore, it is desired to detect how much charge is accumulated on average in the entire image region.

An object of the present invention is to provide a semiconductor photoelectric conversion device capable of accurately detecting how much charge is accumulated by incident light in an image area.

[0034]

SUMMARY OF THE INVENTION A semiconductor photoelectric conversion device of the present invention comprises a photoelectric conversion means for generating electric charges in response to incident light, and a surrounding area for accumulating the electric charges generated by the photoelectric conversion means. With a potential barrier, a storage gate electrode capacitively coupled to the semiconductor charge storage region, storage potential detection means for detecting the potential of the storage gate electrode, and the storage gate electrode Means for generating a control signal for controlling the charge stored in the semiconductor charge storage region based on the potential.

[0035]

The photoelectric conversion means generates electric charges according to incident light. The generated charges are stored in the semiconductor charge storage region.
Since the storage gate electrode is capacitively coupled to the semiconductor charge storage region, its potential is changed as the charges are stored in the semiconductor charge storage region.

The potential change of the storage gate electrode is detected by the storage potential detecting means, and when a predetermined amount of change is detected, the control signal generating means generates a control signal.

For example, when the photoelectric conversion means includes a plurality of semiconductor photoelectric conversion cells, the storage gate electrodes are commonly connected and the potential thereof is detected to accurately detect the average charge storage state of the entire image region. can do.

[0038]

FIG. 1 shows an image sensor according to an embodiment of the present invention. FIG. 1A shows an image sensor circuit,
FIG. 1B shows the accumulated charge detection circuit.

In FIG. 1A, the main control circuit 1 has a C
Control signals are sent to the CD drive circuit 2, the AGC monitor circuit 4, and the integration time control circuit 5, respectively. CCD drive circuit 2
Generates phase signals Φ1 to Φ4 for controlling the transfer CCD of the CCD image sensor 3.

The CCD image sensor 3 has a light receiving portion such as a photodiode for detecting incident light, an accumulating portion for accumulating charges generated when light is incident on the light receiving portion, and transferring the accumulated charges. And a floating gate for detecting charges transferred by the CCD.

Further, the CCD image sensor 3 includes an accumulated charge detection mechanism for detecting how much the charge detected by the light receiving portion is accumulated in the accumulating portion, and the accumulated voltage signal VST
It is supplied to the GC monitor circuit 4.

The AGC monitor circuit 4 generates accumulated charges of sufficient intensity by the incident light in the CCD image sensor based on the control signal supplied from the main control circuit 1 and the accumulated voltage signal VST supplied from the CCD image sensor. If sufficient accumulated charges are generated, the integration end signal EOI is supplied to the integration time control circuit 5.

The integration time control circuit 5 generates various control signals for controlling the CCD image sensor 3 based on the control signal supplied from the main control circuit 1, the integration end signal EOI supplied from the AGC monitor circuit 4, and the like. To do.

For example, at the start of integration, a clear signal CLG is generated based on a control signal from the main control circuit 1 to discharge unnecessary charges from the storage section and CCD transfer section, and then start integration. During integration, control is performed so as to accumulate charges generated by incident light.

At the end of the integration, the integration end signal EOI from the AGC monitor circuit or the control signal from the main control circuit 1 generates the end signal TG when a certain time has elapsed, and the signal charge is stored in the CCD. Transfer to transfer unit.

FIG. 1B is an enlarged view of the portion of the accumulated charge detection circuit in the circuit of FIG. The CCD image sensor 3 has a plurality of semiconductor charge storage regions ST1 and S.
Including T2, ... An insulating film is formed on the surfaces of these semiconductor charge storage regions, and electrodes are further formed thereon to form capacitors C1, C2, .... The insulating electrode on the semiconductor surface that forms this capacitance can perform various functions, but is referred to herein as the storage gate electrode. The plurality of storage gate electrodes are commonly connected.

That is, the capacitors C1, C2, ... Are connected in parallel. The voltage of the storage gate electrodes connected in parallel is represented by VST.

The storage gate electrode is commonly connected to the wiring 9 and is supplied to the AGC monitor circuit 4 shown in FIG.
To supply. The wiring 9 is connected to the gate electrode of the MOS transistor M1 in the AGC monitor circuit 4. Therefore, the conductivity of the MOS transistor M1 is changed by the voltage VST.

The wiring 9 has analog switches 7,
8 is connected, and the voltage VSTFG or the ground voltage is selectively supplied to the capacitance C by the control signals SETA and SETB.
, C2, ... The voltage VSTFG is, for example, a predetermined positive voltage that attracts electrons.

The MOS transistor M1 is connected in series with another MOS transistor M2 and is connected between the power supply voltage VDD and the ground voltage. Other MOS transistor M
The reference voltage VB is applied to the second gate. The interconnection point between the MOS transistors M1 and M2 generates the voltage V1 and is connected to the inverting input terminal of the comparator CMP.

Other MOS transistors M3 and M4 equivalent to the MOS transistors M1 and M2 are connected in series,
Similarly, it is connected between the power supply voltage VDD and the ground voltage.
A reference voltage VB equivalent to the above reference voltage is applied to the gate of the MOS transistor M4, and a reference voltage VCMP is applied to the gate electrode of the other MOS transistor M3. The voltage V2 formed at the interconnection point between the MOS transistors M3 and M4 is applied to the non-inverting input terminal of the comparator CMP.

The output of the comparator CMP is a signal representing the magnitude relationship between the voltage VST of the commonly connected storage gate electrodes and the reference voltage VCMP. That is, the reference voltage VCMP
Is set to an appropriate value, the voltage VST gradually changes as the charge is stored in the semiconductor charge storage region ST, and the output AGCCMP of the comparator CMP changes when the voltage VST reaches a predetermined value. ..

With such a structure, the total amount of charges accumulated in the entire plurality of semiconductor charge accumulation regions ST can be accurately detected.

FIG. 2 schematically shows a configuration example of the CCD image sensor. The configuration of the semiconductor CCD image sensor is shown in a schematic sectional view in the upper part of the figure, and the potential of each part is shown in a graph in the lower part of the figure.

For example, on the surface of the p ⁻ type semiconductor substrate 11, n ⁺ type regions 12 and 13 and n ⁻ type regions 14 and 15 are formed.
Are formed in contact with each other as shown in the figure. An insulating film is formed on the surface of the semiconductor substrate 11, and a predetermined gate electrode is formed on the insulating film by using polycrystalline silicon or the like. For example, a two-layer polycrystalline silicon electrode is formed.

The n ⁺ type region 12 functions as an overflow drain OFD and is applied with a voltage OFD. This n
^An overflow gate electrode 22 is formed on a region adjacent to the ⁺ type region 12, and a voltage OFG is applied. The region adjacent to the overflow gate electrode 22 forms a photodiode PD.

A barrier gate electrode 23 is formed on the other side of the photodiode PD, and a voltage BG is applied to it. A storage gate electrode 24 is formed adjacent to the barrier gate electrode 23 and supplied with a voltage ST. Floating storage gate electrode 25 is formed in contact with a part of storage gate electrode 24, and its voltage is indicated by VST.

Since the floating storage gate electrode 25 is formed only in a part of the storage region, the capacitance becomes small,
Facilitates high speed operation. Further, if a voltage is applied to the floating accumulation gate electrode 25 and the region below it has a deep potential as shown, carriers are preferentially accumulated in this region. When the accumulated charge overflows from this area, carriers are accumulated in a wide area.
This operation corresponds to the change of the sensitivity curve, and the sensitivity is lowered for the high intensity spot light.

A clear gate electrode 26 is formed adjacent to another part of the storage gate electrode 24, and the voltage CLG
Is given. The n ⁺ type region 13 functions as a clear drain region and is supplied with the voltage CLD. That is, the accumulation region, the clear gate region and the clear drain region are F
Configure the ET structure.

A transfer gate electrode 27 is formed adjacent to another part of the storage gate electrode 24, and a voltage TG is applied thereto. The other side of the transfer gate electrode 27 is adjacent to one electrode 28 of the transfer register and transfers charges from the storage region to the transfer register. The phase signal φ1 is applied to the gate electrode 28 in the transfer register area.

The structure shown in FIG. 2 is a sectional structure in which a CCD image sensor formed in a two-dimensional distribution is cut along a certain path, and regions shown at distant positions in the drawing are Actually, it may be an adjacent area.

For example, the clear gate and the clear drain are regions formed so as to project to the side of the storage region. In the other part of the storage region, the barrier gate 23 is arranged on one side and the transfer gate electrode 27 is formed on the other side. It is arranged.

Gate electrodes 22, 23, 24, 26, 2
The potentials when a predetermined voltage is applied to 7 and 28 are shown in the lower part of the figure. The photodiode PD generates electron-hole pairs according to incident light and accumulates electrons therein.

The potential in the lower part of the figure is for electrons, and for example, when a positive voltage is applied, the potential moves downward in the figure. In the configuration shown,
The lower part of the floating storage gate electrode 25 is biased to the lowest potential.

The region below the storage gate electrode 24 is biased to a potential lower than the potential of the photodiode PD and higher than the region below the floating storage gate electrode 25. Photodiode PD, barrier gate 23,
The periphery of the region indicated by the storage gate electrode 24 is set to a high potential by the overflow gate electrode 22, the clear gate electrode 26, an oxide film, etc., and forms a potential barrier against electrons that are carriers.

Therefore, when light is incident on the photodiode PD and electric charges are generated, the generated electrons move from the portion of the photodiode PD to the accumulation region where they are accumulated while being surrounded by the potential barrier. The photodiode PD, a part of the potential barrier surrounding the storage portion, for example, the clear gate electrode 26.
By adjusting the potential of (1), the height of the potential barrier can be reduced and the accumulated charge can be extracted to the clear drain region 13.

Further, when the electric charge is accumulated even in the photodiode portion, the overflow gate electrode 22
It is also possible to draw out charges to the overflow drain region 12 by adjusting the potential of the.

By adjusting the potential of the transfer gate electrode 27, it is possible to transfer the charges accumulated in the accumulation region to the transfer register region.

The structure described above corresponds to one cell of the semiconductor photoelectric conversion device, and a large number of cells are formed on the semiconductor substrate. The floating storage gate electrodes 25 of these cells are commonly connected.

FIG. 3 is a circuit diagram showing a main part of AGC monitor circuit 4 shown in FIG. The output voltage AGCCMP of the accumulated charge detection circuit shown in FIG. 1B is applied to the clock input terminal of the D-type flip-flop DFF1. D
The power supply voltage VDD is applied to the data input terminal D of the FF1. Further, its Q output terminal is taken out through an inverter IN3 and constitutes an accumulation end signal EOI.

The two inputs of the AND circuit AND1 outputs the clear signal XCLR and the clear gate signal CLGO to the inverter I.
Upon receiving the inverted signal at N1, its output is applied to the clear input terminal of DFF1.

The signal obtained by inverting the clear gate signal CLGO with the inverter IN1 is the D-type flip-flop D.
It is applied to the clock input terminal of FF2. This DFF2
The power supply voltage VDD is applied to the data input terminal of.

The Q output terminal has a NOR circuit NOR.
Applied to one input of one. The other input terminal of NOR1 receives the transfer gate signal TG. The inverted output of NOR1 constitutes the signal SETA. AND circuit AN
D2 receives a signal obtained by inverting the clear signal XCLR and the transfer gate signal TG by the inverter IN2, and applies the output signal to the clear input terminal of DFF2.

Further, the transfer gate signal TG constitutes the signal SETB as it is through a buffer if necessary.

FIG. 4 shows the signal waveforms of the main parts in the circuits shown in FIGS. From the top to the bottom, the clear signal XCLR, the clear gate signal CLGO, the transfer gate signal TG = SETB, the other set signal SETA,
The signal waveforms of the signal VST of the floating storage gate electrode, the comparator output AGCCMP, and the integration end signal EOI are shown. In addition, the detection signal V1 shown in FIG.
And the waveform of the reference signal V2.

The clear signal XCLR changes from "1" to "0".
Signal changes to the floating storage gate electrode signal V
ST is set to the ground voltage 0V when the analog switch 8 is turned on. Further, the clear gate signal CLGO changes from "0" to "1", and the accumulated charges in the accumulation region are discharged.

Eventually, the signal SETB changes from "1" to "0".
And at the same time the signal SETA changes from "0" to "1", the analog switch 8 turns off,
When the analog switch 7 is turned on, the voltage VSTFG is applied to the floating storage gate electrode.

Subsequently, when CLGO changes from "1" to "0", the signal SETA also changes from "1" to "0", and the charge accumulation work is started. At this time,
The floating storage gate electrode is brought into a floating state, and its electric potential changes as electric charges are accumulated.

Therefore, the voltage V1 gradually changes its potential according to the amount of accumulated charges. On the other hand, the reference voltage V2 is maintained at a constant value.

When the amount of accumulated charges increases and the voltage V1 becomes equal to the voltage V2, the comparator CMP outputs the output AGC.
Change CMP. This change in signal potential appears as the voltage AGCCMP of the circuit shown in FIG.
Generate OI. That is, the integration end signal EOI is
The state of "1" changes to the state of "0".

With the generation of the integration end signal EOI, the charge accumulation in the accumulation unit is completed, and the charges accumulated in the accumulation unit are transferred to the transfer register unit via the transfer gate TG.

After the charge transfer, the signal SETB becomes “0” again, and the signal SETA changes from “0” to “1”, so that the voltage VSTFG is applied to the floating accumulation gate electrode through the analog switch 7. ..

Eventually, the signal SETA and the signal SETB change, and the floating storage gate electrode is set to the ground potential again. The signals SETA and SETB change again, and the voltage VSTFG is applied to the floating storage gate electrode.
Is applied, and then the floating state is set to start the charge accumulation operation by the incident light. This repeated operation is
This helps to set the potential of the floating storage electrode to VSTFG accurately.

In this way, the CCD as shown in FIG.
The charge storage operation of the image sensor is accurately controlled in response to the amount of charge stored in the storage region.

FIG. 5 shows the structure of an optical sensor on a semiconductor chip. FIG. 5A shows a plan view of one cell,
FIG. 5B is a plan view showing the connection state of the floating storage gate electrodes.

In FIG. 5A, the photodiode PD
Is composed of a thin n-type region formed on the surface of p-type silicon, for example. Adjacent to the photodiode PD, an n ⁻ type region having a low impurity concentration is formed, an electrode is formed on each region, and a predetermined bias voltage is applied. As a result, a buried channel CCD is formed. An n ⁺ type overflow drain OFD is formed on the left side of FIG.
^- is connected to the photodiode PD via the overflow gate OFG type region.

A barrier gate region BG forming a potential barrier is formed next to the photodiode PD, and the storage region ST is formed.
In succession. A part of the storage region ST is connected to the clear drain region CLD via the clear gate region CLG, and continues to the CCD transfer section via the other transfer gate region TG.

The CCD transfer section has four transfer stages Φ1 and Φ.
2, Φ3, Φ4. This CCD transfer section is further continuous to the floating gate region FG. The floating gate region is a charge reading region, receives the charges of the stage Φ4 of the CCD transfer section, and reads the charges induced in the floating gate formed thereon.

A part of the storage region ST is made into a floating storage region STFG, and a floating storage gate electrode is formed thereon. The potential of the storage region ST can be detected by forming an electrode that capacitively couples the potential on the storage region ST.

The storage region ST occupies a relatively large area,
Forming the floating storage gate electrode over its entire area increases its capacitance and limits its operating speed.

Therefore, as shown in FIG.
If the floating storage gate electrode STFG is formed in a part of the fixed potential and the potential is detected or a control voltage is applied, a higher speed operation becomes possible. Floating storage electrode STFG has an area of, for example, about 20% of the storage region.

Further, in the initial stage of the accumulation operation, since the charges are accumulated only under the narrow floating accumulation gate electrode STFG, the accumulated potential changes rapidly and high detection sensitivity is provided. In the latter stage of the accumulation operation, charges are accumulated in a wide area, and overflow is unlikely to occur.

When detecting light, first, the clear gate region CLG is rendered conductive, and the charge existing in the storage portion ST is extracted to the clear drain CLD. In this way, after setting the predetermined initial state, the charges generated by the light incident on the photodiode PD are stored in the storage portion ST via the barrier gate BG.

Floating storage gate electrode STFG
Are commonly connected to many cells. The correspondence of this connection is enlarged and shown in FIG. The cells of the optical sensor have, for example, two types of configurations, and two cells form one unit in terms of arrangement.

FIG. 5B shows the connection portion of the floating accumulation gate electrodes in two cells which are one unit. The floating storage gate electrode 3 is formed on a part of the storage region.
1, 32 are formed. These floating storage gate electrodes 31 and 32 are formed of, for example, polycrystalline silicon.

Further, the wiring 3 formed of, for example, aluminum or the like, which extends in the vertical direction in the figure, is shown.
3, the floating storage gate electrodes 31 and 3 are formed.
Connect 2 in common. The wiring 33 also connects the floating storage gate electrodes of the other cells in common.

Therefore, a part of the storage region STFG and the floating storage gate electrode 31 formed thereon,
32 is connected in parallel for many cells and constitutes one capacitance.

FIG. 6 is a graph showing the potential inside the photosensor along the path shown by the broken line in FIG. 5B. The operation of the optical sensor will be described below with reference to FIG.

First, in the initial state of FIG.
Light enters the photodiode PD and charges are generated, so that a certain amount of charges are accumulated in the accumulation region ST. The overflow gate OFG, the clear gate CLG, and the transfer gate T that surround the storage region
The potentials in the G region are all set high, forming a potential barrier against accumulated charges.

FIG. 6B shows the clear operation start state. When the clear operation is started, the clear gate area CL
The potential of G is changed low. Further, the potentials of the transfer gate region TG and the region of the transfer register section φ1 are also changed to be low.

On the other hand, the floating accumulation gate region ST
The potential of FG is raised high. In accordance with these potential changes, the charges accumulated in the accumulation region are discharged to the region of clear drain CLD and transfer register φ1 via clear gate CLG and transfer gate TG. After the accumulated charge is discharged, the clear completion operation shown in FIG. 6C is performed.

In the clear completion operation shown in FIG. 6C, the potential of the floating storage gate region STFG is changed to a low level to attract the generated electrons, and the potentials of the clear gate region CLG and the transfer gate TG pass through the electrons. Set high to shut off.

Also, the potential of the transfer register area is set high. After that, the floating storage gate region STF
Although the potential of G is removed, since the floating storage gate electrode is brought into a floating state, the potential of the floating storage gate region STFG is kept as it is, and a deep potential well is formed.

FIG. 6D shows the potential distribution in the charge storage state. When light is incident on the photodiode PD, an electron-hole pair is generated, and an electron of the electron-hole pair flows into the storage region ST from the photodiode PD.

The accumulated electrons are first accumulated in the floating accumulation gate region STFG having a low potential. When the accumulated charge gradually increases, the accumulated charge gradually spreads from the floating accumulation gate region STFG region to the accumulation region ST and the photodiode PD region and accumulated.

The accumulated charge amount is detected as an average of a large number of cells in the photosensor via the floating accumulation gate electrode. When the detected accumulated charge amount reaches a predetermined value, the charge accumulation operation ends and the reading operation is performed.

FIG. 6E shows the potential distribution in the reading operation. Floating storage gate electrode S
The potential of TFG is controlled from the outside and set high. On the other hand, the potential of the transfer gate region TG changes low,
The charges accumulated in the accumulation region are transferred to the transfer register unit via the transfer gate region TG. In this way, the accumulated charges that have reached the desired accumulation amount are transferred to the transfer register section and read out as signal charges.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0109]

As described above, according to the present invention,
Accurate detection of the accumulated charge can be performed by directly reading the amount of charge accumulated in the charge accumulation region of the optical sensor via the capacitor.

For example, in an optical sensor including a large number of cells, even if there is an extremely bright region in a part, it is possible to accurately detect the accumulated charge as a whole.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. 1A is a block diagram showing an image sensor circuit, and FIG. 1B is a circuit diagram of an accumulated charge detection circuit.

FIG. 2 is a cross-sectional view showing a configuration example of a CCD image sensor and a graph showing a potential distribution.

FIG. 3 is a block diagram showing a configuration example of a control circuit.

FIG. 4 is a graph showing a signal waveform in a main part of the circuits shown in FIGS. 1 and 3.

FIG. 5 shows an optical sensor. FIG. 5A is a plan view showing the photosensor for one cell, and FIG. 5B is a plan view showing the connection of the floating storage gate electrodes in more detail.

FIG. 6 is a diagram illustrating an operation. 6A to 6B
[Fig. 3] is an energy band diagram showing a potential distribution in the optical sensor.

FIG. 7 shows a conventional technique. FIG. 7A is a block diagram showing the main part of a conventional focus detection device, and FIG.
7B is a cross-sectional view showing another example of the optical sensor, and FIG. 7C is a circuit diagram of the overflow detection unit.

[Explanation of symbols]

1 main control circuit 2 CCD drive circuit 3 CCD image sensor 4 AGC monitor circuit 5 integration time control circuit 7, 8 analog switch 11 semiconductor substrate (p ⁻ type) 12, 13 n ⁺ type region (diode) 14, 15 n ⁻ type Region 22 to 28 Insulated gate electrode PD Photodiode C Capacitance M Transistor CMP Comparator OFG Overflow gate BG Barrier gate ST Storage unit CLG Clear gate CLD Clear drain TG Transfer gate

Claims (8)

[Claims] 1. A photoelectric conversion means for generating charges in response to incident light, and a semiconductor charge storage region for accumulating the charges generated by the photoelectric conversion means, which can be surrounded by a potential barrier. A storage gate electrode capacitively coupled to the semiconductor charge storage region, a storage potential detection unit for detecting the potential of the storage gate electrode, and a storage gate electrode stored in the semiconductor charge storage region based on the potential of the storage gate electrode. And a means for generating a control signal for controlling the electric charge. 2. The semiconductor photoelectric conversion device according to claim 1, wherein the storage gate electrode is formed only on a partial surface of the semiconductor charge storage region. 3. The photoelectric conversion means includes a plurality of semiconductor photoelectric conversion cells formed in a semiconductor substrate, and the semiconductor charge storage region corresponds to each of the plurality of semiconductor photoelectric conversion cells in the semiconductor substrate. 3. The semiconductor photoelectric conversion device according to claim 1, comprising a plurality of semiconductor storage regions formed in. 4. The storage gate electrode is formed on each of the plurality of semiconductor charge storage regions, and the storage potential detecting means includes a single common electrode commonly connected to these storage gate electrodes. The semiconductor photoelectric conversion device described. 5. The semiconductor photoelectric conversion device according to claim 4, further comprising means for selectively applying a voltage to the storage gate electrode for selectively eliminating stored charges. 6. An insulating transfer gate electrode arranged adjacent to the semiconductor charge storage region for controlling a part of the potential barrier, and an insulating transfer gate electrode arranged adjacent to the insulating transfer gate electrode. The semiconductor photoelectric conversion device according to claim 1, further comprising a transfer register for receiving and transferring the charges accumulated in the charge accumulation region. 7. An insulating clear gate electrode disposed adjacent to the semiconductor charge storage region for controlling a part of the potential barrier; and an insulating clear gate electrode disposed adjacent to the insulating clear gate electrode. The semiconductor photoelectric conversion device according to claim 1, further comprising a clear drain region for receiving and discharging charges accumulated in the charge accumulation region. 8. The storage gate electrode is applied with a voltage of a predetermined magnitude with a polarity for attracting the charge to be stored before the charge storage is started, and then the storage gate electrode is floated during the charge storage. The semiconductor photoelectric conversion device according to any one of claims 1 to 7, further comprising a control unit for setting a state.