JPH0591077A - Digital data demultiplexing method and circuit able to absorb destuff jitter - Google Patents

Abstract

PURPOSE:To eliminate a data error by allowing an analog IC to implement D/A conversion to a low group signal subject to smooth by a smoothing buffer memory after re-smoothing. CONSTITUTION:The high order group signal HS of frame configuration is demultiplexed into a low order group signal by a demultiplex circuit 1, a pulse subject to stuffing is subject to destuffing and the result is outputted as a low order group signal LS. A smoothing buffer memory 2 writes the signal LS subject to destuffing synchronously with a write clock WRCLK and reads the signal synchronously with a read clock RDCLK and the result is outputted as a signal MS. An analog IC3 receives the signal MS from the memory 2 and uses a built-in memory 5 to implement smoothing and to apply D/A conversion to the signal and the result is outputted to a transformer 4 synchronously with the RDCLK from the DMUX 1. Since the memory 2 acts like reducing jitter in advance, no error takes place in the signal data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data separating method capable of absorbing destuffing jitter in a digital multiplexer and its circuit.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing an example of a conventional digital data separation circuit.

Demultiplex circuit 51 (hereinafter D
The MUX 51) inputs a high-order group signal having a frame structure and demultiplexes it into a low-order group signal. The analog IC 53 uses the built-in memory 55 for DMUX 5
After the signals separated in 1 are input and smoothed, digital / analog conversion is performed. The transformer 54 performs unipolar / bipolar conversion based on the output of the analog IC 53.

[0004]

The above-mentioned conventional digital data separation circuit is affected by the jitter absorption characteristics of the analog IC, and when it receives jitter exceeding its capability,
It has the drawback of causing errors in the data.

In view of the above-mentioned drawbacks, it is an object of the present invention to provide a digital data separating method and circuit which do not generate an error even when receiving data exceeding the jitter absorption characteristic of an analog IC.

[0006]

The digital data separation method of the present invention comprises a first step of demultiplexing a frame-configured high-order group signal into a low-order group signal, and demultiplexing by a demultiplexing. Write the low-order group signal to the buffer memory for smoothing,
The second step of digitally smoothing the jitter that periodically occurs in the low-order group signal by reading in synchronization with the clock signal and the re-smoothing of the low-order group signal smoothed by the smoothing buffer memory After that, the third step of digital / analog conversion and the fourth step of unipolar / bipolar conversion of the digital / analog converted signal are performed.

Further, the digital data separation circuit of the present invention includes a demultiplex circuit for inputting a frame-configured high-order group signal and separating it into a low-order group signal, and a low-order group separated by the demultiplex circuit. Buffer memory for digitally smoothing the jitter that periodically occurs in the signal, and an analog IC that performs digital / analog conversion after re-smoothing the low-order group signals smoothed by the smoothing buffer memory It is composed of a transformer for unipolar / bipolar conversion of a signal digital / analog converted by an IC.

Preferably, the smoothing buffer memory reads the low-order group signals in synchronization with a read clock different from the write clock for writing the low-order group signals. More preferably, the smoothing buffer memory performs a FIFO operation, and the analog I
C has a built-in memory for re-smoothing,
Re-smoothing is performed in synchronization with the read clock.

In the present invention, "smoothing" means arranging pulse trains, which are not arranged at equal intervals by destuffing the stuffed signals, at equal intervals.

[0010]

The smoothing buffer memory digitally smoothes the jitter periodically generated in the low order signal separated from the high order signal by the demultiplexing circuit. The analog IC re-smooths the low-order group signals smoothed by the smoothing buffer memory, then performs digital / analog conversion, and outputs a low-order group signal without jitter through a transformer.

Therefore, even if the destuffing jitter generated during demultiplexing exceeds the jitter absorption capability of the analog IC, the smoothing buffer memory does not cause an error in the data due to the smoothing performed in advance.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. 2 is a block diagram showing an embodiment of a digital data separation circuit of the present invention, FIG. 3 is a block diagram showing an example of an integrated circuit usable in the embodiment of FIG. 2, and FIG. It is a block diagram showing the case of a system.

Demultiplex circuit 1 (hereinafter DM
UX1) is a signal H of a frame-configured high-order group.
S is separated into low-order group signals, the stuffed pulse is destuffed, and the low-order group signals LS are output together with the write clock WRCLK and the read clock RDCLK.

The buffer memory 2 for smoothing writes the destuffed signal LS in synchronization with the write clock WRCLK, reads the written signal LS in synchronization with the read clock RDCLK, and outputs it as a signal MS. The writing and reading are performed by the FIFO operation.

Therefore, the jitter periodically generated by the separation by the DMUX 1 is digitally smoothed.

The analog IC 3 inputs the signal MS from the buffer memory 2, performs smoothing using the built-in memory 5, performs digital / analog conversion, and outputs the signal to the transformer 4 in synchronization with the read clock RDCLK from the DMUX 1. The transformer 4 performs unipolar / bipolar conversion on the output signal of the analog IC 3.

Therefore, even if the high-order group signal HS contains a jitter that exceeds the jitter absorption capability of the analog IC 3, the buffer memory reduces the jitter in advance, so that no error occurs in the signal data.

Further, a specific example of the analog IC 3 will be described. As a typical analog IC3, FIG.
There is T7290 (or T5290) of AT & T Co. shown in FIG. In this case, the read clock RDC of the embodiment of FIG.
LK may be supplied as Transmit clock (see *) and signal data MS may be supplied as Transmit data (see *).

When the signals of the high-order group are separated into the signals of the four low-order groups, it may be constructed as shown in FIG.

DMUX 11 is a low-order group signal D of four systems.
Write clock WR for 1, D2, D3 and D4 respectively
1, WR2, WR3, WR4 and read clock RD
It is output together with 1, RD2, RD3 and RD4. The buffer memories 21, 22, 23, 24 for smoothing are
The signals D1, D2, D3 and D4 are smoothed, and the analog ICs 31, 32, 33 and 34 are smoothed again. The re-smoothed signal is digital-to-analog converted, and then the transformers 41, 42, and 4 respectively.
It is output via 3, 44.

The buffer memories 21, 22, 23,
24 DO + and DO- are made to correspond to the positive polarity signal and the negative polarity signal of the bipolar signal, respectively.

[0022]

As described above, according to the present invention, by providing the buffer memory in the preceding stage of the analog IC,
Destuff jitter generated during DMUX is analog IC
Even if it exceeds the jitter absorption capability of the above, it has the effect of eliminating the data error while having the resistance to the destuff jitter.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional example.

FIG. 2 is a block diagram showing an embodiment of a digital data separation circuit of the present invention.

FIG. 3 is a block diagram showing an example of an analog IC that can be used in the embodiment of FIG.

FIG. 4 is a block diagram showing an embodiment in the case where the low-order group signal data is of four systems.

[Explanation of symbols]

 1,11 DMUX (demultiplex circuit) 2,21,22,23,24 Buffer memory 3,31,32,33,34 Analog IC 4,41,42,43,44 Transformer 5 Built-in memory of analog IC

Claims (5)

[Claims] 1. A first step of demultiplexing a frame-configured high-order group signal into a low-order group signal, and a low-order group signal separated by demultiplexing in a smoothing buffer memory. By writing and reading in synchronization with the clock signal, the second step of digitally smoothing the jitter that periodically occurs in the low-order group signal and the low-order group signal smoothed by the smoothing buffer memory After re-smoothing, digital /
A digital data separation method comprising a third step of analog-to-analog conversion and a fourth step of unipolar / bipolar conversion of a digital / analog-converted signal. 2. A demultiplex circuit for inputting a frame-configured high-order group signal and separating it into a low-order group signal, and a jitter which is periodically generated in the low-order group signal separated by the demultiplex circuit. After smoothing the buffer memory for smoothing digitally, and the low-order group signals smoothed by the buffer memory for smoothing,
A digital data separation circuit consisting of an analog IC for analog conversion and a transformer for unipolar / bipolar conversion of the signal digital / analog converted by the analog IC. 3. The smoothing buffer memory comprises:
3. The digital data separation circuit according to claim 2, wherein the low-order group signals are read in synchronization with a read clock different from a write clock for writing the low-order group signals. 4. The smoothing buffer memory comprises:
4. The digital data separation circuit according to claim 2, which performs a FIFO operation. 5. The digital data separation circuit according to claim 3, wherein the analog IC has a built-in memory for performing re-smoothing, and performs re-smoothing in synchronization with the read clock.