JPH0590212A - Dry etching device - Google Patents

Abstract

PURPOSE:To effectively conduct an etching treatment on the wafers in a plurality of reaction chambers in a short period of time by providing a plurality of reaction chambers, and housing parts, a spare chamber, a transfer means and a control section where an instruction signal, with which a sequence program is carried out by a sequencer. CONSTITUTION:A wafer 10 is moved between a plurality of reaction chambers 11 to 13 and an auxiliary chamber 16 in a vacuum state. The wafer 10 is moved between the auxiliary chamber 16 and wafer housing sections 19 and 20 in a state of atmosphere of nitrogen gas. The title etching device is provided with a sequencer 5, with which the wafer 10 is carried by a transfer means 5b and an etching treatment is conducted on untreated wafers in the reaction chambers 11 to 13, and a control section 1 which outputs an instruction signal for carrying out a sequence program when the execution condition is satisfied after the process treatment is started based on the execution condition for carrying out the treated wafer, transferring the untreated wafer to the reaction chamber 11 to 13 in a shortest time to be subjected to an etching treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique by dry etching, and more particularly to a dry etching apparatus for performing a wafer etching process in a plurality of reaction chambers.

[0002]

2. Description of the Related Art In the manufacture of semiconductors such as VLSI and ULSI, there is a demand for a dry etching apparatus having a reaction chamber capable of performing a high degree of process treatment along with high integration and miniaturization.

As an example of this dry etching apparatus,
The one shown in FIG. 8 is known.

This dry etching apparatus is equipped with a wafer 10
Is equipped with one reaction chamber 21 for performing the etching process of
This reaction chamber 21 is connected to the auxiliary chamber 2 via the reaction chamber gate 21a.
It is connected to 2. A double arm 23 for exchanging the wafer 10 is provided in the preliminary chamber 22,
The spare room gate 22a is provided. A wafer chuck arm 18 and an orientation flat stage 18a for aligning the orientation flat of the wafer 10 are arranged in front of the preliminary chamber gate 22a. Further, on both sides of the wafer chuck arm 18, wafer cassettes 19 and 20 for accommodating the wafer 10 are arranged.

Next, the operation of the dry etching apparatus will be described.

First, the wafer chuck arm 18 takes out the wafer 10 from one of the wafer cassettes 19 and 20 and places it on the orientation flat stage 18a. When the orientation flat stage 18a receives the wafer 10, it rotates the orientation flat stage 18a to detect the orientation flat and perform positioning. When this positioning is completed, the preliminary chamber 22 is brought to the atmospheric state with nitrogen gas, and the preliminary chamber gate 22a is opened. Then, the double arm 23 exchanges the wafer 10 in the preliminary chamber 22 with the wafer 10 on the orientation flat stage 18a, and closes the preliminary chamber gate 22a.

By this exchange, the orientation flat stage 18a
The wafer 10 that has been taken out is inserted into a fixed position of the wafer cassette 19 or 20 by the wafer chuck arm 18. After the replacement, the double arm 23 is rotated to the reaction chamber 21 side, and the preliminary chamber 22 is set to a high vacuum, and the reaction chamber 2
When the process 1 is finished, the reaction chamber gate 21a is opened, and the wafer 1 in the reaction chamber 21 and the preliminary chamber 22 is opened by the double arm 23.
Exchange 0. Then, the reaction chamber gate 21a is closed and the double arm 23 is rotated to face the orientation flat stage 18a.

In the reaction chamber 21, dry etching is carried out while controlling the flow rate of reaction gas, the degree of vacuum, the RF discharge and the temperature according to the set etching conditions.

[0009]

By the way, in the above-mentioned conventional dry etching apparatus, the number of reaction chambers 21 is one, and the unprocessed wafer 10 reacts from the wafer cassette 19 or 20 through the orientation flat stage 18a and the preliminary chamber 22. Room 21
The processed wafer 10 is an unloading path from the reaction chamber 21 to the preparatory chamber 22 and the orientation flat stage 18a and back to the wafer cassette 19 or 20.

Since the sequence of such a transfer process controls only a single path, it can be executed by a simple sequence program. However, in order to improve the production efficiency, a plurality of reaction chambers 21 are provided and dry etching is performed. In such a case, the transfer route of the wafer 10 becomes considerably complicated, and the problem remains that the above sequence control cannot be applied.

An object of the present invention is to solve the above problems.

[0012]

According to the present invention, in order to achieve the above object, a plurality of reaction chambers for etching a wafer and a wafer container for supplying an unprocessed wafer and receiving a processed wafer. The chamber is connected to each of the reaction chambers, and when the wafers are transferred to and from the wafer storage unit, the chamber is kept in an atmospheric state with nitrogen gas, and when the wafers are transferred to and from the reaction chambers, the chambers are kept at a high temperature. A preliminary chamber for maintaining a vacuum state, a transfer means for transferring a wafer between the wafer storage unit and each reaction chamber through the preliminary chamber, wafer transfer by this transfer means, and etching processing of unprocessed wafers in each reaction chamber A sequencer that executes a plurality of sequence programs, and the unprocessed wafer is transferred to the reaction chamber in the minimum time to perform etching processing, and the processed wafer is unloaded. Based on the execution condition set in advance to so that, when the execution conditions after the process processing start is satisfied, and a control unit that performs control for sending a command signal for executing the sequence program to said sequencer,
It is characterized by having.

[0013]

In the present invention, execution conditions are set in advance so that an unprocessed wafer is transferred to the reaction chamber in the minimum time to perform etching processing and the processed wafer is unloaded.

When the dry etching apparatus is operated, the control section sends a command signal to the sequencer to execute the sequence program, and the process processing is started. Then, the unprocessed wafer is transferred from the wafer storage section to the preliminary chamber. At this time, the preliminary chamber is kept in the atmospheric state by nitrogen gas.

Subsequently, the preliminary chamber is maintained in a high vacuum state,
An unprocessed wafer is supplied from the preliminary chamber to the reaction chamber, and the wafer is dry-etched.

In the progress of this etching process,
The control unit continues to send command signals to the sequencer, and carries out control so that unprocessed wafers are carried into the reaction chamber in the minimum time based on preset execution conditions, etching processing is performed, and processed wafers are carried out. ..

For this reason, during the etching process, even if the processing time varies depending on the type of wafer and the etching conditions, the reaction chamber where the etching process is completed is
Since the unprocessed wafers are supplied in a short time, the wafers can be transferred to the plurality of reaction chambers without loss time, and the efficiency of the etching process can be improved.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an electrical block diagram showing a control unit of the dry etching apparatus.

In this dry etching apparatus, wafers 1 are placed in a plurality of reaction chambers 11 to 13 from a wafer cassette 19 or 20 which is a wafer storage unit through a preliminary chamber 16 and a transfer chamber 14.
The process of carrying 0 to carry out the etching process is controlled by giving a command from the control unit 1 to the sequencers 5 to 8.

The control unit 1 is a CPU (central processing unit) and includes a writing unit 1a, a reading unit 1b, a computing unit 1c, a judging unit 1d and an output unit 1e.
The writing means 1a is for writing data in the memory 3, and is connected to the input means 2 for performing setting operation such as etching process order. The writing means 1a is connected to the memory 3 for storing the setting input from the input means 2 and various data. A reading means 1b for reading data is connected to the memory 3. This reading means 1b
Is connected to a computing means 1c that controls the operation of the entire apparatus. In this example, the arithmetic means 1c performs sequence control based on the setting signal, and also performs arithmetic processing for receiving a process processing information given during operation and searching for an executable sequence.

The calculating means 1c is connected to the writing means 1a and is connected to the judging means 1d. This judging means 1d judges the step number and the like, and
A command signal for executing the sequence program is output based on the calculation result of the calculation means 1c.
The judging means 1d is connected to the output means 1e which sends a command signal to the sequencers 5-8. The output means 1e is connected to the CRT 4 and also to the transport system sequencer 5, the first reaction chamber sequencer 6, the second reaction chamber sequencer 7 and the third reaction chamber sequencer 8.

The transfer system sequencer 5 is a sequence board for sequence-controlling the transfer of the wafer 10 between the wafer cassettes 19 and 20, which will be described later, and the reaction chambers 11 to 13 via the auxiliary chamber 16 and the transfer chamber 14. And
The detection signal from the sensor 5a is guided and sends a control signal to the actuator 5b. The first reaction chamber sequencer 6 is a sequence board that controls the etching process of the wafer 10 in the first reaction chamber 11 in sequence. The detection signal from the sensor 6a is introduced to the control board 6 and sends the control signal to the actuator 6b. The second reaction chamber sequencer 7 is a sequence board that controls the etching process of the wafer 10 in the second reaction chamber 12 in sequence, receives the detection signal from the sensor 7a, and sends the control signal to the actuator 7b. The sequencer 8 for the third reaction chamber is a sequence board that controls the etching process of the wafer 10 in the third reaction chamber in sequence, and guides the detection signal from the sensor 8a and sends the control signal to the actuator 8b. ing.

These sequencers 5 to 8 have respective sensors 5a.
The wafers 10 are loaded and unloaded in accordance with a predetermined route by driving the actuators 5b to 8b in response to the detection signals output from the to 8a. However, this transfer process is configured to be executed by a plurality of sequence programs. There is.

FIG. 2 is a schematic configuration diagram of the dry etching apparatus.

This dry etching apparatus is equipped with a wafer 10
It is equipped with three reaction chambers for carrying out the etching treatment. First
Each of the third to third reaction chambers 11 to 13 is provided with a reaction chamber gate 11a, 12a, 13a, and each reaction chamber gate 11a to 13a is connected to the transfer chamber 14. A double arm 15 for exchanging the wafer 10 is arranged in the transfer chamber 14. A preliminary chamber 16 is connected to the transfer chamber 14 via a transfer chamber gate 14a. The preliminary chamber 16 has an orientation flat stage 17 for detecting the orientation of the wafer 10 and performing alignment.
Is equipped with.

In front of the preliminary chamber 16, the wafer 1
A wafer chuck arm 18 for taking out 0 is arranged. Further, two wafer cassettes 1 for accommodating the wafers 10 are provided on both sides of the wafer chuck arm 18.
9 and 20 are arranged.

Thus, in the dry etching apparatus thus constructed, when the wafer 10 is transferred between the wafer cassette 19 or 20 and the spare chamber 16 as in the conventional case, the inside of the spare chamber 16 is filled with nitrogen gas. Maintained in atmospheric conditions. On the other hand, when the wafer 10 is transferred between the reaction chambers 11 to 13 via the preliminary chamber 16 and the transfer chamber 14, the inside of the preliminary chamber 16 is kept in a high vacuum state. In each of the reaction chambers 11 to 13, dry etching is performed while controlling the flow rate of the reaction gas, the degree of vacuum, the RF discharge, the temperature, etc., according to preset etching conditions.

Then, the sequence processing contents (see Table 1)
When the dry etching apparatus is activated by setting a sequence execution condition (see Table 5) and the like, the control unit 1 executes an automatic scheduling task, a schedule control task, a wafer task, etc. by performing task control. Specifically, the automatic scheduling task creates the sequence schedule table (see Table 2), the wafer task creates the wafer sequence table (see Table 3), the wafer information table (see Table 4), etc. Upon receiving the changing process processing information, the etching processing operation that minimizes the throughput is performed.

Next, the etching processing operation of this dry etching apparatus will be described with reference to the flow chart.

First, when the dry etching apparatus is operated, the sequence processing number, the transfer process number and the wafer retention position number are preset by the input means 2. In this case, when the contents of the sequence processing are input under the conditions shown in Table 1, the processing order is written in the memory 3 so that the process processing shown in FIG. 3 is performed. The order for performing the etching process on the wafer 10 can be set arbitrarily, but in this example, the order is set to the first reaction chamber 11, the second reaction chamber 12, and the third reaction chamber 13.

[0032]

[Table 1]

Next, when the dry etching apparatus is operated, the automatic scheduling task and the schedule control task are activated.

The automatic scheduling task reads out the processing sequence number, the transfer process number, and the retention position number of the wafer 10 together with the etching order stored in advance in the memory 3, and the calculation means 1c performs the calculation.

Then, after executing the flow chart shown in FIG. 5 to create the sequence schedule table shown in Table 2 (step S51), the wafer task is activated (step S52).

[0036]

[Table 2]

Then, the automatic scheduling task reads the step number of the activated wafer task from the memory 3 and judges by the judging means 1d whether or not the step number becomes 2 (step S53). Here, after the operation is started and the step number becomes 1, the wafer 10 is transferred to the preliminary chamber 16, and then it is checked whether the wafer 10 is transferred from the preliminary chamber 16 to the transfer chamber 14.

At this time, if the step number is 2, it is determined whether or not there is another wafer 10 (step S5).
4). Here, if there is no wafer 10, the process processing ends, but if there is a wafer 10, the next wafer task is activated (step S55). Then, the process proceeds to step S53, and the flow of FIG. 4 is repeated.

By the way, the wafer task activated as described above executes the flowchart shown in FIG. 6 to create the wafer sequence table shown in Table 3.

[0040]

[Table 3]

Then, in this wafer task, 1 is assigned to the step number and 0 is assigned to the state flag, and the state flag is written in the memory 3 (step S61).

Also, the step number is transmitted to the schedule control task (step S62).

Then, it is judged whether or not the state flag becomes 1, and if the state flag becomes 1 (step S63),
Wait for the status flag to change to 0. Here, when the status flag becomes 0 (step S64), the step number is read from the memory 3 and the judgment means 1d judges.

After this, it is judged whether or not the step number has become N, that is, whether the final processing has been completed (step S65).

At this time, if it is not the final process, the process proceeds to step S62 to continue the process, but if the step number becomes N, the process is ended.

By the way, the schedule control task started together with the above-mentioned automatic scheduling task executes the processing shown in the flowchart of FIG.
First, it is determined whether or not there is any sequence that has ended (step S71).

At this time, if none of the sequence ends, the process proceeds to step S74. If the sequence ends, 1 is added to the step number of the corresponding wafer task and the wafer retention position table is updated (step S7).
2).

Then, after setting the status flag of the corresponding wafer task to 0 (step S73), it is determined in step S74 that the step number is transmitted.

When the step number transmitted from the wafer task is received (step S74), the schedule control task reads the step number from the memory 3, and the schedule table in Table 2 and Table 4 above.
A feasible sequence is searched from the wafer information table shown in FIG. 5 and the sequence execution conditions of Table 5 (step S7).
6).

[0050]

[Table 4]

[0051]

[Table 5]

Here, it is determined whether or not there is a feasible sequence (step S77), and if there is no feasible sequence, the process proceeds to step S71, and if there is a feasible sequence, the status flag of the corresponding wafer task is set to 1. ,
The wafer retention position table is updated (step S7).
8).

Thereafter, a command signal is output to the sequencer (step S79), and the process returns to step S71 to repeat the same operation as above.

For example, assuming that the processing progresses in the above process and the state shown in FIG. 4 is assumed, the six wafers No. 1 to No. 1 transferred to this dry etching apparatus are processed.
The state of No6 is as follows.

Wafer No. 1 Etching is being performed in the third reaction chamber 13.

Wafer No2. The movement from the second reaction chamber 12 to the transfer chamber 14 is completed, and the movement to the third reaction chamber 13 is awaited.

Wafer No. 3. After the etching process is completed in the second reaction chamber 12, the transfer chamber 14 is waiting to be moved.

Wafer No. 4. After the etching process is completed in the first reaction chamber 11, the transfer chamber 14 is waiting to be moved.

Wafer No. 5 When the transfer from the wafer cassette 19 to the preliminary chamber 16 is completed, the transfer to the transfer chamber 14 is awaited.

Wafer No.6. Waiting for transfer to the spare room 16.

At this time, the wafer sequence table of each wafer task is shown in Table 6 and the wafer information table is shown in Table 7.
The state has changed to.

Here, each wafer task will be described. Wafer task No. 1. Since the step number is not 14 (the position of the wafer cassettes 19 and 20), the step number 10 is transmitted to the schedule control task and the status flag becomes 0.

Wafer task No. 2. Step number is 14
Therefore, it sends the step number 9 to the schedule control task and waits for the status flag to become 1.

Wafer task No. 3. Step number is 14
Therefore, step number 8 is transmitted to the schedule control task and the status flag is set to 1 and is waiting.

Wafer task No. 4. Step number is 14
Therefore, step number 5 is sent to the schedule control task and the status flag is set to 1.

Wafer task No. 5. Step number is 14
Therefore, it sends the step number 2 to the schedule control task and waits for the status flag to become 1.

Wafer task No. 6. 1 for step number
Is assigned to the status flag, step number 1 is transmitted to the schedule control task, and the status flag is waiting for the status flag to become 1.

[0068]

[Table 6]

[0069]

[Table 7]

As for the schedule control task, all executable sequences are searched, and an example thereof is as follows.

.. When the wafer task 2 sends the step number 9, the process (3) is read from the position of step 9 in the sequence schedule table of Table 8, and the current stay position is read as the destination stay position.

.. When the step number 8 is transmitted from the wafer task 3, the process (4) is read from the position of step 8 in the sequence schedule table of Table 6, and the current stay position is read as the move destination stay position is.

.. When the wafer task 4 transmits the step number 5, the process (4) is read from the position of step 5 in the sequence schedule table of Table 6 and the current stay position is read as the move destination stay position.

.. When the step number 2 is transmitted from the wafer task 5, the process (2) is read from the position of step 2 in the sequence schedule table of Table 6, and the current stay position is read as the move destination stay position is.

.. When the step number 1 is transmitted from the wafer task 6, the process (1) is read from the position of step 1 in the sequence schedule table of Table 6, and the current stay position is read as the move destination stay position is.

.. When there is a request for step (1), if the presence or absence of a wafer at the wafer retention position is searched in the wafer information table of table 8 from the sequence execution conditions of table 5 created in advance, there is a wafer, so sequence 1 of step (1)
Determines that cannot be executed.

.. When there is a request for step (2), if the presence or absence of a wafer at the wafer retention position is searched from the wafer information table in Table 8 above from the sequence execution conditions,
Since there is a wafer but there is no request for step (5), it is determined that sequence 3 cannot be executed.

.. When there is a request for step (3), if the presence or absence of a wafer at the wafer retention position is searched from the above-mentioned sequence execution conditions in the wafer information table, the wafer retention position for which step (4) is requested is Therefore, it is determined that the sequence 6 cannot be executed.

.. When there is a request for step (4), if the presence / absence of a wafer at the wafer retention position and the presence / absence of a wafer at the wafer retention position (no reservation) are searched from the sequence execution condition in the wafer information table, the wafer at the wafer retention position is searched. Since there is no request for step (3) in which n of steps is equal, it is determined that sequences 4 and 5 cannot be executed. Therefore, it can be said that there is currently no new startup sequence.

[0080]

[Table 8]

Next, the first to third reaction chambers 11 to 13
When the etching sequence No. 2 of No. 1 is completed, the sequencer 5 to 8 informs the schedule control task of the end of the sequence, and the status flag of the wafer sequence table of wafer task No. 1 is set to 0 and the step number is set to 1.
1, the in-process flag of the wafer information table is 0, and the process completion flag is 1 (see Table 9).

[0082]

[Table 9]

Since the status flag of wafer task No. 1 has become 0, step number 11 is transmitted.

Since the schedule control task sends the step number 11, the process is (4) from the position of the step number 11 in the sequence schedule table of Table 6, the current stay position is the stay position of the destination. Then, the executable sequence is searched for in the same manner as above.

In this case, since the process (4) of wafer task No. 1 and wafer task 4 is possible, task No.
1, the simultaneous movement sequence No. 8 is set to 6, the state flag is set to 1 (see Table 10), and the sequence is output to the corresponding sequencer 5 to 8. Hereinafter, the processing is executed in the same procedure as above.

[0086]

[Table 10]

As described above, according to this embodiment, the throughput can be minimized by the task management, and the sequencers 5 to 8 which operate based on this sequence control.
When the wafer 10 is being transported during the etching process by executing the sequence program, if there is a reaction chamber where the etching process is completed, the wafer 1
0 will be sent and will be carried out by exchange. Further, the wafers 10 that are sequentially transferred are reserved during standby and are immediately sent to the processed reaction chambers, so that the wafers 10 can be transferred to the three reaction chambers without loss time, and the wafers 10 can be transferred to the three reaction chambers without loss time. The etching process becomes faster.

[0088]

As described above, according to the present invention, the control section sends the command signal to the sequencer to execute the sequence program, and the unprocessed wafer is placed in the reaction chamber in the minimum time based on the preset execution condition. Since the control is performed so that the wafers are carried to perform the etching process and the processed wafers are carried out, the unprocessed wafers are always supplied in a short time to the reaction chamber where the etching process is completed. Therefore, since the wafers can be transferred to the plurality of reaction chambers without loss time, the efficiency of the etching process can be improved.

[Brief description of drawings]

FIG. 1 is an electrical block diagram of a control unit according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a dry etching apparatus.

FIG. 3 is an explanatory diagram showing a process treatment of a dry etching apparatus.

FIG. 4 is an explanatory diagram showing the position of a wafer in a dry etching apparatus.

FIG. 5 is a flowchart illustrating the operation of an automatic scheduling task.

FIG. 6 is a flowchart illustrating an operation of a wafer task.

FIG. 7 is a flowchart illustrating the operation of a schedule control task.

FIG. 8 is a schematic configuration diagram of a conventional dry etching apparatus.

[Explanation of symbols]

 1 Control Part 3 Memory 5 Transfer System Sequencer 5b Actuator 10 Wafer 11 First Reaction Chamber 12 Second Reaction Chamber 13 Third Reaction Chamber 19 Wafer Cassette 20 Wafer Cassette

Claims (1)

[Claims] 1. A plurality of reaction chambers for performing a wafer etching process, a wafer storage unit for supplying an unprocessed wafer and receiving a processed wafer, and a wafer storage unit connected to each of the reaction chambers. A preliminary chamber that keeps the chamber in an atmospheric state with nitrogen gas when transferring wafers between them, and keeps the chamber in a high vacuum state when transferring wafers to and from the reaction chamber,
A transfer unit that transfers a wafer between the wafer storage unit and each reaction chamber through the preliminary chamber, and a transfer of the wafer by the transfer unit and an etching process of an unprocessed wafer in each reaction chamber according to a plurality of sequence programs. Based on the sequencer and the execution conditions set in advance to carry out the etching process by carrying the unprocessed wafer to the reaction chamber in the minimum time and carry out the processed wafer, this execution condition is satisfied after the process process is started. And a control unit for controlling the sequencer to send a command signal for executing a sequence program.