JPH0589605A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To enable a digital signal reproducing device which is constituted so that original digital signals can be detected from reproduced RF signals to accurately and quickly detect the original digital signals with a small-scale circuit without performing any waveform equalization on the reproduced RF signals. CONSTITUTION:A series of data converted from reproduced RF signals by means of an A/D converter 27 are held in a plurality of latches 28a-28c of a latch group 28. By using the held series of data as address information, a memory 29 is accessed in which numerous data patterns PT corresponding to the level of the reproduced RF signals are stored. Therefore, the original digital signals are detected by selectively reading out a specific data pattern out of the numerous data patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus suitable for reproducing a digitized video signal or the like.

[0002]

2. Description of the Related Art As is well known, a commercially available optical video disc recording system is a CA in which the disc rotation speed is constant.
There are a V recording method and a CLV recording method in which the linear velocity is constant on the inner and outer circumferences of the disc. The CLV type disc can obtain, for example, twice as long playing time as the CAV type disc. On the other hand, in the CAV type disc, an image of one frame is recorded per track of the track, and by making the reproduction light beam jump between the tracks, various kinds of slow reproduction, still image, double speed reproduction, reverse rotation, etc. Special reproduction can be easily performed.

By the way, conventionally, a video signal is digitized and recorded and reproduced in real time on a medium of high density and large capacity such as a magneto-optical (MO) disk. In this case, a high data transfer rate is required, but in order to reduce the transfer rate,
Multi-channelization is basically effective, and a transmission method using intersymbol interference is also effective.

First, referring to FIGS.
The O video disc recording / reproducing apparatus will be described. Figure 6
In the figure, 10 is a recording system and 20 is a reproducing system, and an analog video signal input from the terminal IN of the recording system 10 is
The data is digitized by the A / D converter 11 and supplied to the encoding circuit 12 to generate data conforming to a predetermined format.

The output data of the encoding circuit 12 is supplied to a precoding circuit PC consisting of an adder 13 and a 1-bit delay feedback element 14 and undergoes a predetermined partial response type transmission end equalization. The intermediate series output from the precode circuit PC is supplied to the recording side optical head Hw via the recording amplifier 15 and recorded on the MO disc D.

As is well known, the partial response method positively utilizes a waveform having intersymbol interference in order to narrow a required transmission band. For example, a class I PR (1, In the 1) method, so-called duobinary code, as shown by the solid line in FIG.
Compared with the unipolar (single flow) code shown by the broken line in the figure, the power spectrum is compressed to 1/2 on the frequency axis.
Further, on the transmission path, there are three levels of [+ A], [-A] and [0] corresponding to "1" of the information source sequence,
There is no direct transition between [+ A] and [-A] levels, and it always passes through the [0] level. In the PR (1,1) method, the data at the present time is a response in which only the data one clock before is interfered.

In the reproducing system 20, the so-called RF signal reproduced from the MO disk D by the reproducing optical head Hr is passed through the reproducing amplifier 21 and the waveform equalizing circuit 2 is used.
2 and the PLL circuit 23 are commonly supplied. Recording system 10
In accordance with the PR (1,1) method, the equalizing characteristics of the equalizing circuit 22 are selected as shown by the solid line in FIG. 8, and the reproducing side optical head as shown by the broken line in FIG. Spatial frequency characteristics (Modulation Transfer Function) such as Hr are equalized.

As a result, in the recording system 10, the original digital signal as shown in FIG. 9A, for example, is supplied to the precode circuit PC, and the precode data as shown in FIG. Recorded in D.
In the reproducing system 20, an RF signal as shown in FIG. 6C is reproduced from the disc D, and the waveform equalizing circuit 22
The waveform is equalized as shown in FIG.

The output of the equalization circuit 22 is a pair of comparators 24.
The signal is commonly supplied to one of the input terminals a and 24b, and compared with the pair of reference voltages Vra and Vrb supplied to the other input terminal, respectively, and the level is judged as a ternary signal.

The outputs of the comparators 24a and 24b are supplied to the decoding circuit 25 and are returned to the data conforming to a predetermined format. On the other hand, in the PLL circuit 23, a continuous reproduction data clock CK is generated based on the clock component separated from the reproduction RF signal, and this reproduction data clock CK is supplied to the latch 26 as a time axis reference, The timing of the data output from the decoding circuit 25 is adjusted.

[0011]

By the way, in the conventional MO video disk recording / reproducing apparatus as described above, the partial response system is adopted to reduce the required transmission band, and in the reproducing system, intersymbol interference is caused. In order to detect the transmission data (original digital signal) from the reproduction RF signal permitted by the above, it is necessary to open the eye pattern of the reproduction RF signal by accurate reproduction equalization.

By the way, the reproduction equalization is not performed, and the MTF is
In the case of only, since there is interference of not only the data one clock before but also the data two clocks before, the eye pattern is hardly opened,
It is not possible to detect the original digital signal by simply separating with a threshold value.

However, for example, in the waveform equalization characteristic corresponding to the PR (1,1) system, as shown in FIG. 8, the level difference from the MTF is about 3 dB at the fundamental wave frequency fpr. However, there is a problem that it is difficult to make an adjustment for accurate reproduction equalization. Also, the disk is C
When recorded by the AV system, the spatial frequency characteristic of the reproduced RF signal changes depending on the radius of the track, and it is necessary to control the equalization circuit accordingly.
There was a problem that accurate reproduction equalization becomes more difficult.

In general digital processing, a maximum likelihood decoding method is used in which an expected value for the next data is obtained from the system response and past data, and a path with a low expected value is cut off. However, this maximum-likelihood decoding method requires high-speed calculation, and the circuit scale becomes enormous. Therefore, it is not suitable for the field of digital video recording / reproduction for processing a large amount of data in real time.

In view of such a point, an object of the present invention is a digital circuit which does not require waveform equalization or high-speed calculation and can detect an original digital signal from a reproduced RF signal accurately and at high speed with a small-scale circuit. A signal reproducing device is provided.

[0016]

According to the present invention, a medium on which a digital signal is recorded is scanned by a reproducing conversion element to obtain a reproduced RF signal, and the medium is generated based on a clock component separated from the reproduced RF signal. In a digital signal reproducing apparatus configured to detect an original digital signal from a reproduction RF signal using a reproduction clock as a time axis reference, an AD converter 27 for converting the reproduction RF signal into q-bit data, and a plurality of A / D converters The latch group 28 in which the latches 28a to 28c are connected in series and holds a series of data supplied from the AD converter, and a large number of data patterns PT corresponding to the level of the reproduction RF signal at a series of time points are stored. A memory 29 is provided, and a series of data held in the latch group is accessed as address information in the memory 29. By reading select a specific data pattern is a digital signal reproducing apparatus adapted to detect the original digital signal.

[0017]

According to this structure, the original digital signal can be detected accurately and at high speed from the reproduced RF signal which is not waveform-equalized by a small-scale circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the digital signal reproducing apparatus according to the present invention is applied to reproduction of a digital video disc will be described below with reference to FIGS.

The structure of an embodiment of the present invention is shown in FIG.
In FIG. 1, portions corresponding to those in FIG. 6 described above are denoted by the same reference numerals, and redundant description will be omitted. In FIG. 1, 20
M represents a reproducing system as a whole, and in this embodiment, for data detection, an AD converter 27 and a plurality of latches 28 are provided.
a group of latches 28 in which a to 28c are connected in cascade, and high-speed R
AM29 and is provided.

The A / D converter 27 is supplied with the RF signal from the regenerative amplifier 21 and a sampling clock having a period of, for example, 15 nS from the PLL circuit 23, and the regenerated RF signal is composed of, for example, 5 bits. It is quantized and converted into a digital signal (data). This data is sequentially supplied to the three-stage latches 28a, 28b, 28c, and based on the clocks respectively supplied from the PLL circuit 23, a series of data Dk, Dk-1, Dk- on the time axis.
2 is held in each of the latches 28a to 28c.

The RAM 29 stores a large number of data patterns (reference patterns) PT corresponding to the level of the reproduction RF signal at a series of time points, and latches 28a to 28a-2.
Data Dk, Dk at three time points respectively held in 8c
-1, Dk-2 are accessed with an address of 15 bits in total, and a specific reference pattern corresponding to this address is read. The CPU 3 stores the above-mentioned reference pattern PT.
Performed by zero.

The operation of the embodiment of the present invention will be described below with reference to FIGS. In this embodiment, as shown in FIGS. 2 and 3, various reference patterns of the RF signal are preset in the RAM 29 and, as shown in Table 1 below, a series of latch patterns held in the latches 28a to 28c. A specific reference pattern corresponding to the precoded data Dk, Dk-1, Dk-2 is read out.

[0023]

[Table 1]

Generally, the positive gradient of the reference pattern at each time point corresponds to "1" of the precode data, and the negative gradient of the reference pattern corresponds to "0" of the precode data. As is clear from Table 1, the reference patterns in FIGS. 2 and 3 have polarities opposite to each other.

Further, as is apparent from FIGS. 2 and 3,
Precode data Dk at the present time in each reference pattern
On the other hand, the influence of the data Dk-3 three clocks before is small, and if the precode data Dk-2 and Dk-1 two clocks before and one clock before which the interference is stronger are known, It is possible to determine Dk. Therefore, this 3
By simultaneously comparing the RF signal levels at the time points, the precode data Dk at the current time point can be immediately detected for each pattern of the input RF signal.

As described above, in this embodiment, the precode data at the present time can be detected without performing the waveform equalization of the reproduction RF signal, so that the waveform equalization circuit is not required and the apparatus Adjustment becomes easy, and dynamic adaptive control becomes easy even when reproducing a disc recorded by the CAV method. Further, since the pattern of the input RF signal is compared with the reference pattern PT stored in the RAM 29, there is no need for high-speed calculation, and the circuit can be constructed with a relatively small circuit to reduce the transfer rate. It is possible to have multiple channels.

The data detection by the pattern comparison is similar to the maximum likelihood decoding method using the trellis diagram in the Viterbi decoding method, but the maximum likelihood decoding method branches the determination result at one point on the time axis. In contrast to leaving as a branch, this embodiment differs from the maximum likelihood decoding method in that the determination is carried over to the point where interference can be ignored and the determination is made as a series of patterns on the time axis.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the structure of the essential parts of another embodiment of the present invention. In FIG. 4, parts corresponding to those in FIGS. 1 and 6 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 4, 28N is n latches 28.
a-28n is a cascaded n-stage latch group, 29M is a multi-output RA having m + 1 output terminals 29oo-29om
The reproduction RF signal which is M and has been converted into q-bit data by the AD converter 27 is supplied to the latch group 28N. The data output from each of the latches 28a to 28n of the latch group 28N is supplied to the RAM 29M as a total of nq-bit addresses as described above, and the multi-output RA is output.
From the output terminals 29oo to 29om of the M29M, m + 1 series data are respectively output with the timings shifted by one clock.

Reference numeral 40 denotes a majority decision circuit, which is provided with m + 1 input terminals 40iO to 40im, and these input terminals 40iO to 4im.
0im and corresponding output terminals 29oo to 29 of RAM 29M
om and RAM are connected as follows, RAM29M
The m + 1 series data from are supplied to the majority circuit 40 at the same timing. As the output of the majority decision circuit 40, the precode data Dk at the present time can be detected.

That is, the first output terminal 29 of the memory 29M
oo is directly connected to the first input terminal 40iO of the majority circuit 40, and the second output terminal of the RAM 29M is also connected.
29oa and the second input terminal 40ia of the majority circuit 40 are 1
It is connected through the individual latches 41aa. Similarly, the m + 1-th output terminal 29om of the RAM 29M and the m + 1-th input terminal 40im of the majority circuit 40 are connected via the m latches 41ma to 41mm. Generally,
n ≧ 4, m + 1 ≧ 3, n ≠ m + 1. The rest of the configuration is similar to that of the embodiment shown in FIG.

In this embodiment, the number of observation points is increased and the result is determined by the majority logic. Therefore, while the advantages of the embodiment of FIG. Can be raised.

Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 5 shows the configuration of the essential parts of still another embodiment of the present invention. In FIG. 5, parts corresponding to those in FIGS. 1, 4 and 6 are denoted by the same reference numerals, and redundant description will be omitted.

In the embodiment of FIG. 5, a subtractor 51 is connected between the AD converter 27 and the latch group 28N, and
R via the precode circuit 52 and the DC detection circuit 53
The output data of the AM 29 is digitally fed back to the subtractor 51.

Further, as indicated by a broken line in FIG. 5, the output of the DC detection circuit 53 is added to the adder 55 via the DA converter 54.
To the analog-to-digital converter 27 together with the conversion reference voltage Vrf.

In the embodiment of FIG. 5, the history of the detected data within an appropriate period is checked and the direct current component is fed back. Therefore, while the advantages of the embodiment of FIG. Even when the DC is cut off, it can be easily dealt with.

In each of the above embodiments, RA
Although the reference pattern PT is stored in M, the reference pattern PT may be stored in the ROM. Further, in each of the above-described embodiments, the MO disk is used as the recording medium, but the present invention is, for example, a digital VTR.
It can be widely applied to reproduction of general high-density digital recording.

[0038]

As described above in detail, according to the present invention,
In a digital signal reproducing apparatus configured to detect an original digital signal from a reproduction RF signal, a series of data converted from the reproduction RF signal by an AD converter is held in a plurality of latches in a latch group and held. A series of data is used as address information to access a memory in which a large number of data patterns corresponding to the level of a reproduction RF signal are stored, and a specific data pattern is selected from the large number of data patterns and read out. It is possible to obtain a digital signal reproducing apparatus which can detect an original digital signal accurately and at high speed from a reproduced RF signal which is not waveform-equalized with a circuit having a large scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital signal reproducing apparatus according to the present invention.

FIG. 2 is a diagram for explaining the operation of an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of an embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of still another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration example of a conventional digital signal reproducing device.

FIG. 7 is a diagram for explaining the operation of a conventional example.

FIG. 8 is a diagram for explaining the operation of a conventional example.

FIG. 9 is a diagram for explaining the operation of a conventional example.

[Explanation of symbols]

 27 A-D converter 28, 28N Latch group 29, 29M RAM D Digital video disk Hr Playback side optical head PT Reference pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 9/80 B 9185-5C

Claims (1)

[Claims] 1. A medium on which a digital signal is recorded is scanned by a reproducing conversion element to obtain a reproduced RF signal, and a reproduced clock generated based on a clock component separated from the reproduced RF signal is used as a time axis reference. , Above playback R
In a digital signal reproducing apparatus adapted to detect an original digital signal from an F signal, A-D for converting the reproduced RF signal into q-bit data
A converter, a group of latches in which a plurality of latches are connected in series to hold a series of data supplied from the AD converter, and a large number of data patterns corresponding to the level of the reproduction RF signal at a series of time points. A stored memory is provided, and the series of data held in the latch group is accessed as address information in this memory, and a specific data pattern is selected from the large number of data patterns and read out. A digital signal reproducing device characterized in that a digital signal is detected.