JPH0589202A - Layout pattern generator - Google Patents

Abstract

PURPOSE:To obtain a layout pattern considering delay time between cells when the layout pattern is designed. CONSTITUTION:This generator is equipped with a logic diagram input means 1, a connection information extracting means 3, an allowable delay time attaching means 7 which attaches allowable delay time on the wiring of a logic diagram, a maximum delay time checking means 8 which estimates the area of the layout pattern 6 and finds the maximum delay time of wiring from the connection information, an allowable delay time checking means 9 which checks the fact that the allowable delay time is between the maximum delay time and prescribed minimum delay time, an allowable delay data generating means 10 which finds allowable wiring length from the allowable delay time, a cell arranging means 4 which arranges the cell based on those information, and an inter-cell wiring means 5. Thereby, it is possible to improve the precision of a logic function and to shorten a construction term when the layout pattern is designed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout pattern creating apparatus for an integrated circuit or the like.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional layout pattern creating apparatus. 1 is a logic diagram input means, 2 is a logic diagram, 3 is connection information extracting means, 4 is cell arranging means, 5 Is an inter-cell wiring means, and 6 is a layout pattern.

Next, the operation will be described. A logical diagram 2 is created by the logical diagram input means 1. The connection information extraction means 3 is used from the logic diagram 2 to extract the connection information required for the cell placement means 4 and the inter-cell wiring means 5. Subsequently, the cell arranging unit 4 arranges the cells using the extracted connection information, and the inter-cell wiring unit 5 arranges the arranged cells according to the connection information to create the layout pattern 6.

[0004]

The conventional layout pattern forming apparatus is configured as described above, and although the degree of integration can be improved by optimizing the cell arrangement and the inter-cell wiring, the layout is improved. When creating a pattern, the delay time due to the wiring between cells cannot be taken into consideration, and the delay time is calculated from the layout pattern after creating the layout pattern.
There has been a problem that the layout pattern must be used again for the logic simulation, and the layout pattern must be redesigned again depending on the result of the logic simulation.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a layout pattern creating apparatus in which a delay time between cells is taken into consideration when designing a layout pattern.

[0006]

According to a first aspect of the present invention, there is provided a layout pattern creating apparatus, wherein a logic diagram inputting means for inputting a logic diagram of an integrated circuit and a permissible delay time between cells are provided as properties for wiring in the logic diagram. Allowable delay value adding means to add, connection information extracting means to extract connection information required for automatic placement and routing and logic simulation from the logic diagram, and estimate the area of the layout pattern from the connection information extracted from the logic diagram to determine the maximum delay time. Maximum delay value investigation means to check
Allowable delay time added to the logic diagram: Allowable delay time checking means to check if it is greater than or equal to the set minimum delay value and less than or equal to the maximum delay value, and to check the allowable wiring length from the allowable delay time to create allowable delay data. The delay data creating means, the cell arranging means for arranging cells using the allowable delay data, and the inter-cell wiring means for wiring between the arranged cells are provided.

Since the layout pattern creating apparatus according to the second invention creates the allowable delay data, the fan-out number checking means for checking the fan-out number of each cell in the logic diagram and the tentative wiring length based on the fan-out number. And a logical simulation means for performing a logical simulation.

[0008]

The means for adding the allowable delay time in the first invention is
Allowable delay time is added to the wiring in the logic diagram, the maximum delay time checking means estimates the layout pattern area from the extracted connection information and checks the maximum delay time, and the allowable delay time checking means uses the added allowable delay time. Is greater than or equal to the set minimum delay value and less than or equal to the maximum delay value, and the permissible delay data creating means investigates the permissible wiring length from the permissible delay time between the added cells, creates permissible delay data, and Since the arranging unit arranges the cells using the allowable delay data, it is possible to obtain the layout pattern in which the delay time between the cells is taken into consideration.

The fan-out number checking means in the second invention checks the fan-out number of each cell in the logic diagram, and the tentative wiring length checking means checks the tentative wiring length from the fan-out number, and the logic simulation means. Is a logical simulation using the tentative wiring length and the connection information, and the allowable delay data creating means checks the allowable wiring length from the result of the logical simulation, creates the allowable delay data, and outputs the delay information to the cell placement means, Reflected in the inter-cell wiring means.

[0010]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a logic diagram input means, 2 is a logic diagram, 3 is connection information extracting means, 4 is cell arranging means, 5 is inter-cell wiring means, 6 is a layout pattern, 7 is an allowable delay time adding means, 8 Is a maximum delay time investigation means, 9 is an allowable delay time investigation means, 10 is an allowable delay data creation means, 11
Is technology data.

Next, the operation will be described. In FIG. 1, the logic diagram 2 is input using the logic diagram input means 1. The permissible delay time adding means 7 adds the permissible delay time set by the layout pattern designer to any wiring in the logic drawing as a property to the input logic diagram 2.

The connection information extracting means 3 extracts the connection information necessary for the cell arranging means 4 and the inter-cell wiring means 5 and the allowable delay time added to the wiring. Maximum delay time extraction means 8
Is the extracted connection information, the area of each cell used in the cell placement means, the design rule of the layout pattern,
The maximum delay time is examined by using the technology file 11 in which the minimum delay time and the capacitance value per unit wiring length are set.

Subsequently, the allowable delay time checking means 9 determines that the allowable delay value added for each wiring is the technology file 11.
It is checked whether or not the condition that the value is equal to or more than the minimum delay value set in 1 and less than or equal to the maximum delay value checked by the maximum delay value checking means 8 is satisfied. If the condition is not satisfied, the allowable delay time is added again, so the process returns to the allowable delay time adding means 7. If the condition is satisfied, the allowable delay data creating means determines the allowable delay time for each wiring. The technology data 11 is used to check the wiring length between the cells to create allowable delay data.

The cell arranging means 4 arranges the wiring between the cells so as to satisfy the minimum value of the permissible wiring length by using the generated permissible delay data. I will increase the length. If the placement is not within the allowable range, the placement is stopped and the allowable delay time adding means 7
Return to. When all the cells are arranged in accordance with the allowable delay data, the inter-cell wiring means 5 wires the cells to create a layout pattern 6.

A specific example of the above operation will be described below. For example, a cell A having an area of S ₁ (μm ² ) and a cell B having an area of S ₂ (μm ² ) with a signal number n (lines), S ₃
When obtaining the layout pattern of the cell C having the area of
The logic diagram input means 1 is used to input the logic symbols of each A, B, and C, and the respective cells are wired by n signals to create the logic diagram 2.

The allowable delay time Ta (ns) set by the layout pattern designer is added as a property to the input arbitrary wiring in the logic diagram 2 by using the allowable delay time adding means 7. The connection information extracting means 3 extracts the connection information necessary for creating the layout pattern and the allowable delay time property added to each wiring, and creates the connection information and the allowable delay time data. Then, the maximum delay time examining means 8 examines the total sum S (μm ² ) of the areas of the cells used when creating the layout pattern from the extracted connection information. In this embodiment, S (μm ² ) = S ₁ (μm ² ) + S ₂ (μm ² ) + S ₃ (μm ² ). In addition, the number of signals (n), the width ω (μm) of the wiring pattern in the technology data, and the wiring coefficient α (μm)
The area A (μm ² ) of the layout pattern created by this device is calculated using A / μm = A (μm ² ) = S (μm ² ) + n (lines) × ω (μm) × α (μm / line) The area of the layout pattern A (μm
² ) and delay time Tb (ns / μm) per unit wiring length
The maximum delay time Tc (ns) is investigated by Tc (ns) = (√A) × 2 × Tb.

The allowable delay time examining means 9 determines the allowable delay time Ta (n) added to each wiring from the allowable time data.
In the relationship between the minimum delay time Td (ns) and the maximum delay time Tc (ns) set in the technology file, it is checked whether the condition of Td ≦ Ta ≦ Tc is satisfied. If the conditions are not met,
To add the allowable delay time Ta (ns) again, the process returns to the allowable delay time adding means 7. If the condition is satisfied, the permissible delay data creation means 10 uses the permissible delay time data to determine the permissible delay time Ta (ns) for each wiring and the delay time Tb (ns / μm) per unit wiring length for each wiring. The allowable wiring length l (μm) is examined by l (μm) = Ta / Tb, and allowable delay data is created.

The cell arranging means 4 uses the created allowable delay data and the connection information to reduce the wiring length between the cells from the cells to which signals with a small allowable wiring length l (μm) are connected. Place them in order. When it is necessary to dispose the wiring over the permissible wiring length 1 (μm), the cell disposition is stopped and the process returns to the permissible delay time adding means 7. When all the cells are arranged within the allowable wiring length 1 (μm), the inter-cell wiring means 5 for wiring the cells according to the connection information performs wiring between the cells to obtain the layout pattern 6.

Example 2. FIG. 2 shows another embodiment in which the allowable delay data is created. In FIG.
Reference numeral 2 is a fan-out number checking means, 13 is a temporary wiring length checking means, and 14 is a logic simulation means. Next, the operation will be described. First, the fan-out number checking means 12 checks the fan-out number of each cell from the logic diagram 2. The tentative wiring length checking means 13 checks the tentative wiring length between each cell from the number of fan-outs.

Subsequently, the logic simulation means 14 checks the provisional wiring length between each cell and the provisional delay time from the technology file 11, and uses the delay time and the connection information extracted by the connection information extracting means 3 to perform a logic simulation. To do. The permissible delay data creation means 10 checks the permissible delay time for each wiring from the result of the logic simulation, and also checks the permissible wiring length using the technology file 11 to create the permissible delay data.

Next, a specific example of this will be described below. The fan-out number checking means 12 checks the fan-out number n (number) of each logical symbol from the logic diagram 2. The tentative wiring length checking means 13 sets the tentative wiring length l ₂ (μm) between the cells to the fanout number n (pieces) and the wiring length B (μm) per fanout.
From m / piece, it is examined using the formula of l ₂ (μm) = n (pieces) × B (μm / piece). Subsequently, the logic simulation means 14 determines the provisional delay time Te (ns) for each wiring from the provisional wiring length l ₂ (μm) between each cell and the delay time Tb (ns / μm) per unit wiring length. By using the formula Te (ns) = 1 ₂ (μm) × Tb (ns / μm), and using the provisional delay time Te (ns) and the connection information extracted by the connection information extracting means 3, Perform a simulation. Based on the result of the logic simulation, the permissible delay data creation means 10 checks the permissible delay time Ta (ns) between the cells, and from the delay time Tb (ns / μm) per unit wiring length, the permissible wiring length 1 (μm) Is examined according to l (μm) = Ta (ns) / Tb (ns / μm), and allowable delay data is created.

According to FIG. 2, the allowable delay time adding means 7 shown in FIG. 1 is not necessary, and the allowable delay data is created by using the logic simulation means 14. It can be reflected in the means 4 and the inter-cell wiring means 5.

Example 3. In the above embodiment, the case of the layout pattern of the semiconductor integrated circuit has been described, but the layout pattern of the printed circuit board or other digital / analog signal circuit board may be used.

[0024]

As described above, according to the present invention, it is possible to obtain a layout pattern in which the delay time between cells is taken into consideration. Therefore, it is possible to improve the accuracy of the logic function when designing the layout pattern and shorten the construction period. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a layout pattern creating apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a layout pattern creating apparatus according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional layout pattern creation device.

[Explanation of symbols]

 1 Logic Diagram Input Means 2 Logic Diagram 3 Connection Information Extraction Means 4 Cell Placement Means 5 Cell Placement Means 6 Layout Patterns 7 Allowable Delay Time Adding Means 8 Maximum Delay Time Examining Means 9 Allowable Delay Time Examining Means 10 Allowable Delay Data Creating Means 11 Technology data 12 Fan-out number investigation means 13 Temporary wiring length investigation means 14 Logic simulation means

Claims (2)

[Claims] 1. A layout pattern creating device for an integrated circuit or the like having the following elements: (a) a logic diagram input means for inputting a logic diagram of the integrated circuit or the like; (b) an allowable delay corresponding to wiring in the logic diagram. Allowable delay time adding means for adding time, (c) Connection information extracting means for extracting predetermined connection information from the logical diagram, (d) Area of layout pattern is determined from the connection information extracted by the connection information extracting means. Maximum delay time checking means for estimating and estimating the maximum delay time due to wiring in the layout pattern, (e) at least the allowable delay time added to the logic diagram is equal to or greater than a predetermined minimum delay time, and the maximum delay time Allowable delay time checking means for checking one of being less than or equal to the maximum delay time checked by the delay time checking means, (f) Allowance added to the wiring of the logic diagram Allowable delay data creating means for checking the allowable wiring length from the delay time and creating allowable delay data, (g) cell arranging means for arranging cells using the allowable delay data, and (h) connecting the arranged cells with each other. Inter-cell wiring means for wiring between cells according to the connection information extracted by the information extraction means. 2. A layout pattern creating device having the following elements: (a) a logic diagram input means for inputting a logic diagram of an integrated circuit or the like; (b) a fanout for checking the fanout number of each cell in the input logic diagram. Number investigation means, (c) tentative wiring length investigation means for estimating the tentative wiring length from the fan-out number, (d) connection information extraction means for extracting predetermined connection information from the logical diagram, and (e) extracted from the logical diagram Logical simulation means for performing a logical simulation using the connection information and the tentative wiring length, (f) Allowable delay data creation for creating an allowable delay data from the result of the logical simulation and the tentative wiring length checked by the tentative wiring length examining means. (G) cell arranging means for arranging cells using the permissible delay data, (h) extraction between the arranged cells by the connection information extracting means Inter-cell wiring means for wiring between cells in accordance with the connection information.