JPH0589157A - Processor for calculating interaction force for gravity multiple system and electric force multiple system - Google Patents

Abstract

PURPOSE:To provide an inexpensive processor which can calculate interactive force and potential in a gravity or electric force multiple system at a speed of the same order as a supercomputer. CONSTITUTION:A relative position calculation means 2 obtains the coordinate differences of X, Y and Z based on the coordinates of two points, and converts them to logarithm expression. A relative distance calculation means 3 obtains the square of a relative distance r2 from the coordinate difference and the prescribed constant, and a 1/2 power-raising means 4 and a 3/2 power-raising means 5 obtain (r) and r3. Mass or a change Mj is supplied from the external part of an integrated circuit 1 at every cycle. Logarithm expression division means 6a and 6b obtain Mj/r3 and Mj/r. Interactive force calculation means 7a-7c calculate the products of Mj/r3 and the respective coordinate differences. A potential calculation means 8 calculates u*(Mj/r). Fixed point conversion means 9a-9d convert logarithm expression into fixed point expression. Values converted into fixed point expression in addition means for integration 10a-10d are sequentially integrated in integrated value register means 11a-11d. A processing in the integrated circuit 1 is made into a pipe line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gravitational multi-body system such as an astronomical object composed of a large number of stars moving while exerting gravity on each other, and a large number of plasma particles moving while exerting an electric force on each other. The present invention relates to a dedicated processing device for calculating the force and potential that a particle receives from another particle in an electric force multi-body system composed of atoms in a protein molecule.

[0002]

2. Description of the Related Art A gravitational many-body system is a system composed of many particles interacting by gravity. Many galaxies and globular clusters can be regarded as gravitational many-body systems. Although many-gravity systems are extremely simple systems governed only by Newton's equation of motion and universal gravitational force (gravity), they often behave strangely with rich nonlinearity. If there are three or more bodies, there is no analytic solution, so it is necessary to perform numerical calculation, but this involves a great amount of calculation. Gravity reaches far, so N
N * (N-1) / 2 to calculate the movement of individual particles
We must consider all interactions that work on individual pairs. Conventionally, gravity and gravitational potential calculation were written in software and calculated on a supercomputer.

[0003]

In the prior art, when the number N of particles is large, the amount of calculation becomes enormous, and even the best supercomputer at present has a limit of tens of thousands of calculations. On the other hand, in order to clarify the three-dimensional structure of a gravitational many-body system, it is necessary to perform numerical calculation of the interaction of at least millions of particles, but the current supercomputer lacks computational power at all. There is a fundamental problem. Similar problems also exist in the fields of strongly coupled plasma, diluted plasma in which strong instability exists, and the analysis of the three-dimensional structure of protein molecules. Further, since the supercomputer is extremely expensive, even if the above calculation is performed, it will be extremely expensive.

The present invention calculates the gravity and gravitational potential in a gravitational many-body system, or the electric force and electric potential in an electric many-body system at almost the same speed as a supercomputer, and Also offers a much cheaper processor.

[0005]

According to the present invention, as shown in FIG. 1, a relative position calculating means 2 and a relative position calculating means 2 are provided on one integrated circuit 1.
Relative distance calculation means 3, 1/2 power means 4, 3/2 power means 5, logarithmic expression division means 6a, and logarithmic expression division means 6
b, three interaction force calculation means 7a, 7b, 7c,
Potential calculation means 8, four fixed point representation conversion means 9a, 9b, 9c, 9d, four sets of addition means for integration 10a, 10b, 10c, 10d and integrated value register means 11a, 11b, 11c, 11d. , Means for setting the content of the integrated value register means 11 to 0, means for holding the content of the integrated value register means 11, an external bus interface means 15, and four pipeline registers 19
It is composed of a, 19b, 19c and 19d. The relative position calculation means 2 includes component difference calculation means 20a, 20
b, 20c and register means 21a, 21 for three-dimensional coordinates
b, 21c.

[0006]

One of the coordinate data (Xj, Yj, Zj) of the two points indicating the center of mass or the center of charge in the three-dimensional space is supplied from the outside of the integrated circuit 1 every cycle, and the other coordinate data (Xi, Yj, Zi). Yi, Zi) is Xi, Y inside the relative position calculating means 2 via the external bus 13 and the internal bus 12a.
It is stored in the register means 21 for i and Zi. In the relative position calculation means 2, Xi-Xj, Yi-Yj, Zi-Zj.
Are calculated and converted into logarithmic expressions Xij, Yij, and Zij, respectively. The relative distance calculating means 3 has an internal register 46 written via the external bus 13 and the internal bus 12a.
From the value e of X and Xij, Yij, Zij, r2 = Xij ** 2 + Yij ** 2 + Zij ** 2 + e ** 2 is obtained and output. Note that e is a constant. The 1/2 means 4 calculates r = r2 ** (1/2). The 3/2 squaring means 5 calculates the product of r and r2 to obtain r3 = r2 ** (3
/ 2) is calculated. From the outside of the integrated circuit 1, Mj previously expressed in logarithmic expression is supplied every cycle. Note that Mj
Is mass or charge. Two logarithmic expression division means 6a
And 6b determine Mj / r3 and Mj / r, respectively.
The three interaction force calculation means 7a, 7b, 7c are Mj
/ R3 and Xij, Yij, and Zij respectively, that is, Xij * (Mj / r3), Yij * (Mj / r
3), Zij * (Mj / r3) is calculated. The potential calculation means 8 calculates u * (Mj / r) from the constant u and Mj / r.
To calculate. The fixed point conversion means 9a, 9b, 9c are
The logarithmic expressions Xij * (Mj / r3) and Yij, respectively.
* (Mj / r3), Zij * (Mj / r3) are converted into fixed point representation. The fixed point conversion means 9d converts u * (Mj / r) in logarithmic representation into fixed point representation. The adding means for integration 10a, 10b, 10c, 10d of the integrated value register means 11a, 11b, 11c, 11d respectively containing the four values converted into the fixed point representation and the respective integrated values before that. The values are added together, and the results are respectively added value register means 11a, 11b,
It is written in 11c and 11d. The contents of the integrated value register means 11 can be read out of the integrated circuit 1 using the internal bus 12b and the external bus 13.

The processing in this integrated circuit is pipelined. Therefore, pipeline registers 19a, 19b, 19c, 1 for adjusting the delay difference between data
There is 9d. The delayed data is Xij, Yij, Zi
j and Mj.

[0008]

EXAMPLES First, the logarithmic expression used in the examples will be described. A binary number p having a bit length 1 is a real number x = 2 ** (p / f). ． ． (Formula 5) is represented. Where f is a constant, f = 2 ** m. ． ． (Formula 6) This m will be called the fractional word length. Letting y be the value when the original bit pattern is regarded as an unsigned fixed-point display with a fraction part word length of m bits, p = y * f. ． ． (Equation 7) Therefore, x = 2 ** y. ． ． (Equation 8) The following relationship holds. 1 or more 2 *
Real number in the range less than * (2 ** (1-m)) is the relative interval 2
It will be expressed by ** (-(2 ** m)). In the embodiment, bit length l = 12, of which fraction part word length m
= 5 bits is used. Therefore, the bit pattern 0x000 (0x is a 3-digit number following 0
The hexadecimal number of F) indicates 1, the bit pattern 0x001 indicates 2 ** (1/32), and the bit pattern 0xFFF indicates 2 ** (127+ (31/32)). These 12 bits are logarithmically expressed as bits [1
1: 0]. Bits [11: 0] mean data consisting of 12 bits from bit 0 to bit 11. Only positive values can be represented in this format. Therefore, the former bit, which is used to indicate whether the code is 1 bit or 0, is called the code flag, and is assigned to bit 12 of logarithmic expression. If the latter bit is 1, the value expressed in logarithmic expression is not 0. This bit is called a non-zero flag and is assigned to bit 13 of logarithmic representation. Therefore, in the embodiment, the logarithmic representation is 14
It is expressed in bits.

Examples will be described below. The overall configuration is shown in FIG.

The coordinate inputs Xj, Yj, and Zj are each 20
Bits, expressed in fixed point. Input Mj is 1
It is expressed in logarithmic notation with a 4-bit width. External bus 13
Are register addresses A [2: 0] and 28 having a 3-bit width.
It is composed of a data bus D [27: 0] having a bit width, and control signals CS (chip select), OE (output enable), and WE (write enable).
A PC (pipeline control) 14 is a 1-bit input signal indicating whether the integrated circuit 1 can perform an operation. NB 1
Reference numeral 6 is a 1-bit output signal for detecting the case where the distance between the two points is smaller than the constant h. The NB 16 is used to detect a case where the interaction force or the potential becomes large and overflow or the like may occur.

The internal bus comprises an internal bus 12a for transmitting data input from the external bus 13 and an internal bus 12b for outputting data to the external bus 13.

The relative position calculation means 2 has three processing means for performing the same processing on the X, Y and Z components, but since the contents are the same, only the one for the X component will be described here. explain.

There is a register means 21a for storing the value of Xi. It consists of a latch. This is written from the external bus 13 via the internal bus 12a. This register means 21 has a 20-bit length and a fixed-point representation value is entered therein. The control of the latch for writing is performed by the external bus interface unit 15.

An embodiment of the component difference calculating means 20a is shown in FIG. Xj [19: 0] supplied from outside the integrated circuit 1
And Xi [1 supplied from the Xi register means 21a.
9: 0] is given to the 20-bit subtractor 29a, and the difference X
The j-Xi is input to a 20-bit wide D-type flip-flop (hereinafter abbreviated as DFF) 36a. The output of the DFF 36a is XD [19: 0]. XD which is this MSB
[19] represents the code of Xj-Xi. 20-bit width subtractor 29b finds 0-XD, and XD [19]
Control the multiplexer 31 of 19-bit width with Xj-
Get the absolute value of Xi. That is, if Xj-Xi is 0 or positive, XD [19] becomes 0, and the multiplexer 31 outputs XD [18: 0]. If not, XD [1]
9] is 1 and the multiplexer 31 outputs the output of the subtractor 20b, that is, Xi-Xj, and supplies it to the DFF 36c.
XD [19] is a 1-bit wide DFF 36b, 36e,
Xi which is a code flag of logarithmic expression through 36h and 36l
j [12]. The output of DFF 36c is DFF 3
In addition to being an input to 6f, it is given to the comparator 35a and compared with 0 by the comparator 35a. If all 19 bits are 0, 0 is output, and if not, 1 is output.
It is output as Xij [13] which is a non-zero flag of logarithmic expression through FFs 36d, 36g and 36k.

The output xa [18: 0] of the DFF 36f is converted into a logarithmic representation as described below.

PLA (programmable logic array)
32 operates as a priority encoder, and xa
Enter [18: 0] and enter xa [1 as shown in Table 1.
8: 0] is converted to output xe [4: 0]. In Table 1, "x" indicates that either 0 or 1 may be used.

[0017] [Table 1] xa [18: 0] xe [4: 0] 0000000000000000000 00000 0000000000000000001 00000 000000000000000001x 00001 00000000000000001xx 00010 0000000000000001xxx 00011 000000000000001xxxx 00100 00000000000001xxxxx 00101 0000000000001xxxxxx 00110 000000000001xxxxxxx 00111 00000000001xxxxxxxx 01000 0000000001xxxxxxxxx 01001 000000001xxxxxxxxxx 01010 00000001xxx xxxxxxxx 01011 0000001xxxxxxxxxxxx 01100 000001xxxxxxxxxxxxx 01101 00001xxxxxxxxxxxxxx 01110 0001xxxxxxxxxxxxxxx 01111 001xxxxxxxxxxxxxxxx 10000 01xxxxxxxxxxxxxxxxx 10001 1xxxxxxxxxxxxxxxxxx 10010 Further, xa [18: 0] 1 to the right bit at the top in the can to appear MSB of the output of the shifter 33,
PLA 32 also generates shifter control signals sc [4: 0] to control shifter 33. However, here, shifter 3
3 is such that if xa [18: 0] is all bits 0, the output of the shifter 33 is all bits 0, and the shift-in part is always 0. Output of shifter 33 is 1
It is given to a 9-bit wide DFF 36i and its output is x
m [18: 0].

Xe [4: 0] is the non-fractional part in the logarithmic representation. On the other hand, xm [18: 0] represents a fractional part and is given as the upper 6 bits of the address input of the two comparators 35b and 35c and ROM (read only memory) 34. The comparator 35b outputs only when xm [18:13] is 1, that is, 1
1 is output only when the hexadecimal display is 3F. The comparator 35c outputs only when xm [12: 0] is all 0, xm
0 is output to nz. xmnz is given to the least significant bit of the ROM 34 address input. ROM 34 is 128
The conversion of the decimal part to the logarithmic expression is performed with the structure of words × 5 bits. Address input (ie xm [18:13], x
Mnz) is X and data output is Y. When xmnz = 0, Y = 0x1F & (32 * log ₂ (1 + X / 12
8)) When xmnz = 1 and xm [13] = 0 Y = 0x1F & (32 * log ₂ (1+ (X >>)
2) / 32)) When xmnz = 1 and xm [13] = 1 Y = 0x1F & (32 * log ₂ (1+ (X >> 2)
The relationship is +1) / 32)). However, the rounding in this formula is rounded off. The symbol & in the formula means a logical AND in bit units.

This equation is practically almost the same as rounding the normalized data to 5 bits and converting it to logarithm. However, the rounded value is exactly 1 /
When it is equal to 2 (that is, when xmnz = 0), the value of 6 bits is used as it is for conversion without rounding.
This eliminates the bias generated from the rounding direction when the fraction is exactly 1/2.

When the value of Y (the output of the ROM 34) is rounded up to 32, the non-fractional part of the logarithmic expression must be increased by 1. This is the case when the value of X is 0x7E and 0x7F, this condition is detected by the comparator 35b, the output thereof is given to the carry-in input of the adder 30, and one of the inputs passes through the DFF 36j xe.
Incrementing is performed by inputting [4: 0] and giving all bits 0 to the other input. The output of the ROM 34 passes through the DFF 36n and the decimal part Xij [4: of the logarithmic expression.
0]. The output of the adder 30 passes through the DFF 36m and becomes the decimal part Xij [9: 5] of the logarithmic expression. Note that Xi
j [11:10] is omitted here because it is always 0.

The above-mentioned DFFs 36a to 36n are provided to pipeline the processing.

Next, an embodiment of the logarithmic expression multiplying means used for the calculation of multiplication in the present invention is shown in FIG. Here, two logarithmic expression values a [13: 0] and b [13:
[0] multiplication will be described. The multiplication result is c [13:
0]. One AND gate 22 and one ExO
It is composed of an R gate 23 and one 12-bit wide adder 24.

If A = 2 ** (a [11: 0] / 2 ** 5) and B = 2 ** (b [11: 0] / 2 ** 5), then the following relationship and adder 24 The reason for existence of is easily understandable.

A * B = 2 ** ((a [11: 0] + b [11: 0]) / 2 ** 5) The non-zero flag c [13] is non-zero only when both a and b are non-zero. Therefore, using the AND gate 22,
Let the logical product of [13] and b [13] be c [13]. Further, since c becomes negative only when the signs of a and b are different from each other, the ExOR gate 23 is used, and a [12] and b
The exclusive OR of [12] is taken as c [12].

An embodiment of the logarithmic expression division means is shown in FIG.
Here, a case will be described in which the logarithmic expression value a [13: 0] is divided by a non-zero logarithmic expression value b [13: 0] to obtain c [13: 0]. It is assumed that this logarithmic expression division means does not divide by zero.

Since there is a relationship of A / B = 2 ** ((a [11: 0] −b [11: 0]) / 2 ** 5), the subtractor 25 converts a [11: 0] to b. Subtract [11: 0] to be c [11: 0]. If a is zero, c is also zero, so a [13] is left unchanged as c [1
3]. Since c becomes negative only when the signs of a and b are different from each other, the ExOR gate 26 is used and a [1
2] and b [12] are exclusive ORed to obtain c [12].

An embodiment of the logarithmic expression adding means is shown in FIG.
From two non-negative logarithmic expressions X and Y, if the values when X and Y are expressed in fixed point are x and y, respectively, the logarithmic expression adding means obtains a logarithmic expression value Z representing non-negative (x + y). It is a thing. Since X and Y are assumed to be non-negative, 13-bit X [12: 0] excluding the sign flag of logarithmic expression,
It is sufficient to handle Y [12: 0] and Z [12: 0].

Non-negative logarithmic representation addition can be performed as follows.

A) When either one is 0, the other is output as it is.

B) If neither is 0, first compare the input X and Y as unsigned binary numbers and select the larger one. Further, a difference d = | X−Y | between X and Y is obtained. d is 0x
When it is larger than FF, the smaller value of the two inputs X and Y is not larger than 1/256 of the larger value.
Therefore, even if the rounding direction is considered, the calculation result Z is
The larger value of X and Y remains unchanged. d is 0x
When it is smaller than FF, Z becomes larger than the larger one of X and Y. When X> Y, the following relationship holds between Z, X, and d.

Z−X = log ₂ (1 + 2 ** (− d)). ． ． (Expression 16) However, here, Z, X, and d are expressed in a fixed-point format with a fractional part of 5 bits. Therefore, if this relationship is stored in the ROM and d is given as an address and the read data is added to X, Z can be obtained.

In the embodiment, two inputs X [12: 0],
Y [12: 0] are both connected to the subtractors 37a and 37b, and X [12: 0] is DFF 38d and Y [1].
2: 0] is connected to the DFF 38e, and non-zero flags X [12] and Y [12] in logarithmic representation are further NAND.
It is connected to the gate 63 and its output becomes the signal zero through the DFF 38l. This signal means that at least one of the two inputs X and Y is zero. The 13-bit width subtractor 37a calculates XY, and the 13-bit width subtractor 37b calculates YY. The subtractor 37a also serves as a magnitude comparison of X and Y, and this is performed by observing the carry output of the subtractor 37a. Carry output is DFF 3
Signals XgeY and YgtX are obtained through 8a and the inverter 40. XgeY means that X is greater than or equal to Y, and YgtX means that Y is greater than X. The outputs of the two subtractors 37a and 37b are DF
The multiplexer 39 through the F 38b and the DFF 38c
given to a. This multiplexer 39a is XgeY
It is controlled by and outputs | X-Y | XmY [12: 0]
Issue as. That is, when X> = Y, XY is changed to X <Y
In case of, Y-X is output. On the other hand, DFF 38d and DF
The output of F 38e is provided to multiplexer 39b. This multiplexer 39b is controlled by YgtX and X
And Y, whichever is not smaller, that is, if Y> X then Y, otherwise choose X and the selected value is D
It enters one input of the adder 44 through the FFs 38h and 38j. Upper 5 bits of XmY [12: 0] XmY [1
2: 8] is applied to the five inputs of the six-input NOR gate 42a. These 5 bits are used to detect that d is larger than 0xFF. Also, the NOR gate 42a
Zero is input to the remaining one input of the above, indicating that at least one of the inputs X and Y is 0 as described above. Therefore, the output of the NOR gate 42a is 0.
, The difference between X and Y is greater than 0xFF, or X and Y
It indicates that at least one of the two is 0. NOR
The output of the gate 42a becomes a signal called "pass" through the DFF 38g. This signal is copied by 6 bits and 6
The bit width is supplied to the AND gate 43.

Lower 8 bits XmY of XmY [12: 0]
[7: 0] is connected to the address input of the ROM 41.
This ROM stores the relation of (Equation 16), and has a structure of 256 words × 6 bits, and its data D and address A
Considering that the fractional part is 5 bits, the relation of D = 32 * log ₂ (1 + 2 ** (-A / 32)). ． ． (Equation 17) The output of the ROM 41 is a 6-bit wide DFF 3
It is input to the 2-input AND gate 43 having a width of 6 bits via 8f. The AND gate 43 takes an AND for each bit. The output of the AND gate 43 is a 6-bit width DFF.
After 38i, 0 for 7 bits is added to the upper side,
It enters the other input of the bit adder 44. One output of the DFF 38f is connected to one input of the AND gate 43, and the pass is connected to the other input. Therefore, the AND gate 43 sets the input to the adder 44 to 0 when pass is 0. Therefore, when d is larger than 0xFF, and at least one of X and Y is 0.
In the case of, 0 is added to the smaller one of X and Y, and the result is output to Z [12: 0]. If not, RO
The value read from M 41 is added to the smaller one of X and Y and output to Z [12: 0].

FIG. 6 shows an embodiment of the relative distance calculating means.
Here, three logarithmic expression adding means 45a, 45b, 45
c is used. Calculation performed by the relative distance calculation means r2 = Xij ** 2 + Yij ** 2 + Zij ** 2 + e ** 2 Among the squared operations, since Xij, Yij, Zij, and e are logarithmic expressions, 2 bits of the flag This is achieved by shifting the part except for 1 bit to the MSB side and giving 0 to LSB. For example, for Xij, Xij
[12], Xij [10], Xij [9], Xij
[8], ..., Xij [1], Xij [0], 0 will be given. In FIG. 6, this is designated as Xij [1
2, 10, ． 0], and 0. Yij, Zi
The same applies to j. Since the square is taken here, the result is always non-negative. Therefore, processing is performed with 13 bits excluding the logarithmic sign flag. Xij ** 2 and Y
ij ** 2 is given to the input of the logarithmic expression adding means 45a, and X
Get ij ** 2 + Yij ** 2. 1 of e-register 46
The squared e ** 2 and Zij ** 2 of the 3-bit output are given to the input of the logarithmic expression adding means 45b, and Zij ** 2 + e ** 2.
To get Further, these two addition results are given to the input of the logarithmic expression adding means 45c to obtain r2.

This 13-bit output r2 and h register 4
The 13-bit output h of 7 is applied to the 13-bit width subtracter 48, and the magnitude comparison is performed. The comparison result is output from the carry-out of the subtractor 48 to the outside of the integrated circuit 1 as the NB 16 via the inverter 49. If r2> = h, NB is 0,
If r2 <h, NB becomes 1.

The e register 46 and the h register 47 are loaded with values from the external bus 13 via the internal bus 12a. The external bus interface means 15 controls the load.

FIG. 7 shows an embodiment of the 1/2 power means. r2
Is a non-negative logarithmic expression. Therefore, in order to raise this to the power of 1/2, the non-flag portion r2 [11: 1] is shifted to the LSB side by 1 bit to r [10: 0], and r [11] is set to 0. And it is sufficient. Regarding the non-zero flag, r2 [12] is directly set to r [12]. This is because the 1/2 power of 0 is 0 and the 1/2 power of non-zero values is non-zero. The sign flag of the logarithmic representation is omitted because r2 and r are never negative due to the nature of the calculation target here.

FIG. 8 shows an embodiment of the 3/2 squaring means. r2
And r, which is its 1/2 power, are multiplied by a logarithmic expression multiplication means to obtain r3 which is 3/2 power of r2. The sign flag of the logarithmic expression is omitted because r2 and r are never negative due to the nature of the calculation target.

Both r3 and r are logarithmic representation division means 6
Before inputting to a and 6b, the sign flag is supplemented with 0 which means that the value is non-negative. Since Mj can take a negative value, the logarithmic expression division means 6a and 6b also handle the sign flag.

FIG. 9 shows an embodiment of the interaction force and potential calculation means. Both have the same configuration and the same operation, and the difference lies in the input / output data. Explaining the interaction force in the X coordinate axis direction, the pipeline register 19
Xj delayed to correct the pipeline stage difference at a and Mj / obtained by the logarithmic expression division means 6a.
When the product of r3 is taken by the logarithmic expression multiplication means 51, the interaction force in the X coordinate axis direction is obtained. The input data and output data of the three interaction force calculating means 7a, 7b, 7c and the potential calculating means 8 are summarized as follows.

Sign Input data Output data 7a Mj / r3, delayed Xij X component of interaction force 7b Mj / r3, delayed Yij Y component of interaction force 7c Mj / r3, delayed Zij interaction force Z component of 8 Mj / r, constant u potential In the embodiment, 0x1000, which is a logarithmic representation of 1 in the fixed point representation, is used for the constant u.

FIG. 10 shows an embodiment of the fixed point representation conversion means. This means is 5 bits x 32 words ROM 5
2, PLA 53, five 2-input AND gates 54,
It is composed of DFFs 55a, 55b, 55c and a shifter 56 for outputting 48 bits, and converts a 14-bit width logarithmic expression into a 48-bit width fixed point expression and a sign flag. YSign is a code flag.

Since X [4: 0] is the decimal part of the logarithmic expression, it is converted by the ROM 52 into the decimal part of the fixed point expression. If X [4: 0] is A and the output of the ROM is D, the relationship is D = 32 * (2 ** (A / 32) -1). However, if the non-zero flag X [12] of the logarithmic expression represents 0, that is, the logarithmic expression X represents 0, the decimal part of the fixed-point expression must also be 0. Therefore,
The AND gate 54 performs masking for that purpose. The output of the AND gate 54, X [1
2] is added as bit 5 to make a total of 6 bits, and DFF is added.
The input is y [5: 0] of the shifter 56 via 55c.
Since the ROM 52 outputs the value obtained by subtracting 1 from (2 ** (A / 32)) as the decimal part of the 5-bit width of the fixed-point representation, adding X [12] to bit 5
If X is non-zero, it is equivalent to adding 1 in the fixed-point representation, and thus a real number representing 2 ** (A / 32) is obtained in the fixed-point representation with a decimal width of 5 bits. On the other hand, if X is 0, X [12] is 0 and all the outputs of the AND gate 54 are 0, which is 0 even in the fixed-point representation. X [11: 5] determines where y [5: 0] is placed in the 48-bit width. X [11: 5] to PLA 53
The shift control signal of the shifter to the DFF 56b.
To the shifter via. PLA 53 has X [11:
5] is 67, y [5] is Y [47], and 20 is y.
A shift control signal is generated so that [5] appears in Y [0], that is, (value of X [11: 5]) − (Y bit position where Y [5] appears) = 20. All the locations of Y [47: 0] that do not correspond to y [5: 0] are zero.
The sign flag X [13] in the logarithmic expression is the DFF 55a.
Is output as a code flag as YSign.

FIG. 11 collectively shows an embodiment of the adding means for integration and the integrated value register means. These are a 56-bit wide inverter 57, a 56-bit wide 2-input multiplexer 58, a 56-bit wide adder 59, a 56-bit wide 2-input multiplexer 60, a 56-bit wide register 61,
Two 28-bit wide tri-state buffers 62a,
It is composed of 62b. The input given to the adder for accumulation is a 48-bit fixed decimal number (to be called Y [47: 0]) and a flag indicating its sign (to be called YSign). An 8-bit 0 is added to the MSB side of Y [47: 0] to form Y [55: 0]. Subsequent calculations are performed with a width of 56 bits. The inverter 57 inverts each bit of Y [55: 0], and outputs it to Y [5
5: 0] is given to the multiplexer 58 and selected by YSign. If YSign is 0, Y [55: 0] is output as it is, and if 1 is 1, the output of the inverter 57 is selected. The output of this multiplexer is applied to one input of the adder 59, the output of the register 61 is applied to the other input, and YSign is applied to the carry-in input. With this series of connections, YSign = 0, that is, Y [47:
0] is positive or when Y is 0 [47: 0] and the value of the integrated value register are added, and when YSign = 1, Y [4]
[7: 0] 2's complement is taken and added to the value of the integrated value register, that is, Y [47: 0] from the value of the integrated value register.
pull. The operation of taking the complement of 2 is to invert each bit and add 1 to it, but in the embodiment, the inverter 57 inverts the bit and YS is applied to the carry-in input of the adder 59.
1 is added by giving ign.

Normally, the output of the adder 59 is loaded into the integrated value register 61 via the multiplexer 60. However, when the integrated value register clear signal is given to the multiplexer 60, this multiplexer selects and outputs 0, and the register 61 loads the 56-bit wide input only when the register load signal is 1. Integrated value register 6
The output of 1 is supplied to one input of the adder 59 and the tristate buffers 62a and 62b as described above.

Two tri-state buffers 62a, 6
2b are both 28-bit wide, and one is integrated value register 6
The upper 28 bits of the output of 1 are input, and the other lower 28 bits of the output of the integrated value register are input. Both tri-state buffers are 28-bit wide internal bus 12
Drive b. The enable signal of each tri-state buffer, that is, the integrated value register read signal is generated by the external bus interface means 15.

FIG. 12 shows an embodiment of the external bus interface means. In the embodiment, a 3-bit register address A [2: 0], a chip select input CS, a write enable input WE, an output enable input OE, and a PC indicating whether operation is possible for the integrated circuit 1 are provided from the outside of the integrated circuit 1.
Bidirectional data bus DB [27:
0] is input. RA [2: except for PC 14:
0], CS, WE, OE, and DB [27: 0] form the external bus 13.

A [2: 0], CS, WE, and OE are asynchronous inputs to the clock of the integrated circuit 1. Therefore, they are input to the synchronizers 64a, 64b, 64c, and 64d which are synchronized with the clocks respectively, and their outputs are input to the register address decoder 66. It is CS that the integrated circuit 1 accepts the input from the external bus 13.
= 1 and WE = 1 and OE = 0, A [2: 0]
Internal register (Xi, Yi, Zi, e,
Corresponding to h), the register write signal is asserted. It is CS that the integrated circuit 1 outputs a value to the external bus 13.
= 1 and WE = 0 and OE = 1, A [2: 0]
28 of the upper or lower of the integrated value register specified by
The bit read signal is asserted. At the same time, the bus drive signal is asserted.

Data bus part DB [27: of the external bus 13]
0] is connected to the internal bus 12a via the DFF 68b, and the internal bus 12b outputs to DB [27: 0] via the DFF 68a and the tri-state buffer 65. The tri-state buffer 65 is controlled by delaying the bus drive signal by one clock by the DFF 67, and outputs the output of the DFF 68a, which functions as a latch, to DB [2 during the next cycle in which the bus drive signal is asserted.
7: 0], and if not, the high impedance state is entered.

As described above, each integrated value register drives the internal bus 12b through the tristate buffer. Therefore, the procedure for reading the integrated value register is as follows.

1 A [2: 0] and CS = 1, WE = 0,
Assert OE = 1.

Output from the synchronizer in synchronization with 2 clocks.

The 3-register address decoder 66 asserts the bus drive signal and the integrated value register upper / lower reading signal.

4 The upper or lower value of the corresponding integrated value register is output to the internal bus 12b.

The values of the bus drive signal and the internal bus 12b are DFF 67 and DFF, respectively, in synchronization with 5 clocks.
It is taken in by 68a.

6 The tri-state buffer 65 is driven, and the value of the DFF 68a is DB [27: 0].
Is output to.

On the other hand, in the case of writing to the internal register, the value of DB [27: 0] appears on the internal bus 12a via the DFF 68b, so that each internal register takes in the value of the internal bus 12a with a corresponding write signal.

The PC 14 is a DFF 69 connected in series.
To the DFF on the right side every one clock. The number of DFFs in the DFF 69 is Xj, Yj,
The number of pipeline stages from the input of Zj and Mj to the integrated value register 61 of the integrated value register means 11 is equal to -1, which is 14 in the embodiment.

According to the timing chart of FIG. 13, P
Generation of the integrated value register load signal 18 and the integrated value register zero clear signal 17 from the input of C will be described. Xj, Y
The values of j, Zj and Mj are input and calculated every cycle regardless of whether or not they are valid, and reach the input of the integrated value register 61 of the integrated value register means 11. X
When j, Yj, Zj, and Mj are valid, PC = 1 is input.
Conversely, when Xj, Yj, Zj, and Mj are invalid, PC = 0 is input. Valid Xj, Yj, Zj, and Mj are continuously given every cycle. In FIG. 13, time 0,
Valid Xj, Yj, Zj, and Mj are given to 1 and 2, and PC = 1 during this period, otherwise PC = 0. P
The value of C is DFF 69a, 69b, 69 for each clock.
c ,. ． ． It propagates with 69m and 69n at time 15,
In 16 and 17, the output of the DFF 69n becomes 1.
At time 15, the data such as Xj input at time 0, at time 16 the data such as Xj input at time 1, and at time 17 the data such as Xj input at time 2 are accumulated value registers. Appears at 61 inputs. Therefore, the integrated value register needs to be zero-cleared at time 14. This is the output 1 of DFF 69m and DFF 6
It suffices to simultaneously detect the 0 of the 9n output. This is done by the inverter 70 and the AND gate 72, and the AND gate 7
The output of 2 is the integrated value register zero clear signal 17.
By giving the integrated value register zero clear signal 17 at time 14 in FIG. 13, the value of the integrated value register becomes 0 at time 14. The accumulated value register is loaded only when its input has a valid value. That is, D
The output of the FF 69m and the output of the DFF 69n are OR gates 71
To the integrated value register load signal 18. In FIG. 13, the integrated value register load signal 18 becomes 1 at times 14, 15, 16, and 17. When the PC returns from 1 to 0, the output of the DFF 69n also becomes 0 after 14 cycles, and a new value is not loaded in the integrated value register and the value is held.

[0060]

The calculation of "calculating the distance between two points, calculating the interaction force and the potential, and integrating them once" processed by the processing apparatus of the present invention is performed by using 30 floating point numbers on the supercomputer. Equivalent to a command. The present invention performs pipeline processing, and the calculation can be apparently performed in one cycle. Therefore, when the processor constituted by the integrated circuit according to the present invention is operated at 30 MHz,
A processing capacity of 00MFlops can be obtained. This is almost equal to the performance of a super computer. The processing device according to the present invention can be constructed on an integrated circuit by standard CMOS technology, and its mass-production price is about the CPU chip of a general-purpose microprocessor, which is extremely inexpensive as compared with a super computer.

Furthermore, by operating a plurality of the integrated circuits of the present invention in parallel, it is possible to easily obtain a processing capacity proportional to the number of integrated circuits. As a result, it is easy to obtain a processing capacity larger than that of a super computer.

[Brief description of drawings]

FIG. 1 is a schematic configuration of the present invention.

FIG. 2 is a block diagram of an embodiment of a component difference calculation means.

FIG. 3 is a block diagram of an embodiment of a logarithmic expression multiplication means.

FIG. 4 is a block diagram of an embodiment of logarithmic representation division means.

FIG. 5 is a block diagram of an embodiment of a logarithmic addition unit.

FIG. 6 is a block diagram of an embodiment of relative distance calculation means.

FIG. 7 is a block diagram of an embodiment of 1/2 powering means.

FIG. 8 is a block diagram of an embodiment of a 3/2 squaring means.

FIG. 9 is a block diagram of an embodiment of interaction force calculation means and potential calculation means.

FIG. 10 is a block diagram of an embodiment of fixed point representation conversion means.

FIG. 11 is a block diagram of an embodiment of addition means for integration and an integrated value register.

FIG. 12 is a block diagram of an embodiment of external bus interface means.

FIG. 13 is a block diagram of a timing chart showing the operation of the embodiment of the integrated value register.

[Explanation of symbols]

1: integrated circuit, 2: relative position calculation means, 3: relative distance calculation means, 4: 1/2 power means, 5: 3/2 power means, 6: logarithmic expression division means, 7: interaction force calculation means, 8: potential calculation means, 9: fixed point representation conversion means, 10:
Addition means for integration, 11: integrated value register means, 12: internal bus, 13: external bus, 14: PC, 15: external bus interface means, 16: NB flag, 17: integrated value register zero clear signal, 18: integrated value Register load signal, 19: pipeline register, 20: component difference calculating means, 21: Xi, Yi, Zi register means, 2
2: AND gate, 23: ExOR gate, 24: Adder, 25: Subtractor, 26: ExOR gate, 29: Subtractor, 30: Adder, 31: 2-input multiplexer, 3
2: PLA, 33: shifter, 34: ROM, 35: comparator, 36: DFF, 37: subtractor, 38: DF
F, 39: 2 input multiplexer, 40: inverter,
41: ROM, 42: NOR gate, 43: AND gate, 44: Adder, 45: Logarithmic expression adding means, 46: e
Register, 47: h register, 48: subtractor, 49: inverter, 50: logarithmic expression multiplying means, 51: logarithmic expression multiplying means, 52: logarithmic decimal conversion ROM, 53: PLA, 5
4: AND gate, 55: DFF, 56: shifter, 5
7: Inverter, 58: 2 input multiplexer, 59:
Adder, 60: 2 input multiplexer, 61: register, 62: tristate buffer, 63: NAND gate, 64: synchronizer, 65: tristate buffer, 66: register address decoder, 67: DF
F, 68: DFF, 69: DFF, 70: inverter,
71: OR gate, 72: AND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Eri Hashimoto Eri Hinamoto 2274 Hongo, Ebina, Kanagawa Fuji Zero Tux Co., Ltd.Ebina Business Office (72) Nobuaki Miyagawa 2274 Hongo, Ebina, Kanagawa Fuji Zerox Co., Ltd.Ebina Business (72) Inventor Junichiro Makino 3-8-1, Komaba, Meguro-ku, Tokyo Inside the College of Arts and Sciences, The University of Tokyo (72) Inventor Sachiko Kawabe 3-8-1, Komaba, Meguro-ku, Tokyo Inside the College of Arts and Sciences (72) Inventor Tomoyoshi Ito 3-8-1, Komaba, Meguro-ku, Tokyo, Faculty of Arts and Sciences, The University of Tokyo (72) Inventor Shunichi Ebizaki 3-8-1, Komaba, Meguro-ku, Tokyo, Faculty of Arts and Sciences, University of Tokyo (72) Inventor, Sugimoto Univ. Ichiro 3-8-1, Komaba, Meguro-ku, Tokyo Inside the College of Arts and Sciences, The University of Tokyo

Claims (13)

[Claims] 1. A single integration for storing the coordinates of one center of mass point internally, giving the coordinates of the other center of mass point and the mass from the outside, and calculating gravity acting between these two points and gravity potential. In a processing device composed of a circuit, the processing for calculating inside the processing device is pipelined, the data of coordinates and mass are continuously supplied, and further, the calculated gravity and gravity potential are integrated. apparatus. 2. A single unit for storing the coordinates of one of the charge center points inside, giving the coordinates of the other charge center point and the charge from the outside, and calculating the electric force and electric force potential acting between these two points. In the processing device configured by the integrated circuit of, the processing of calculation inside the processing device is pipelined, the data of coordinates and charges are continuously supplied, and further, the calculated electric force and electric potential are integrated. Characteristic processing device. 3. Data inside the processing device or data given from the outside is expressed by the following logarithmic expression and a 1-bit non-zero flag representing non-zero added thereto and a 1-bit sign flag representing positive or negative of x. The processing apparatus according to claim 1 or 2, wherein When the data is a real number x, x = 2 ** (p / f). ． ． It is represented by (Formula 1). Here, ** is a symbol indicating a power, p is a binary number having a predetermined bit length, f is a constant, and f = 2 ** m. ． ． (Formula 2) However, m is a fraction part word length. 4. A difference between coordinate components at two points on a space represented by a coordinate expressed in fixed point and held inside the device and a coordinate expressed in fixed point and supplied from outside the device, Further, a relative position calculation means for expressing these component differences by the logarithmic expression, and r2 r2 = Xij ** 2 + Yij ** 2 + Zij ** 2 + e ** 2, which is the square of the distance between the two points, where Xij, Yij, Zij: Component difference Xij = Xj-Xi, Yij = Yj-Yi, Zij = Z
j-Zi Xi, Yi, Zi: Coordinates held inside the device Xj, Yj, Zj: Coordinates supplied from outside the device e: Relative distance calculating means for obtaining a constant using the logarithmic expression, and r2 is 1 / Calculate the value r squared by the logarithmic expression 1 /
Square means and a value r3 obtained by multiplying r2 by 3/2 by the logarithmic expression 3
/ Square means, two logarithmic expression dividing means for obtaining Mj / r3 and Mj / r by the logarithmic expression using the mass or charge Mj of the logarithmic expression given from the outside of the device, and each of the interaction forces Coordinate component Xij * Mj / r3, Y
Three interaction force calculating means and potential u for obtaining ij * Mj / r3 and Zij * Mj / r3 by the logarithmic expression.
* One potential calculation means for obtaining Mj / r (where u is a constant) by the logarithmic expression, and fixed point expression conversion means for converting these four calculated values from the logarithmic expression to the fixed point expression. The following four adding means for integrating each of these four values, four integrated value register means for holding each integrated value, r2 and the magnitude of the constant h are compared in the logarithmic expression. Comparator means for outputting the result as a flag to the outside of the apparatus, register means for holding the values of Xi, Yi, Zi, e and h, and four integrated value registers according to a register selection address signal given from the outside of the apparatus. Can be output to the external data bus via the internal bus, and the contents of Xi, Yi, Zi,
4. The processing apparatus according to claim 3, further comprising: external bus interface means capable of writing a value from an external bus via the internal bus to a register means for holding the values of e and h. 5. A signal of 0 indicating that the operation is possible for the processing device.
The rise from 1 to 1 is detected, the contents of the four integrated value register means are all set to 0, and the output of the adding means for integration is taken in while the signal indicating the operation is possible is 1 to indicate the operation is possible. 5. The processing apparatus according to claim 4, wherein the contents of the four integrated value register means are held while the signal is 0. 6. In the relative position calculation means, X,
Each of the Y and Z components has three component difference calculating means having the same configuration, and each component difference calculating means determines the positive or negative of the component difference and a means for checking whether the component difference is 0 or not. Means for obtaining the absolute value of the component difference and M for the absolute value of the component difference
Priority encoder means for detecting the number of 0s continuously arranged on the SB side, shifter means for shifting the absolute value of the component difference by a shift amount determined by the output result of the priority encoder means, and the output of the shifter means Logarithmic expression conversion interpolating means, and incrementing means for adding 1 to the output of the priority encoder means if a predetermined number of 1's from the MSB side are continuously arranged in the output of the shifter means. The processing device according to claim 4. 7. A logarithm representing a value of 2 ** (x / m) and 2 ** (y / m) in the calculation of Xij ** 2 + Yij ** 2 + Zij ** 2 + e ** 2 of the relative distance calculating means. From the expressions x and y, 2 ** (z / m) = 2 ** (x / m) +
A logarithmic expression adder for obtaining a logarithmic expression z representing a value of 2 ** (y / m), and means for comparing the magnitudes of x and y,
Means for obtaining the absolute value of the difference between x and y, logarithmic expression adder interpolating means for inputting the absolute value, and its output and x and y
A logarithmic expression adder which has a means for adding the lesser of the two, and whose output is z, and a logarithmic expression x representing the values 2 ** (x / m) and 2 ** (y / m). From y 2 ** (z / m) = (2 ** (x /
m)) * (2 ** (y / m)) is a logarithmic expression z
Is a logarithmic expression multiplier for obtaining the sign flag of x and y, and taking it as the sign flag of z.
And a non-zero flag of y, which is a non-zero flag of z, and a logarithmic expression multiplier which gives a part which is not a flag of x and y to an adder and is a part which is not a flag of z. The processing device according to claim 4. 8. The processing apparatus according to claim 6, wherein the logarithmic expression multiplier is used as the 3/2 means, and r3 is obtained by applying r2 and r to the logarithmic expression multiplier. 9. The logarithmic expression dividing means for obtaining Mj / r3 and Mj / r is a logarithmic expression x, y representing a value of 2 ** (x / m) and 2 ** (y / m) to 2 *. * (Z / m) = (2 ** (x /
m)) / (2 ** (y / m)) logarithmic expression z
Is a logarithmic expression divider that calculates ExOR of the sign flags of x and y, and sets it as the sign flag of z, and x
5. The process according to claim 4, wherein the non-zero flag of z is a non-zero flag of z, and a non-flag portion of x and y is given to a subtracter and a non-flag portion of z is used. apparatus. 10. The three interaction force calculation means are X
ij and Mj / r3, Yij and Mj / r3, and Zij
8. The processing apparatus according to claim 7, further comprising three logarithmic expression multipliers that respectively input and Mj / r3. 11. The potential calculation means comprises u and M.
8. The processing device according to claim 7, further comprising the logarithmic expression multiplier having j / r as an input. 12. A part of a part which is not a flag of logarithmic expression is given to the inverse transform interpolation means, and a non-zero flag of logarithmic expression is 0.
In the case of, the mask means for clearing the output of the inverse transform interpolation means to zero, and the shift means for shifting the output of the mask means according to another part other than the part of the logarithmic expression flag,
When the sign flag of the logarithmic expression means negative, the inverting means for inverting each bit of the output of the shift means, the means for sign extension with the MSB of the output of the inverting means, and the sign flag of the logarithmic expression are non-negative. Fixed point representation conversion means for converting from logarithmic representation to fixed point representation, and further comprising means for outputting 0 if it represents, and outputting 1 if it represents negative. 4. The processing device according to 4. 13. The processing apparatus according to claim 12, wherein the carry-in of the addition means for accumulation is supplied from the fixed point table conversion means.