JPH0587906U - Load drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the delay time of turning off the FET2 and reduce noise. [Structure] A diode D11 having a cathode on the side of FET1 is connected between the drain of FET1 and the gate of FET2.
Or transistor 6 between the gate of FET2 and ground
And the transistor 6 is controlled by the drive signal.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a load driving circuit.

[0002]

[Prior Art]

 For example, in an electronically controlled fuel injection internal combustion engine, an electromagnetic idle speed control valve is installed in the auxiliary air passage, and the auxiliary air flow rate is adjusted by controlling the opening of the idle speed control valve according to the engine state. However, as a drive circuit for driving this idle speed control valve, two solenoids for valve opening and valve closing are provided, and for valve opening and valve closing based on the drive signal with the duty ratio set. There is a device in which the two solenoids are alternately energized to drive the idle speed control valve (see Japanese Utility Model Laid-Open No. 60-134841).

In FIG. 3 showing a conventional load drive circuit for driving such a solenoid, an electric field effect transistor (hereinafter referred to as FET) 1 is a drain, a cathode is a diode D 1 on the drain side, and a valve for closing a valve as a load. It is connected to a power source via a solenoid 3, connected to ground at a source, and at a gate, a drive signal having a duty ratio set is input from a microcomputer (not shown) via a resistor R1. Like FET1, FET2 has a drain connected to the power source via the diode D3 on the drain side and the solenoid 4 for valve opening on the drain side, connected to ground at the source, and connected at the gate to the FET1 via resistors R3 and R5. It is connected to the drain. In addition, C1 and C2 connected between the gates of the FETs 1 and 2 are noise reducing capacitors, R2 and R4 are charge discharging resistors, D5 is a gate protection Zener diode of FET2, and D2 and D4 are respectively. It is a noise absorption diode connected to the power supply.

Further, the drain of the FET 2 is connected to a self-diagnosis circuit 5 for detecting disconnection / short circuit of the solenoids 3, 4 and the like. Next, the operation will be described. When the drive signal from the microcomputer rises from low level to high level, charging of the capacitor C1 via the resistor R1 starts, and when the gate voltage of the FET1 reaches a predetermined voltage, the FET1 is turned on and the power supply is turned on. Energization of the solenoid 3 is started, and the idle speed control valve is driven in the valve closing direction. While the solenoid 3 is energized, the FET 2 has a gate voltage of 0 and is therefore off, and the solenoid 4 is deenergized. Next, when the drive signal falls from the high level to the low level, the electric charge accumulated in the gate of the FET1 is discharged through the resistor R1 and the capacitor C1, the FET1 is turned off and the energization of the solenoid 3 is stopped. , The drain voltage goes high. Then, when the capacitor C2 is charged from the power source through the solenoid 3 and the resistors R5 and R3 and the gate voltage of the FET2 reaches a predetermined voltage, the FET2 is turned on to start energizing the solenoid 4 and the idle speed control valve operates. Driven in the valve opening direction. Therefore, the idle speed control valve is controlled to open according to the duty ratio of the drive signal.

As described above, the rise and fall of the gate voltages of the FETs 1 and 2 are moderated by the action of the resistor R1, the capacitor C1, the resistor R3, and the capacitor C2 connected between the gates of the FETs 1 and 2 and the ground. As a result, the turn-on time of FETs 1 and 2 becomes long, and a large current change disappears, so noise is reduced.

[0006]

[Problems to be solved by the device]

 However, in the conventional load drive circuit, the FET2 is turned on and off by using the low level and high level of the drain voltage by turning the FET1 on and off, and the gate of the FET2 includes the resistors R5 and R3 and the noise reduction circuit. The capacitor C2 is connected. Therefore, although the noise of the FET2 is reduced by the capacitor C2 and the resistor R3, when the FET1 is turned from ON to OFF or from OFF to ON as shown in FIG. 4 showing the drain voltage of the FET1 and FET2, The charge accumulated in the gate of the FET2 is not immediately charged / discharged, and a delay time occurs in turning the FET2 off and on with respect to the on / off of the FET1. In particular, when the FET1 is turned on, the FETs 1 and 2 are simultaneously turned on in the period T 2. Therefore, originally, in the load circuit that drives the idle speed control valve, the energization amount to the solenoids 3 and 4 is large, and the energization amount further increases when the FETs 1 and 2 are simultaneously turned on. There is a possibility that the change in current will increase and radiation noise will increase, resulting in malfunction.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a load drive circuit in which two field effect transistors are not simultaneously turned on.

[0008]

[Means for Solving the Problems]

 Therefore, the present invention has a first field effect transistor which has a capacitance at the gate and turns on to conduct current to a first load, and a capacitance at the gate, in which the first field effect transistor is turned on. And a second field effect transistor which is turned off when the first field effect transistor is turned on, and is turned on when the second field is turned off to energize a second load. A second electric field effect transistor is provided when the first field effect transistor is turned on. A discharge means for discharging the charge accumulated between the gate and the source of the effect transistor is provided.

[0009]

[Action]

 According to the above configuration, when the first field effect transistor is turned on, the electric charge accumulated between the gate and the source of the second field effect transistor is discharged by the discharging means. Turns off rapidly as the gate voltage drops. Therefore, when the first field effect transistor turns on, the delay time for turning off the second field effect transistor can be shortened, the simultaneous on state of two field effect transistors can be avoided, and noise can be reduced. Becomes

[0010]

【Example】

 An embodiment of the present invention will be described below with reference to FIGS. The same elements as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1 showing the first embodiment, FETs 1 and 2 are first and second field effect transistors, respectively, and a valve closing solenoid 3 and a valve opening solenoid 4 are first and second loads, respectively. A rectifying diode D11 as a discharging means has its cathode connected to the drain side of FET1 and connected between the drain of FET1 and the gate of FET2.

Next, the operation will be described. When the drive signal rises from the low level to the high level, the FET1 is turned on and the energization of the solenoid 3 is started, and the drain voltage of the FET1 becomes approximately 0V. At this time, since the cathode side and the anode side of the diode D11 become low level and high level, respectively, the diode D11 becomes conductive and the electric charge accumulated in the capacitor C2 is rapidly discharged to the ground via the diode D11 and the FET1. , FET2 turns off rapidly. Therefore, the FET2 is rapidly turned off, and the simultaneous ON state of the FETs 1 and 2 is avoided.

When the FET1 is off, the drain voltage is higher than the gate voltage of the FET2 and the diode D11 does not conduct. According to this structure, when the FET2 is turned off, the electric charge accumulated in the gate of the FET2 is discharged to the ground via the drain of the FET1 via the diode D11. The FETs 1 and 2 are turned off, and the simultaneous on-states of the FETs 1 and 2 are avoided. Therefore, since a large current does not flow at the same time, radiation noise is reduced, malfunction is prevented, and quality is improved.

Next, a second embodiment will be described. This type uses a bipolar transistor to discharge the electric charge accumulated in the gate of the second field effect transistor. In FIG. 2, an NPN bipolar transistor (hereinafter, simply referred to as a transistor) 6 has a collector connected to the gate of the FET 2, an emitter connected to the ground, and a base inputting a drive signal through a resistor R.

Next, the operation will be described. When the drive signal rises from the low level to the high level, the FET1 turns on and the transistor 6 also turns on. When the transistor 6 is turned on, the electric charge accumulated in the gate of the FET 2 is rapidly discharged to the ground via the collector and the emitter of the transistor 6. Therefore, the same effect can be obtained by using the transistor 6.

[0015]

[Effect of the device]

 As described above, according to the present invention, when the second field effect transistor is turned off, the electric charge accumulated in the gate of the second field effect transistor is discharged by the discharging means. When the field effect transistor is turned off, the second field effect transistor is turned off rapidly, and the simultaneous turn-on state of the first and second field effect transistors is avoided. Therefore, since a large current does not flow at the same time, radiation noise is reduced, malfunction is prevented, and quality is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a signal waveform diagram of FIG.

[Explanation of symbols]

 1, 2 Field effect transistor (FET) 3, 4 Solenoid 5 Self-diagnosis circuit D11 Diode 6 Transistor

Claims (1)

[Scope of utility model registration request] 1. A first field effect transistor having a gate having a capacitance and being turned on to conduct a current to a first load, and a gate having a capacitance and having a capacitance when the first field effect transistor is on. A load driving circuit comprising: a second field effect transistor that is turned off and is turned on when energized to energize a second load; A load driving circuit comprising a discharging means for discharging the electric charge accumulated between the gate and the source.