JPH0586199U - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a non-volatile semiconductor memory device with improved write / erase / read processing speed. [Structure] Writing / erasing / providing in block units
A read circuit and a control circuit for controlling each read / write circuit are provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a nonvolatile semiconductor memory device having a floating gate, capable of electrically writing and reading, and capable of erasing in block units.

[0002]

[Prior Art]

 4 to 7 are views showing a conventional nonvolatile semiconductor memory device disclosed in, for example, Japanese Patent Laid-Open No. 63-25981. FIG. 4 is a cross-sectional view (not to scale) of an EEPROM memory cell containing various layers grown and / or deposited on a P-type single crystal silicon substrate 10. First, as a preliminary step, a field oxide region (not shown) is grown on the P-type single crystal substrate 10 by a known method to a thickness of about 10,000 Å. Next, a first gate oxide region 40 is grown on the P-type single crystal substrate 10 to a film thickness of about 250 Å. Next, a first polysilicon layer is grown on the first oxide layer 40 to a thickness of about 3,000Å. Next, the first polysilicon layer is lightly dipped. Floating gate 60 is then formed from the first polysilicon layer using known masking and etching techniques. After formation of the floating gate 60, the inter-polyoxide 70 and the second gate oxide region 80 are co-grown in known manner. The interpolyoxide 70 is grown to about 800 to 850Å and the second gate oxide region 80 is grown to about 600Å. A second layer of polysilicon is then deposited over the interpolyoxide 70 and the second gate oxide region 80 to a thickness of about 4,500 Å and then doped. The control gate 90 is then formed from the second polysilicon layer by known masking and etching techniques. Finally, as is known, the source region 20 and the drain region 30 are formed by arsenic implantation.

The first gate oxide region 40 covers a portion of the P-type single crystal silicon substrate 10 in the region below the floating gate 60. The first gate oxide region 40 further overlaps a portion of the drain region 30 below the floating gate 60. The first gate oxide region 40 may be a silicon dioxide (SiO ₂ ) layer. The first gate oxide region 40 further includes a thin dielectric region 50. Using the known Kooi effect when forming the first gate oxide region 40, the portion of the first gate oxide region 40 designated as the dielectric thin film region 50 is the remaining portion of the first gate oxide region 40. The dielectric film region 50, which grows more slowly and is therefore thinner, forms the portion of the first gate oxide region 40 that overlaps the drain region 30. The dielectric thin film region 50 may be further extended to a region above the P-type single crystal silicon substrate 10 located between the drain region 30 and the source region 20. Although the dielectric thin film region 50 may be formed by any of the known methods for forming the dielectric thin film region, in this embodiment of the present invention, Kooi et al., `` Format ion of Silicon Nitride at a Si-Sio ₂ Interface During Local Oxidation of Silicon and During Heat-Treatment of Oxidized Silicon in NH ₃ Gas, 123j. Electrochemical Soeiety 1117 (July 1976) is used to form the electroconductive thin film region 50 by using the Kooi effect.

The first channel region 35 is a device channel portion located below the floating gate 60 and in contact with the drain region 30. A conductive channel of the charge carrier is formed in the first channel region 35 under the conditions described below. The second channel region 37 is a device channel portion located below the control gate 90 and in contact with the source region 20 but not extending below the floating gate 60. A conductive channel of the charge carrier is formed in the second channel region 37 under the conditions described below. The first channel region 35 and the second channel region 37 are simultaneously formed by P-type threshold adjustment implantation. The first gate oxide region 40 forms a dielectric layer between the first channel 35 and the floating gate 60. The first gate oxide region 40 further forms a dielectric region between a portion of the drain region 30 under the floating gate 60 and the floating gate 60. Floating gate 60 is a portion of the region of P-type single crystal substrate 10 grown on first gate oxide region 40 and extending about 0.2-0.3 μ over the portion of drain region 30 and in contact with drain region 30. Is formed so as to extend above. Floating gate 60 comprises a phosphorus-doped polysilicon layer used to store charge during programming of EE PROM memory cells, as described below. Interpolyoxide region 70 grows on floating gate 60. Interpolyoxide region 70 may be composed of an oxide or another equivalent dielectric known in the art.

The second gate oxide region 80 grows on the P-type single crystal substrate 10 and covers the portion of the P-type single crystal silicon substrate 10 that overlies the channel 37. The second gate oxide region 80 further overlaps the portion of the source region 20 located below the control gate 90. The interpolyoxide region 70 and the second gate oxide region 80 may be grown simultaneously as described above. Control gate 90 is formed over second gate oxide region 80 and interpolyoxide 70 and extends from drain region 30 to source region 20. The control gate 90 overlaps both the drain region 30 and the source region 20 by about 0.2 to 0.3 μ. Control gate 90 includes a layer formed of known phosphorus-doped polysilicon. Control gate 90 is more heavily doped than floating gate 60. The control gate 90 forms the control gate of the floating gate device where it overlaps the floating gate 60, and since the control gate 90 extends longer than the floating gate 60 and over a portion of the source region 20, the select transistor device is It also forms the control gate of. The function of the selection transistor portion of the EEPROM memory cell will be described later.

FIG. 5 is a second conventional example in which the first gate oxide region 40 is grown below the floating gate 60 to a uniform thickness. In this embodiment, masking, etching and oxide growth techniques known in the art are used to form a thin first gate oxide region 40 of uniform thickness. FIG. 6 shows a portion of an EEPROM memory array. First EEPROM cell 100, second EEPROM cell 110, third EEPROM cell 120 and fourth EEPROM cell 130 form part of an EEPROM memory array. FIG. 6 shows only a portion of the memory array. Therefore, in a 256 Kbit memory, there are typically 512 columns of EEPROM memory cells, each column containing 512 cells, or 512 rows and 512 columns. Any equivalent known array technology may be used as will be apparent to those skilled in the art. Therefore, in a 256 Kbit memory array, there may be 256 columns and 1024 rows of cells.

The drain of the first EEPROM cell 100 is connected to the first bit line 140. The drain of the second EEPROM cell 110 is also connected to the first bit line 140. In a typical EEPROM memory array, there will be one bit line for each column of EEPROM memory. That is, there would be 512 bit lines in a 256K memory array. Therefore, both the drain of the third EEPROM cell 120 and the drain of the fourth EEPROM cell would be connected to the second bit line 150. The control gate of the first EEPROM cell 100 is connected to the first word line 160. The control gate of the second EEPROM cell 110 is connected to the second word line 170. In a typical EEPROM memory array, there is one wordline for each row of EEPROM memory cells in the array. That is, there are 512 word lines in a 256 Kbit memory cell array. Thus, the control gate of the third EEPROM cell 120 is connected to the first word line 160 and the control gate of the fourth EEPROM cell 130 is connected to the second word line 17 0.

The source of the first EEPROM cell 100 is connected to the common line 180. The source of the second EEPROM cell 110 is also connected to common line 180. In a typical memory cell array using the present invention, there is one common line 180 for every pair of rows of EEPROM memory cells. That is, in a 256 Kbit memory cell array, there will be 256 common lines. As shown in FIG. 6, both the source of the third EEPROM memory cell 120 and the source of the fourth EEPROM memory cell 130 are connected to the common line 180. The drain of the first ground MOSFET device 190 is connected to the common line 180. The source of the first ground MOSFET device 190 is connected to ground line 210. The gate of the first ground MOSFET device 190 is connected to the first word line 16 0. Ground line 210 is connected to ground 220. The drain of the second ground MOSFET device 200 is connected to the common line 180. The source of the second ground MOSFET device 200 is connected to ground line 210. The gate of the second ground MOSFET device 200 is connected to the second word line 170. The voltage applied to the word line 160, that is, the voltage applied to the gate of the first MOSFET grounding device 190 is increased, or the voltage applied to the word line 170, that is, the voltage applied to the gate of the second MOSFET grounding device 200. Can be operatively connected to ground by raising the source of the first EEPROM cell 100, the source of the second EEPROM cell 110, the source of the third EEPROM 120 and the source of the fourth EEPROM cell 130. However, by keeping the gate of the first MOSFET grounding device 190 and the gate of the second MOSFET grounding device 200 low, the source of the first EEPROM cell 100 and the source of the second EEPROM cell 110 are The source of the third EEPROM cell 120 and the source of the fourth EEPROM cell 130 are kept floating, ie they are not connected to ground and are not held at any fixed voltage potential. Therefore, a selective grounding means was developed to ground the source of the EEPROM cell during programming and reading and to float the source during erase. Therefore, the cell conducts during programming and does not conduct during erase.

FIG. 7 is a schematic explanatory diagram of the operation of the EEPROM memory cell device and the ground device. The drain of the first EEPROM cell 100 is connected to the first bit line 140. The source of the first EEPROM cell 100 is connected to the common line 180. The drain of the first ground MOSFET device 190 is connected to the common line 180. The source of the first ground MOSFET device 190 is operably connected to ground 220 via ground line 210. The control gate of the first EEPROM cell 100 and the gate of the first grounding MOSFET device 190 are both connected to the first word line 160. There is more than one grounding MOSFET device in each row of the array. For example, there is one grounding MOSFET device for every 16-bit line in each row of the array.

Next, the operation will be described. Each cell of the EEPROM memory array has a storage location for information. The bit of memory associated with the cell is indicated by a binary code "0" or "1" state depending on whether the cell is conducting during the read mode. Erase all cells first before programming the EEPROM memory cell array. Electrically erasing the cell causes positive charge to accumulate on the floating gate. Therefore, an erased cell will conduct when tested for continuity during read mode. In a memory array using this preferred embodiment of the present invention, all cells of the EEPROM memory cell array are erased simultaneously. EEPROM memory cells that want to be in the binary "1" state during programming of the EEPROM memory cell array may store a negative charge on the floating gate during the programming mode. It will be apparent to those skilled in the art that any of a number of different configurations known in the art can be used to determine the order in which the cell's floating gate is loaded with negative charges. Therefore, one byte of cells may be written at the same time, or in any order.

Erase Mode According to FIG. 7, when it is desired to erase an EEPROM memory cell, the first word line 160 is grounded. The first bit line 140 is at a potential in the range of about 17-20 volts. Therefore, there is a high voltage difference between the drain and the floating gate of the first EEPROM cell 100. Under this condition, if a high positive voltage exists in the drain of the first EEPROM cell 100, the electrons accumulated in the floating gate of the first EEPROM cell 100 will be attracted to the drain of the first EEPROM cell 100. Electrons, as known to those skilled in the art, then tunnel from floating gate 60 to drain region 30 through dielectric film region 50 as shown in FIG. As a result, the floating gate of the first EEPROM cell 100 is discharged. In addition, the first grounding MOSFET device 190 is non-conductive because the first grounding MOSFET device 190 is operatively connected to ground through the first word line 160. Therefore, the source of the first EEPROM cell 100 is floating. Therefore, the first EEPROM cell 100 does not conduct. In the conventional example, all cells of the memory array are erased at the same time. That is, all word lines 160 in the array are grounded and all bit lines in the array are at an erase potential of about 17-20 volts. Therefore, the cells of the array are erased as described above. In the example shown in FIG. 5, the tenth gate oxide region 40 is grown below the floating gate 60 as a uniform film. The first gate oxide region 40 may be grown to a film thickness of about 200Å, for example. In this example, when the EEPROM memory cell is erased, electrons tunnel through the first gate oxide region 40 in the same manner as described above, and it takes about 1 second to erase.

Write Mode When it is desired to write a binary “1” to the first EEPROM cell 100, the first bit line 14 0 is brought to a potential of about 10V. However, other voltages can be used as is known in the art. The voltage on the first word line 160 is in the range of about 17-20V. Therefore, the drain of the first EEPROM cell 100 will be at a voltage of about 10V and the control gate of the first EEPROM cell 100 will be at a higher potential of about 17-20V. The first grounding MOSFET device 190 is conductive because the gate of the first grounding MOSFET device 190 is maintained at the higher potential by the first word line 160. Thus, the first grounding MOSFET device 190 is conductive and the source of the first EEPROM cell 100 is operatively connected to ground 220 via the common line 180 and the first grounding MOSFET device 190. In this condition the first EEPROM cell 100 will be programmed using the hot electron injection phenomenon known in the art. According to FIG. 4, control gate 90 is maintained at about 17-20V, drain region 30 is maintained at about 10V, and source region 20 is operatively connected to ground. Control gate 90 is maintained at a very high voltage so that an N-channel is formed between drain region 30 and source region 20. Under this condition, a current in the form of negative electrons flows from the source region 20 to the drain region 30 via the second channel 37 and the first channel 35. Frohnan-Bent chkowsky, `` FAMOS-A New Semiconductor Charge Storage Devicej, Solid-Stat e Electro-nics, Vol. 17, p. Electrons will accumulate, ie, some of the electrons that flow into the first channel 35 will pass through the gate oxide region 40 in the direction of the floating gate 60 under the influence of the positive attraction potential directed to the floating gate 60. , Some electrons are deposited on the floating gate 60, thereby filling the floating gate 60 with a negative charge, and writing takes about 10 μs.

Read Mode and Select Transistor Operation During the read mode it is necessary to determine whether the floating gate 60 above the EEPROM memory cell means is charged with positive or negative charge. No current flows through the EEPROM memory cell means during the read mode when the floating gate 60 is filled with negative charge. Conversely, current flows through the EEPROM memory cell means during the read mode when the floating gate 60 is filled with positive charge. According to FIG. 6, when reading the first EEPROM memory cell 100, the first word line 160 is about 5V and the first bit line 140 is about 2V. All remaining word lines and all remaining bit lines in the EEPROM memory cell are grounded. Therefore, the second word line 170 is grounded. The gate 60 of the first grounding MOSFET device 190 is maintained at about 5V by the first word line 160, so that the first grounding MOSFET device 190 is biased conductive. That is, the first ground MOSFET device 190 is in a conductive state. Thus, the source of the first EEPROM memory cell 100 is operatively connected to the ground 220 via the common line 180, the first ground MOSFET device 190 and the ground line 210. The drain of the first EEPROM memory cell 100 is maintained at about 2V by the first bit line 140. Furthermore, the control gate 90 of the select transistor portion of the first EEPROM memory cell 100 is maintained at about 5V, so that the select transistor of the first EEPROM memory cell 100 is conductive. That is, the first EEPROM memory cell 100 is conducting or non-conducting depending on the charge state of the floating gate 60. That is, when the floating gate 60 of the first EEPROM cell 100 is filled with positive charge, a conduction channel will be formed in the first channel region 35 of FIG. 4 and the first EEPROM cell 100 will conduct. However, when the floating gate 60 of FIG. 4 is filled with electrons, a conduction channel is not formed in the first channel region 35 of FIG. Therefore, the first EEPROM cell 100 will not conduct. The drain of the second EEPROM cell 110 is maintained at about 2V by the first bit line 140, and the source of the second EEPROM cell 110 is operatively connected to ground through the first grounding MOSFET device 190. Will be understood. Thus, when the floating gate of the second EEPROM cell 110 is filled with positive charge, a conducting channel of the channel region 35 of FIG. 4 is formed and the MOSFET below the floating gate 60 will be conducting. However, the control gate 90 of the second EEPROM cell 110 is kept low by the second word line 170. Therefore, no conduction channel is formed in the second channel 37 of FIG. 4, and the selection transistor of the second EEPROM cell 110 is in the non-conduction state. Therefore, even if the drain of the second EEPROM cell 110 is maintained at about 2V, the source of the second EEPROM cell 110 is maintained at a low value and the floating gate of the second EEPROM cell 110 is filled with positive charge. This is because the control gate 90, which also forms the gate of the select transistor portion of the second EEPROM cell 110, is held low by the second word line 170. The second EEPROM cell 110 does not conduct. Reading is as fast as several 100 ms.

[0014]

[Problems to be Solved by the Invention]

 Since the conventional nonvolatile semiconductor memory device is configured as described above, erasing requires 1 sec / block time. In contrast, writing is 10 μsec / byte, and reading is 100 nsec / byte, which is faster than erasing. Therefore, there is a problem that the erasing time is long.

The present invention has been made to solve the above problems, and an object thereof is to obtain a non-volatile semiconductor memory device in which the erase time of the memory is shortened.

[0016]

[Means for Solving the Problems]

 The non-volatile semiconductor memory device according to the present invention comprises a write / erase / read circuit provided in block units and a control circuit for controlling each read / write circuit.

[0017]

[Action]

 The non-volatile semiconductor memory device according to the present invention can write / read other blocks even during erasing,

[0018]

【Example】

 Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a nonvolatile semiconductor memory device including claims 1 to 3 of the present invention, and FIG. 2 is a sectional view showing the structure of a memory cell. In the block, a control gate 4 is a word line and a drain 2 Are connected to a bit line, and the source 3 is connected to a common source line in the block. FIG. 3 shows a state in which memory cells are arranged in an array in a certain block. In the figure, WL is a word line, BLI is a bit line, SL is a source line, and YGI is a Y gate. Table 1 shows voltage conditions at the time of reading / writing / erasing of the nonvolatile semiconductor device.

[0019]

[Table 1]

Next, the operation will be described. FIG. 1 shows an example in which the block is divided into four blocks, and one erase circuit is selected by two address inputs. Now, when the block 2 is in the erased state, all the outputs of the X decoder 2 become Ov, the output from the Y decoder makes the Y gate non-conducting state, and the bit line BLI becomes floating. Then, a high voltage of 10v is output from the erasing circuit 2, 10v is added to the source line SL, and all the memory in the block 2 is erased. When writing to the block 3 in this state, one of the X decoders 3 becomes 12v in the selected state by the address input, and one of the Y gates 3 selected by the Y decoder 3 is selected. The book becomes conductive, one bit line BLI is supplied with a high voltage from the write circuit and 6v is applied, and the erase circuit becomes 0v and is written. Then, by changing the address input, it is possible to write to all the memories of the block 3. This is the same when writing to block 1 and block 4. When the block 2 is in the erased state and the block 3 is read, the states of the X decoder 3, the Y decoder 3, the Y gate 3 and the erase circuit 3 are the same, but the voltage condition is the condition at the time of reading. . Also, the read / write circuit is switched to the read circuit, that is, the sense amplifier, and is read. The switching of the read / write circuit and the voltage condition are controlled by the control circuit which receives the control signal. As described above, writing or reading can be performed while erasing in the device. Further, in this invention, since the erase block storage circuit is provided, the block information being erased is stored. As a result, when a signal for writing / reading is accessed in the block being erased, information can be taken out from the data input / output circuit, and it can be notified to the outside that access is impossible.

[0021]

[Effect of the device]

 As described above, according to the present invention, since the writing / erasing / reading circuit provided for each block and the control circuit for controlling each writing / erasing / reading circuit are provided, some blocks are not provided. It is possible to write / read to / from other blocks even during erasing, and it is possible to obtain the effect of improving the processing speed of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration of a memory cell according to a first embodiment of the present invention.

FIG. 3 is a layout diagram of a memory cell array in a block according to a first embodiment of the present invention.

FIG. 4 is a step diagram showing a configuration of a conventional memory cell.

FIG. 5 is a cross-sectional view showing a configuration of a conventional memory cell.

FIG. 6 is a layout view of a conventional memory cell array.

FIG. 7 is a partial view of a conventional memory cell array.

[Explanation of symbols]

 1 Non-volatile semiconductor memory device BL bit line SL source line WL word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (3)

[Scope of utility model registration request] 1. A non-volatile semiconductor memory device comprising a plurality of blocks in which a plurality of insulated gate type memory transistors having floating gates are arranged in a matrix to form one block, and the blocks can be erased. A non-volatile semiconductor memory device characterized in that other blocks can be written therein. 2. A nonvolatile semiconductor memory device comprising a plurality of blocks in which a plurality of insulated gate memory transistors having floating gates are arranged in a matrix to form one block, and the blocks can be erased in block units. A non-volatile semiconductor memory device characterized in that other blocks can be read therein. 3. A non-volatile semiconductor memory device comprising a plurality of blocks in which a plurality of insulated gate memory transistors having floating gates are arranged in a matrix to form one block A non-volatile semiconductor memory device, which outputs an inaccessible signal when a signal for writing or reading to a block is accessed.