JPH0586092B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to an error signal correlation detection circuit such as a tap weight control circuit of a cross-polarization interference compensation device, such as automatic waveform equalization using a transversal filter. (Background Art) A conventional circuit will be explained using a 2 ³ =8-value signal as an example of a received signal. The 8-value signal is a signal normally used in the 64QAM communication system. In other words, the 64QAM signal is a signal having a state of 8×8=64 values because signals with 8-value amplitudes are arranged in-phase and orthogonally. FIG. 7 shows an example of the basic configuration of a receiving system for the 64QAM communication system. 100 is a receiving antenna, and 101 is a receiver, whose main function here is to convert the frequency from the RF band to the IF band. A demodulator 102 demodulates a signal having eight amplitude levels. Usually a quadrature detector is used. 103 is an A/D converter for identifying and reproducing demodulated signals. A waveform equalizer 104 is used to reduce waveform distortion caused by fading and the like, and a transversal filter is used. Note that this figure shows an example of a normal transmission system, so 1
Although 04 is a waveform equalizer, in the case of a communication system equipped with a cross-polarization interference compensation function, 104 may be replaced with an interference compensator instead of the waveform equalizer. 1
05 is the output point of the identified and reproduced data string. FIG. 8 shows a specific example of the configuration of the transversal filter circuit. This consists of a filter section 1040 and a control circuit 1041. The filter section 1040 includes seven stages of delay elements 1040-a, multipliers 1040-b provided corresponding to each delay element, and an adder 1040-c that adds the outputs of each multiplier. One delay element delays the input signal by a time corresponding to a clock period.
The control circuit 1041 applies a control signal C _-3 to the multiplier.
~C ₃ is produced. The present invention relates to a novel configuration of this control circuit. As shown in FIG. 1, a 4-bit or more A/D converter is used to identify and reproduce the detected signal for the 8-value signal. Note that this figure is an example when natural code arrangement is used, and the A/D converter outputs the result of counting the 8-value signal points from the top in binary numbers. That is, this is an example in which the most significant signal is identified as bits (1, 1, 1), and the least significant signal is identified as bits (0, 0, 0). Of course, if the code arrangement is changed to, for example, a Gray code arrangement, the relationship between signal points and identification bits will be different, but the present invention is naturally applicable to that case as well. As shown in Figure 1, in the case of natural code arrangement, the most significant bit of the identification bits is the result of identification to divide the input range into two (this is called identification of Path1), and the top two The bit number is the result of further dividing the whole into two equal parts, that is, dividing the whole into four equal parts (this is called identification of Path2),
The upper 3rd bit is the result of further dividing the whole into 2 equal parts, that is, the result of dividing the whole into 8 equal parts, and the upper 4
The bit number is the result of dividing the whole into 16 equal parts. In other words, the identification level of the upper 4th bit is
This is the signal point position of the transmitted signal (this is Path4
It is called identification. ). Therefore, the upper three bits represent the identification result of the received signal. For example, in the case of natural code arrangement,
The highest level signal point is identified as (1, 1, 1), the fifth signal point from the top as (0, 1, 1), and the lowest signal point as (0, 0, 0). be done. Furthermore, the value of Path4 indicates the direction of change of the received signal with the transmitted signal point as the threshold value. In other words, it is desirable to have the highest noise margin when the received amplitude corresponds to the vicinity of the signal point, so it is natural to transmit at such a level when transmitting, but the receiving side may be affected by the received amplitude due to intersymbol interference during transmission, etc. It is normal for the signal point to shift either above or below the signal point. Accordingly
It can be said that the value of Path4 represents the direction of intersymbol interference. That is, if the received signal changes in the positive direction compared to the transmitted signal, Path4=1, and if it changes in the negative direction, Path4=0. Conventionally, for waveform automatic equalizers and cross-polarization interference compensators using transversal filters, the ZF (Zero-Forcing) method has been used in tap weight control circuits that control the tap weight circuits, especially in high-speed regions. It was used. Regarding the transversal filter control circuit 1041 shown in FIG. 8, a specific configuration corresponding to the ZF method is shown in FIG. Here, signal 1 of Path1 represents the polarity of the signal, and signal 1 represents the direction of intersymbol interference.
Take 2 bits of signal 2 of Path4 as the input signal,
clock period delay circuits 3, 4, 5, 6, respectively.
7, 8, 9, 10, and exclusive OR circuits 11 and 1 that take correlations in different cycle periods, respectively.
2, 13, 14, 15, 16, 17, its output M
Integrating circuits 18, 19, 2 for integrating the required bits for the set (FIG. 2 shows the case where M=5)
It was composed of 0, 21, 22, 23, and 24. In wireless signal transmission, the modulator input signal on the transmitting side is almost always bipolar due to the configuration of the transceiver. Therefore, even on the receiving side, the demodulator output (A/D converter input) becomes bipolar. For example, in Figure 1, the level indicated by the dashed line between the fourth and fifth signal points from the top is zero level,
A value larger than that is positive, and a value smaller than that is negative. Therefore, Path1 represents the polarity of the signal. In the ZF method, control is performed using only the signal representing the polarity of the signal (Path 1) and the signal representing the direction of intersymbol interference (Path 4), which represent the direction of error, and the signal representing the absolute amount of error. Therefore, this output signal is constant regardless of the amount of intersymbol interference of the 8-level signal, so when the amount of intersymbol interference is large, that is, when the amount of distortion is large, control convergence is poor and the entire device This was a cause of deterioration of the characteristics of the product. (Problem to be solved by the invention) In order to solve the above-mentioned drawbacks, the present invention takes into account not only the direction but also the absolute amount of the error signal, and tap weight control that weights the error signal according to the amount using only a digital logic circuit. It provides a circuit for obtaining signals. (Structure and operation of the invention) A case will be described in which an embodiment of the invention is applied to the ZF method, which is a control method for a transversal automatic equalizer. Figure 3 shows a control circuit for a 64QAM 7-tap transversal filter. Delay elements 29-36 are the same as delay elements 3-10 of the conventional circuit shown in FIG. Exclusive OR circuit 45
51 are the same as 11 to 17 of the conventional circuit. Integrators 52-58 are different from conventional integrators 18-24 to reflect the features of the present invention, as will be described later. Further, delay elements 37 to 44 are newly provided here. This is the signal input from input points 27 and 28 (Path5' and Path6' as described later)
This is to match the time of the signal inputted from the input point 26 (Path 4). As shown in FIG. 4, the 8-value signal (64QAM demodulated signal) is digitized by a 6-bit A/D converter. Generally, in the case of a ²ⁿ value signal, an A/D converter having an accuracy of (n+2) bits or more is used. As a result, Path1 to Path4 are the same as in FIG. Path4 and
As shown in Figure 5, the results of the exclusive OR of Path5 (referred to as Path5') and the results of the exclusive OR of Path4 and Path6 (referred to as Path6')
The amount of intersymbol interference can be evaluated in four stages using the two bits Path5' and Path6'. In other words, it can be said that the closer the received signal is to the transmitted signal, the smaller the intersymbol interference is, and the farther away from the transmitted signal, the larger the intersymbol interference becomes. closest to the point, both of which are 0
Since the state where is the farthest from the signal point,
This is because Path5' and Path6' can represent the magnitude of intersymbol interference. Figure 5 clarifies this point. Generally, when the detection bit of the amount of intersymbol interference is A (A: an integer), it can be evaluated in 2 ^A stages. In the present invention, as a signal used for controlling the tap,
A Path1 signal representing the polarity of the signal, a Path4 signal representing the direction of intersymbol interference, and Path5' and Path6' signals representing the amount of intersymbol interference are used. The signal of Path1 comes from the input point 25, the signal of Path4 comes from the input point 26, and the signals of Path5' and Path6' come from the input points 27 and 2, respectively.
It is input from 8. The processing of the Path1 signal and the Path4 signal is the same as in the conventional example, and the outputs of the exclusive OR circuits 45 to 51 determine the counting direction (in other words, up direction or down direction) of the up/down counter that constitutes the integrator. give. In the present invention
A tap weight control signal is obtained by changing the count amount of the upda counter, that is, the integration time constant, using the signals of Path5' and Path6'. Specifically, the number of stages of the up-down counter is also variable in four stages according to the amount of intersymbol interference in four stages.
In other words, when the amount of intersymbol interference is minimum (Path5′=
Path6' = 1) is the case where the number of counter stages is the largest, the control speed can be slow, so high-precision control is performed, and the amount of intersymbol interference is the maximum (Path5' =
Path6'=0) has the smallest number of counter stages to enable high-speed control. FIG. 6 shows a specific configuration example of a counter for executing the above operations. For example, 8191 bits or (2 ¹³ −
1) A 13-stage counter is required for bit-by-bit integration. Except for the stage number control section consisting of AND circuits 70-73 and inverters 74-77, this is the same as a known up-down counter. Input point 62
is a count direction designation signal input point, into which the output signal of the exclusive OR circuit 45 etc. in FIG. 3 is input. 59 is a clock path input point which is a count pulse, 60 is a Path5' signal input point, and 61 is a Path6' signal input point. When the amount of intersymbol interference is minimum, that is, when Path5'=Path6'=1, gate 70 is turned on, so T-flip-flops 63 to 69 operate, and the number of counter stages becomes maximum. And vice versa
Since the gate 73 is turned on when Path5'=Path6'=0, the T-flip-flops 66 to 69 operate, so that the number of counter stages is minimized. As described above, the number of stages can be made variable according to the amount of intersymbol interference. Then, by arbitrarily extracting K bits from the highest stage of the counter according to the required accuracy of the tap weight control signal, a tap weight control signal having K bit accuracy can be obtained. With the above configuration, the integrator automatically shortens the integration time of the integrator when the amount of intersymbol interference is large, and lengthens the integration time of the integrator when the amount of intersymbol interference is small. By switching the time constant of , control accuracy and convergence can be improved. The above is a case where the ZF method is applied, but the control algorithm of the transversal equalizer mainly integrates the multi-value level of the input or output signal and the output error signal. It is clear that selecting the digit position of the counter input by looking at the magnitude of the output error signal can be applied to all the algorithms shown in Table 1.

[Table] (Effects of the Invention) As described above, this error signal correlation detection circuit uses the upper p-down counter to quickly converge control when the amount of intersymbol interference is large. By connecting a count pulse to the stage and automatically switching to output a stable control signal by slowing down the control speed and lengthening the integration time when the amount is small, overall characteristics can be improved. A tap weight control signal can be obtained that enables the tap weight control signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional identification method, FIG. 2 is a conventional tap weight control circuit, FIG. 3 is a control circuit according to the present invention, and FIG. 4 is a diagram showing a classification method according to the present invention.
FIG. 5 is a diagram showing intersymbol interference between Path5' and Path6', and FIG. 6 is a block diagram of the up-down counter. FIG. 7 shows an example of the configuration of a receiving system for a 64QAM communication system, and FIG. 8 shows an example of the configuration of a waveform equalizer using a transversal filter. 1...Polar signal input terminal, 2...Error signal (direction of intersymbol interference) input terminal, 3, 4, 5, 6,
7, 8, 9, 10...clock period delay circuit, 1
1, 12, 13, 14, 15, 16, 17...exclusive OR circuit, 18, 19, 20, 21, 2
2, 23, 24...Integrator, 25...Polar signal input terminal, 26...Bit input terminal indicating the direction of intersymbol interference, 27, 28...Bit input terminal indicating the amount of intersymbol interference, 29- 44... Clock cycle delay circuit, 45-51... Exclusive OR circuit, 52
~58...Integrator, 59...Count pulse input terminal, 60, 61...Bit input terminal indicating the amount of intersymbol interference, 62...〓p-down control signal,
63-69...T-flipflop, 70-7
3...3-input AND circuit, 74-78...inverting circuit, 79-95...2-input NAND circuit, 96-
98...2 input OR circuit.

Claims (1)

[Claims] 1 2 J for identifying a multi-value signal with ^N values (N: integer)
A first delay element array 2 that delays the most significant bit (MSB) of the A/D converter output with (J: an integer of J≧N+2) bit precision in units of clock cycles.
9, 30, 31, 22, a second delay element array 33, 34, 35, 36 that delays the upper (N+1) bit data of the output of the A/D converter in clock cycle units; At least one delay element array having the same configuration as the second delay element array for delaying a signal representing the amount of intersymbol interference generated based on the output from the upper (N+1)th bit of the D converter in units of clock cycles. A third delay element array including delay element arrays 37, 38, 39, and 40, and an exclusive OR of output signals having different delay amounts from the first delay element array and the second delay element array. Exclusive OR circuit arrays 45, 46, 4
7, 48, 49, 50, , 51, and counter rows 52, 53, 5 that add or subtract clocks according to the output of the exclusive OR circuit row.
4, 55, 56, 57, and 58 to obtain the tap control signal of the transversal filter, the circuit is configured to obtain the tap control signal of the transversal filter according to the signal representing the amount of intersymbol interference output from the third delay element array. An error signal correlation detection circuit characterized in that the number of count stages of a counter string is made variable.