JPH058572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD This invention relates to a method of forming electrical contact between a region of a semiconductor substrate and an interconnect layer.

[Prior art]

For making electrical contact between doped (or doped) regions of a semiconductor substrate, such as the source and drain regions of a field effect transistor, and a doped polycrystalline silicon (hereinafter referred to as "poly") interconnect layer. One method is to use the LOCOS (local oxidation of silicon) method to define the active area, followed by the formation of a gate oxide layer and the creation of a fairly large contact cut to expose the substrate. formation, deposition of poly layer,
Steps include defining and etching the poly layer with predetermined spacing, removing residual gate oxide, and co-diffusion of dopants into the poly and exposed substrate. Exemplary aforementioned methods including steps for forming contact between a poly layer and a substrate are described in U.S. Pat. No. 4,268,321, No. 14
As depicted in FIGS.

In describing preferred embodiments of the present invention, the method or process of the present invention will be described below in contrast to conventional processes.

[Disclosure of the invention]

In accordance with the present invention, a method for making electrical contact between a first region of a semiconductor substrate and an interconnect layer includes defining a second region on the substrate;
doping the defined second region with an impurity type dopant at a concentration suitable to form a depletion mode channel; removing a section or segment to expose it, forming a dopable interconnect layer to completely cover the section of the substrate, and forming the dopable interconnect layer without exposing the section of the substrate; The method includes the steps of defining, masking and etching a layer and doping the first region of the substrate and the interconnect layer with a dopant of the given impurity type.

The method according to the invention is that damage to the substrate surface next to the contact is avoided by the dielectric layer. This method is useful for fabricating insulated gate field effect transistors (IGFETs) with self-aligned gates and entirely single-doped poly. Besides, this method also allows the poly layer,
The sequence of steps can be maintained to simultaneously dope the source and drain (S/D) regions and any other conductive regions of the substrate.

The embodiments described in the brief summary above include implanting dopants early in wafer fabrication. The process creates a parasitic depletion channel near the surface of the substrate that generally surrounds the area that will become the contact cut. Later in the process, contact cuts are made through the protective dielectric layer using a patterned photoresist and an etchant that does not attack the silicon substrate. This exposes the substrate surface underlying the area of the contact cut. A first poly layer is then deposited over the wafer. Photoresist patterning followed by poly etching
During sequencing, the poly covering the exposed substrate at the contact cut remains in place and extends from there slightly to and slightly overlaps the adjacent dielectric layer. In this manner, the substrate surface at the cut will be masked by the poly, so that the silicon substrate will not be attacked by the etchant used to remove the poly areas. Without such a method, the etchant easily erodes the substrate silicon. Subsequent processing steps remove the exposed dielectric and diffuse dopants into the exposed poly and substrate areas.

Typically, the poly acts as a mask for the etchant when the dielectric layer is etched. This unetched dielectric is removed during subsequent dopant diffusion into the exposed poly and substrate.
Acts as a dopant barrier. Thereby, the dielectric surrounding the contact cut prevents the dopants from reaching the substrate directly below, and in effect separates the poly layer connected through the contact cut from the doped region of the substrate to a predetermined electrical resistance. Separate (dekatupuru) with . but,
The ion implantation performed early in the process creates a poly-to-substrate connection between the conductively doped substrate region immediately adjacent to the contact cut and the contact cut. This is ensured by the presence of parasitic depletion channels that are electrically connected by buried contacts. Typically, this adjacent region is the S/D of the IGFET.
It is an electrode.

A parasitic IGFET that connects a poly interconnect electrode to a conductively doped region of the substrate is limited in its current carrying capacity, but when the conductive region is the S/D region of the IGFET, that region is connected to the conductively doped region of the substrate. are simultaneously accessible through passages in the doped regions. Therefore, the S/D electrodes of this IGFET can be connected directly through high current doped paths or low current poly interconnect paths in the substrate without complicating the entire manufacturing process or causing surface damage to the substrate. I can do it. These and other advantageous aspects of the invention will become apparent from an understanding of the disclosure set forth below.

〔Example〕

This example uses the well-known local oxidation of silicon, that is, the LOCOS method, to create an IGFET with the same impurity type poly layer and a self-aligned gate structure. A method (process) is disclosed for forming a contact between. The differences between the conventional process and the process according to this embodiment will be more clearly understood after considering the approaches individually.

First, we consider the conventional process and its IGFET performance results. Figures 1, 2, 3 and 5 summarize the main processes of manufacturing an IGFET device according to conventional processes, focusing on the formation of contacts between the poly layer and the substrate. be. These figures are cross-sectional views taken along a perpendicular plane, as well as views showing the structure obliquely. FIG. 1 schematically illustrates one stage of the LOCOS process, particularly representing a corner of the active area. The active region of the substrate 2 (generally designated 1) is bordered by a field region (field oxide) 3 of thermally grown silicon dioxide. Cell and channel stopper (not shown) below field oxide
The ion implantation for setting is done early in the process using the well-known LOCOS method.

A gate dielectric layer 4 of silicon dioxide (gate oxide) covers the exposed surface of the active region 1 .

By the way, while the relative dimensions of each layer are important in understanding the steps in subsequent steps, the figures are not drawn to scale to represent the actual structure.
Rather, it should be noted that these are global depictions of the organization and only provide insight into the results of successive processing steps.
A typical embodiment includes a gate oxide layer of approximately 700 Å;
It includes field oxide ranging in thickness to 13000 Å and poly layers each having a thickness of about 4000 Å.

Some processes should not be overlooked in understanding the various steps that characterize conventional processes. For example, processes that simultaneously form a poly layer on both the gate electrode and the interconnect electrode, processes that ensure that the gate electrode, interconnect electrode, and conductive regions of the substrate are doped with the same impurity at the same time, and A process that prescribes the sequence of steps in which a structure is formed. In order to adapt to these various purposes, conventional processes
A fairly large contact cut is used in the S/D area intended for the formation of the IGFET. The pattern of cuts, shown as outline 6 in FIG. 2, is made in a conventional manner using a photoresist mask and a hydrofluoric (HF) acid wet etch to remove the exposed silicon dioxide. The duration of the oxide etch process is determined to expose areas 7 of the substrate surface without over-etching the fairly thick field oxide 3. usually,
The HF acid etchant used to remove the gate oxide region does not attack the surface 7 of the substrate 2 very strongly. The problems with conventional processes manifest themselves in the next steps of the manufacturing process, namely the deposition or attachment of the poly layer and the definition or definition.

The depiction in FIG. 3 represents the poly layer after it has been deposited and patterned using conventional photolithographic techniques. Area 1 as a whole
Edge 8a of gate electrode poly layer 8 designated as 1
Note the gap between and the edge 9a of the S/D interconnect poly layer 9. It is clear that if there is any overlap between the two, the gate and S/D will be shorted after poly doping. Typical dimensions of the gap separating these two are in the range of 4 microns. Similarly, region 1 between edge 4a and edge 9a of gate oxide 4
Note the exposure of the substrate surface 7 at 1. The typical separation between edges 4a and 9a is about 1 micron, a value that is highly dependent on the precision of the processing equipment.

Exposure of substrate 7 in region 11
can be done intentionally in conventional processes. Fourth
The figure illustrates the result if poly layer 9 is allowed to overlap gate oxide layer 4 in region 11.
The exposed gate oxide, ie, gate oxide 4 not covered by a poly layer such as 8 or 9, is removed, typically by etching with HF acid.
This is to expose the substrate surface for the next doping process. However, some of the gate oxide remains covered by the poly layer, such as section 12 in FIG. 4, for example. Unfortunately, when the poly layer and exposed substrate are doped, the gate oxide section 12 will act as a dopant barrier. The dopant impurity, coded as “X”, is located in region 13.
does not penetrate into the gate oxide section 12 of the doped
This prevents the formation of a conductive path between the contact region 14 and the doped S/D region 16. FIG. 4 illustrates the problem in an n-channel IGFET environment. Doped regions 14 and 16, which are diffusely doped at different depths, are created by the poly layer 9 penetrating the dopants.

Figure 5 shows the main IGFETs in the conventional process.
Figure 2 illustrates the structure of a junction between an S/D region and a poly interconnect. That is, the structure of FIG. 3 is subjected to an oxide etch and doping of the exposed poly and substrate. Doping is either by ion implantation or by a diffusion process.

As previously mentioned, conventional processes attempt to avoid overlap of the interconnect poly and gate oxide by ensuring a 1 micron separation in region 11. However, treatment of the exposed substrate surface itself will compromise the performance of the IGFET during fabrication.
This is primarily due to the undesirable effects of the carbon tetrachloride gas plasma etchant used to remove poly during patterning of areas such as 8 and 9. This etching material is also an effective etching material for the single crystal silicon of the substrate 2. Thus, while avoiding the problems illustrated in FIG. 4, the degree of etching of the surface 7 of the substrate 2 changes during removal of unwanted poly during electrode and interconnect definition. The depressions or cracks in the surface 7 caused by such etching have an adverse effect on process control with respect to layer depth tolerances, endpoint detection accuracy and overetching requirements.

The effects of damage to the substrate surface mainly appear later as a deterioration in the electrical performance of the IGFET. Typical degradation includes excessive leakage current, premature breakdown, and unreliable loss of reproducibility of other juncture characteristics. With data storage characteristics based on inherent capacitance characteristics and the trend toward higher impedance, IGFETs with lower leakage current tolerances are desired.

The process described above can also be extended to include structures with multiple poly layers. For example, forming or depositing another dielectric layer over the structure of FIG. 3, depositing a second poly layer, defining and etching the second poly layer, and then depositing a gate oxide layer. Through each step of removing all exposed dielectric, including both Poly 4 and other dielectric layers, the resulting structure is one with multiple poly layers. The doping, metallization and surface passivation steps are then followed in the customary manner. Neither the single poly layer nor the multi-poly layer versions of conventional processes are designed to reduce damage caused to the surface of the substrate.

Having provided a basic understanding of the conventional process used to manufacture IGFETs and their interconnects, we will now explain the differences made by the present invention from the starting structure depicted in Figure 1, and then follow the new process. The unique characteristics of the IGFET formed using this method will be explained based on typical application examples. This embodiment is used to fabricate an n-channel IGFET with a single poly layer used to form both the gate electrode and the S/D interconnect electrode. Other dopants and dielectric materials can be used. Similarly, we believe that application to multi-poly layer structures will be readily apparent to those skilled in the art based on the foregoing description.

To understand the differences or features of the present invention, let us begin with the LOCOS-shaped structure depicted in FIG. 1 and consider the various processes applied thereto. Conventional processes include two initial ion implantation steps that do not alter the shape of the IGFET or contacts. The first acts to regulate the threshold level of the IGFET, and the second
Determine whether the IGFET should be in enhancement mode or depletion mode. Typically, the first implant implants boron ions with a dose of 4.3×10 ¹¹ cm ⁻² over the entire wafer at an energy of about 40 keV. Following this global implant, masking all but the channel region of the IGFET device that will later be operated in depletion mode, an energy of approximately 140 keV and 1.3
Implant phosphorus ions with a dose in the range of ×10 ¹² cm ^-2 . According to conventional processes, the active areas of the enhancement mode device are completely masked with photoresist during this depletion implant. The implant into the gate region of the depletion IGFET is large enough to overcome the boron doping effects discussed above.

In significant contrast to conventional processes, the process disclosed herein is performed immediately prior to the latter described depletion implant step. In the present invention, instead of completely masking, enhancement mode
Only selected areas of the S/D region of the IGFET are exposed and implanted with phosphorus ions. The area exposed to the implant for enhancement mode device formation should extend beyond the area where the poly interconnect and substrate are to be bonded, but not into the area that will later constitute the IGFET-specific portion. will not be extended. For an n-channel enhancement mode IGFET, the area exposed through the ion implantation mask is indicated by dotted line 1 in Figure 6.
It is represented by 7. A light depletion doped with n-type phosphorus ions is represented by dot 18. The active area of a depletion mode device adjusts its exposure to meet its threshold voltage requirements.

While in the prior art the contact cuts through the oxide layer 4 of FIG. 2 were considered to expose a larger substrate surface area 7 than the contact area for bonding poly interconnects to the substrate surface, the practice of the present invention The contact cut according to the example is quite small. The masking and HF acid etch steps remove the substrate surface area 19 so that the area remaining covered by the poly interconnect 21 is sufficiently small after the poly is patterned.
It is done only in Looking at Figure 8, at this point,
It is helpful to refer to the plan view of the layout depicted in FIG. Note in FIG. 10 that this embodiment defines an even smaller contact cut area within the poly interconnect area which is smaller than the implant area. This implantation results in a residual silicon dioxide layer 4
This becomes even clearer when one considers that the etching agent used to remove the etchant does not attack single crystal silicon.

The structure illustrated in FIG. 8 is deposited or deposited, masked, and etched to form a single poly layer that forms the interconnect and gate electrode patterns. The interconnect poly 21 in the area of contacts 22 completely overlaps the gate oxide 4 and a carbon tetrachloride gas plasma etch used to remove the poly is applied to the substrate 2.
surface 19. Therefore, no surface damage occurs. Although it is possible to leave poly outside the region where the phosphorus ions 18 were implanted, in order to ensure maximum effective channel width, it is recommended that almost all of the interconnect poly 21 in the active area be within the implanted region. is preferred. Referring again to FIG.

As with conventional processes, any exposed or exposed oxide is removed by an HF acid etch.
A phosphorous n-type dopant is then diffused into the exposed poly and substrate. The results are shown in FIG.

It is also evident from the structure of FIG. 9 that the diffused S/D region of the IGFET is physically separated from the poly interconnect electrode. However, in this case the two are coupled through an electrically conductive parasitic depletion channel, generally designated 23. The phosphorus dopant does not diffuse through the oxide layer 24 again;
There is no difference from the basic sequence of the conventional process. Channel 2 with timely injection early in the process
An electrically conductive connection is achieved through 3. Parasitic channels and other depletion
Since the mode IGFETs were implanted at the same time, the channel has typical -3V threshold characteristics depending on the typical impurity dose.

FIG. 11 is a schematic diagram showing an equivalent circuit of the structure shown in FIG. 9. Node 26 corresponds to the poly interconnect electrode of FIG. parasitic depletion
IGFET 27 represents parasitic channel 23 of FIG. Node 29 is the main node designated by reference number 28.
Represents the S/D electrode of IGFET. Node 30 corresponds to the poly gate electrode of FIG. node 31
The other S/ for IGFET28 represented by
The D electrode preferably constitutes a diffusion region of the substrate.
At this point, everyone will undoubtedly recognize that 27 parasitic IGFETs are also formed on the 31 side in this process. This type of versatility gives the IC designer a great deal of free hand in prescribing circuit layout and device performance.

Recognizing that some parasitic depletion channels are limited in their current carrying capacity, it is worth considering at least their implications for circuit structure. Although generally acceptable at low currents, the use of interconnect poly that couples through parasitic channels
It is particularly compatible with the load characteristics of the IGFET gate electrode.

With this in mind, consider the flip-flop circuit schematically illustrated in FIG. The various electrical nodes of the circuit are also marked with symbols D and P to indicate conductive paths that are diffused or perhaps implanted into the substrate itself, and poly conductive paths, respectively. Typically, the power supply voltage V and the ground potential are connected via similarly doped conductive paths in the substrate. Preferably, resistors 32, 33 are formed from segments of selectively doped poly, with a doping range significantly less than the dose of the interconnect poly.

The main IGFETs 34 and 36 are surrounded by dotted lines 37 and 3
8 with an accompanying parasitic depletion IGFET. For example, the main IGFET3
The four diffused S/D electrodes are electrically coupled to another set of interconnect poly electrodes through parasitic IGFETs 41,42. Those interconnecting polyelectrodes themselves are the main
Connect to the gate electrode of IGFET 36 and resistor 32. Note the general compatibility of bonding at both the poly and diffused electrode levels. The flip-flop circuit configuration described herein, under favorable operating conditions, can benefit from the contacts forming process described herein without sacrificing circuit or process complexity. is undoubtedly clear.

Preferably, the use of a parasitic depletion IGFET to couple the interconnect poly electrode to the S/D region is limited to small current loads, but this limitation is not as severe as one might first think. The current carrying capacity of the channel can be increased depending on the concentration of implanted phosphorus ions. However, it should be noted that the preferred process effectively creates parasitic channels with large width-to-length ratios. Projection 39 in Figure 10
The channel, denoted by , includes three consecutive sides for coupling the contact cut region to the S/D region. Therefore, the contact cut area is mostly surrounded by the S/D area. This high width to length ratio provides large current carrying capacity. The channel shapes shown here are merely illustrative, so there is no doubt that contact areas as well as implant areas
It can be seen that the cut and S/D regions can be reshaped to create channels of useful electrical properties.

Among the variations contemplated for the embodiments described herein are processes that differ in material and dopant form. Moreover, as anyone can appreciate, the structure illustrated here is
It is also adaptable for uses other than connections between S/D electrodes of IGFETs. For example, S/D in Figure 9
Doped regions described as electrodes can serve equally well as conductive paths in the substrate layer.

Other embodiments in addition to those contemplated include:
The process described above can also be extended to processes in which a second dielectric layer separating the first poly layer from a second poly layer is formed after patterning the first poly layer. The second dielectric layer acts as a barrier during etching of the second poly layer pattern. As with the single poly layer process, the exposed dielectric is removed before the multiple poly layers and substrate are co-doped. In another type of implementation of this embodiment, the second dielectric layer is a composite layer of stacked materials such as silicon dioxide and silicon nitride. The purification of this process step is carried out using the MNOS equipment on a common wafer.
It can also be introduced into a manufacturing sequence compatible with the formation of both IGFET and IGFET.

[Brief explanation of the drawing]

Figures 1-5 schematically illustrate the key steps of a conventional process used to fabricate contacts between a poly layer and a diffusion region of a substrate.
A perspective view of the IGFET device taken at right angles is shown. FIGS. 6-9 contain a series of similar right-angled perspective views that schematically illustrate an approach to making contacts in accordance with one embodiment of the present invention. FIG. 10 schematically illustrates the relative pattern of the contact cut areas when viewed from above. FIG. 11 shows a completed polycontact structure with poly contacts made by the method disclosed herein.
Represents an equivalent circuit diagram of an IGFET. FIG. 12 is a circuit diagram schematically depicting the flip-flop structure of the IGFET of FIG. 11.

Claims (1)

[Claims] 1. A dielectric layer 4 is formed on the entire surface of an active region formed on a semiconductor substrate 2, and a first region (S/D region) in which an enhancement type FET is formed in the active region; defining a second region 17 adjacent thereto, doping the second region 17 with an n-type impurity dopant, and removing a portion of the dielectric layer 4 in the second region 17; By this, the contact cut region 19 is exposed on the surface of the semiconductor substrate 2, and an inter-channel interconnection layer 21 that completely covers the contact cut region 19 and a gate electrode portion of the enhancement type FET are formed. A polycrystalline silicon layer 21 that can be doped in a region
etching away the dielectric layer 4 without exposing the contact cut region 19; and doping the etched region of the dielectric layer 4 with an n-type dopant that is the same as the impurity dopant. forming a depletion type FET under the inter-channel interconnect layer 21 and diffusing the inter-channel interconnect layer 21 and the first region (S/D); A method of forming electrical contacts between regions of a semiconductor substrate that connects them with constant electrical conductivity.