JPH0583278A - Data transmission system - Google Patents

Abstract

PURPOSE:To execute a data transmission at a high speed without having a complicated constitution, in the data transmission system which is constituted of plural computers, and executes the data transmission between the computers concerned. CONSTITUTION:Between output terminals 1A-4A and input terminals 1B-4B of data of ECUs 1-4, an AND gate 13 constituted so as to be closed in the case its ECU executes a data transmission, and so as to be opened in other case is placed, respectively, and also, to the each input terminal, a receiving register 12 is connected, respectively. For instance, in the case the ECU 1 executes the data transmission, the data concerned passes through the AND gate 13 of each ECU, whenever one bit is outputted and goes round the system concerned, returns to the original ECU 1 (received by the receiving register 12 of a first ECU 1), and also, the data concerned is received by each receiving register 12 of the ECU 2-ECU 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly to a data transmission system capable of transmitting data from one computer to another computer with a simple structure and at high speed. Is.

[0002]

2. Description of the Related Art In automobiles, motorcycles and the like (hereinafter simply referred to as "vehicles" and the like), an electronic control unit (hereinafter referred to as ECU) having a built-in microcomputer controls engine ignition timing, fuel injection control, automatic shift control. , Driving force control, braking control, suspension control, air conditioning control, self-diagnosis function, etc. are performed. When performing a plurality of controls in this way, the processing capacity of one microcomputer decreases, so that a microcomputer is used for each control target.

By the way, since the plurality of microcomputers often use common vehicle data such as engine speed, vehicle speed, and temperature, data communication is performed between the microcomputers in such a case, and If shared, the load on each microcomputer is reduced.

Regarding data communication, a LAN method in a general communication field is well known. However, if the LAN system is directly applied to an in-vehicle data transmission system, the system may be a large scale. ..

On the other hand, a vehicle data transmission system which does not use the LAN method is disclosed in, for example, Japanese Patent Laid-Open No. 62-2572.
39 publication. In this system, an input / output interface having a shift register is connected to each of a plurality of electronic control units, and the shift registers are connected in series to form a loop-shaped transmission path. Data is sequentially transmitted in the transmission path by outputting the data bit by bit.

[0006]

In the data transmission system described in the above publication, when data is to be transmitted to a loop-shaped transmission line in the system, the shift register that constitutes the transmission line is provided with the data. Data is output bit by bit. Then, the output data is shifted bit by bit in synchronization with the synchronization signal for data transmission. In other words, in this system, the data transmitted from a certain microcomputer is temporarily stored in the register and then transmitted to the next microcomputer. Therefore, the data length to be transmitted is transmitted to the next microcomputer. There will be a delay.

Therefore, as the number of microcomputers connected increases, the degree of data delay increases, and the number of microcomputers that can be connected is limited when high-speed processing is desired by engine control or the like.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a complicated structure in a data transmission system that is composed of a plurality of computers and performs data transmission between the computers. An object of the present invention is to provide a data transmission system that can perform high-speed data transmission without having it.

[0009]

In order to solve the above-mentioned problems, in the present invention, the data is closed between the data input terminal and the data output terminal of each computer when the computer transmits data. A gate means configured to be otherwise opened and connecting at least one input terminal of each computer to an output terminal of another computer, and further to its output terminal I was connected to the input terminal of the computer.

According to a second aspect of the present invention, the data transmission system is formed in an annular shape by connecting the input terminals and the output terminals of all the computers of the system to the output terminals and the input terminals of the adjacent computers.

According to a third aspect of the present invention, a check bit area is provided in data transmitted from each computer, and at least one of the computers receives data transmitted from another computer through the gate and the output terminal. Check bit control means for inverting the check bit of the data, determining means for determining whether the data received through the input terminal is data output from the computer, and the received data Check bit inversion detection means for detecting the presence or absence of inversion of the check bit in the data when the data is output from the computer, and the transmitted data if the inversion of the bit is not performed properly. And a data retransmitting means for retransmitting the data.

According to a fourth aspect of the present invention, the check bit control means is configured to invert the bit in the check bit area only when the data transmitted from another computer is the data addressed to the computer. ,
Further, the data retransmitting means retransmits the transmitted data when the computer as the data transmission destination does not invert the bit in the check bit area.

In the present invention, the data re-transmission is not performed more than a predetermined number of times.

According to a sixth aspect of the present invention, when the computers are connected in a loop, a data length area is provided in the data to be transmitted, and at least one of the computers is provided with another computer. Data adding means for adding predetermined data to the transmission data,
A means for rewriting and transmitting the data length in the transmission data from the other computer is provided.

According to a seventh aspect of the present invention, in the system of the sixth aspect, at least one of the computers determines whether the data output from the computer is multiplexed by another computer. ,
When data is multiplexed, the data transmitted by the computer is deleted and the data length is rewritten,
A transmission means for transmitting them is provided.

[0016]

In the data transmission system according to the first aspect of the present invention, the transmitted data is received by a computer other than the computer that transmits the data, and the data is transmitted to other computers in real time.

In the data transmission system according to the second aspect, since the systems are connected in a ring, when data is sent from one computer, the data is
It cycles through the data transmission system bit by bit and returns to the computer.

In the data transmission system according to the third and fourth aspects, if the computer that has passed or received the data does not invert the check bit, the data is retransmitted by the computer that has transmitted the data.

In the data transmission system according to the fifth aspect of the present invention, since the data retransmission is not performed a predetermined number of times or more, the data processing delay of the data transmission side computer is prevented.

In the data transmission system according to the sixth aspect, other data is added to the data being circulated in the system. That is, the data is multiplexed.

In the data transmission system according to the seventh aspect, when the data is multiplexed, when the multiplexed data returns to the computer that sent the original data, the computer transmits the multiplexed data to the computer. The data output by is deleted and transmitted again.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 2 is a schematic block diagram of the first embodiment of the present invention. In the figure, the first electronic control unit (hereinafter referred to as "EC
U ”. The first to fourth ECUs 4 each include a microcomputer, and perform a predetermined calculation using various connected sensors or various data calculated by another ECU to control various connected actuators.

The first ECU 1 to the fourth ECU 4 have output terminals 1A to 4A and input terminals 1B to 1B, respectively.
The input terminal 4B is provided, and the output terminal and the input terminal which are respectively adjacent to each other are connected by using the line 5, so that they are connected in an annular shape. When each ECU performs data transmission, the data is transmitted from the output terminals, and as a result, the data is transmitted in the arrow direction in the figure.

FIG. 1 is a diagram showing the configuration of FIG. 2 with a simple function. In the figure, the same reference numerals as those in FIG. 2 represent the same or equivalent parts. The first ECU 1 to the fourth ECU 4 have the same configuration.

The operation of the first embodiment of the present invention will be briefly described below with reference to FIG. First, each of the first ECU1
When transmitting data, the fourth ECU 4 generates a frame having a predetermined number of bits as shown in FIG. 4 and transmits the frame. Then, the first ECU 1 to the fourth ECU 4 respectively transmit the transmission register 11 that stores the frames to be transmitted,
And a reception register 12 for accumulating the received frames. Then, each of the first ECU 1 to the fourth ECU 4
During frame transmission (data transmission mode), the second input terminal 13B of the AND gate 13 becomes "L", and the AND gate 13 is closed. When frame transmission is not performed (data reception / passage mode), the second input terminal 13B is closed. The input terminal 13B becomes "H" and the AND gate 13 opens.

Here, for example, the second ECU2 to the fourth ECU
4 is in the data receiving / passing mode, the first EC
When U1 enters the data transmission mode for transmitting a frame to another ECU (second ECU2 to fourth ECU4), the frame generated by the frame generation means 15 is
After being temporarily stored in the transmission register 11, the OR gate 14
And to the input terminal 2B of the adjacent second ECU 2 via the output terminal 1A. Even if a frame is output from the transmission register 11, it is assumed that the output frame remains in the transmission register 11.

Since the AND gate 13 of the second ECU 2 is open, the frame sent from the first ECU 1 passes through the AND gate 13 and the OR gate 14 and is transferred from the output terminal 2A to the third ECU 3. Further, the frame input to the input terminal 2B is transferred to the reception register 12, vehicle data is extracted from the frame as needed, transferred to the data processing means 16, and used for predetermined arithmetic processing.

The frame of the first ECU 1 transferred from the second ECU 2 to the third ECU 3 is similar to the fourth ECU.
4 is transferred. Then, from the fourth ECU 4 to the first EC
It is transferred to U1. Also in the 3ECU3 and the 4ECU4, the input frame is taken into each receiving register 12, vehicle data is extracted as needed, and then transferred to the data processing means 16.

Since the first ECU 1 is in the data transmission mode,
The AND gate 13 is closed. Therefore, the frame that has gone through the system once and returned is the reception register 1
2 is only input into the second ECU 2, and is not output to the second ECU 2 again. Then, the first ECU 1 determines whether or not the frame received by the reception register 12 is the frame transmitted by the own station. In the case of the frame of its own station, if the first ECU 1 does not continuously transmit other frames thereafter, the first ECU 1 enters the data receiving / passing mode.

The ECU in the data receiving / passing mode
(2ECU2-4ECU4 in the above example), if necessary, invert the bit at a predetermined position of the data to pass,
Indicates that the ECU has been passed. In this case, the ECU that has transmitted the data (the first ECU 1) determines that the data transmission was not normally performed and transmits the frame again unless the bit is inverted.

Further, the bit inversion may be performed only by the ECU that actually takes in the data in the frame, and the ECU that simply passes may not perform the bit inversion.

By the way, a plurality of ECUs (for example, the first EC
U1 and 3ECU3) simultaneously transmit data, AND gate 1 of 1ECU1 and 3ECU3
Since 3 is closed, the frame output from the first ECU 1 only stops in the reception register 12 of the third ECU 3 via the second ECU 2, and is not transmitted to the fourth ECU 4. Similarly, the data output from the third ECU 3 is also the fourth
It is only received by the reception register 12 of the first ECU 1 via the ECU 4, and is not transmitted to the second ECU 2.

Here, the first ECU 1 and the third ECU 3
Detects the contents of the reception register 12 and, if the frame in the reception register 12 is transmitted from another ECU, extracts vehicle data from the frame as necessary to extract data from the frame. 16 and then transfers the frame in the reception register 12 to the transmission register 11,
The frame is transferred to the adjacent ECU. This allows
Even when a plurality of ECUs transmit a frame at the same time, the data is transmitted accurately without collision.

Now, FIG. 3 shows an example of a concrete configuration of the first ECU 1. In the figure, the same reference numerals as those in FIG. 1 represent the same or equivalent portions. The figure also shows an example in which data is transmitted and received using an optical fiber.

First, the first ECU 1 has a CPU 21 and a RAM.
It includes a microcomputer including 22, a ROM 23, an input / output interface 24, and a common bus 25. Then, the transmission register 11 is connected to the common bus 25.
And the reception register 12 are connected.

In this example, the light receiving element 26 is the first
The input terminal 1B of the CU1 and the line 5 (see FIGS. 1 and 2).
The optical data emitted from the adjacent ECU is received via (refer to). The output of the light receiving element 26 is compared with the potential of a predetermined level in the comparator 27, and when it exceeds the level, it is recognized as "H" data, and the comparator 27 produces an output. This output is the first input terminal 13 of the AND gate 13.
It is input to A, and the reception register 12 and the CPU 2
It is also input to 1. The CPU 21 includes a second input terminal 13B of the AND gate 13 and the OR gate 14.
Is also connected to.

The serial output terminal of the transmission register 11 is
It is connected to the input terminal of the OR gate 14 and the serial input terminal of the transmission register 11. This OR gate 1
The output line 4 is connected to the switching element 28, and by the ON / OFF operation of the switching element 28,
The light emitting element 29 which is the output terminal 1A of the first ECU 1 is controlled.

The sensors 201 and 202 are connected to the input / output interface 24. The actuators 401 and 402 are also connected to the input / output interface 24 via the drivers 301 and 302.

The transmission register 11 and the reception register 1
2 of the function and a part of the function of the RAM 22 to the CPU 21
May be realized by. In addition, AND gate 1
The functions of 3 and the OR gate 14 may be realized by the CPU 21. That is, reference numeral 21 surrounded by a broken line
The part indicated by A, and further the reference numeral 2 surrounded by a two-dot chain line
The function of the portion indicated by 1B may be realized by the CPU.

FIG. 4 is a diagram showing an example of a data structure of a frame which is transmission data of each ECU. In this example, 1
The frame is divided into 5 blocks. First, the first block located at the head of the
This command indicates whether to "transmit" vehicle data such as engine speed, vehicle speed, intake air amount, or "request" transmission of such vehicle data to a predetermined ECU (see FIG. 5).

The second block is the ECU for transmitting the frame.
The ECU number indicating the transmission side ECU, and the third block indicates the reception side ECU that is the ECU in which the frame should be received (the ECU that actually fetches and uses the in-frame data as well as simply passing through the frame). The ECU number.

In the fourth block, if the first block is a "request" command, the engine speed, vehicle speed,
A data code corresponding to vehicle data such as the intake air amount is arranged, and when the first block is a "transmit" command, the data code and the vehicle data corresponding to the data code are arranged. An example of this data code and vehicle data is shown in FIG.

Bits corresponding to the number of ECUs constituting the data transmission system are assigned to the fifth block, and each bit corresponds to each ECU. Then, when a frame is transmitted from a predetermined ECU, the ECU through which the frame has passed (that is, the E that transmitted the frame)
(ECU other than CU) inverts the bit corresponding to the ECU. When the transmitted frame circulates and returns, the ECU that has transmitted the frame confirms the inversion of the bit and determines whether or not another ECU has normally received the frame. The frame in FIG. 4 has a fixed bit length in this example.

FIG. 12 shows a frame structure (A in the figure) accumulated in the transmission register 11 of the first ECU 1 when the frame is transmitted from the first ECU 1, and the frame circulates in the data transmission system. Frame structure when it is received by the receiving register 12 (FIG. 9B)
Indicates. The command is a “request” command, and the frame transmission destination is the third ECU 3.

Next, the operation of the first embodiment of the present invention will be described in detail. Each ECU has two modes, a data transmission mode and a data reception / passage mode, as described above. Then, in the data transmission mode, another ECU
A state (command is “request”) requesting transmission of vehicle data such as engine speed, vehicle speed, intake air amount to
There are two states, that is, a state in which the frame is transmitted to another ECU (a command is “transmission”) after receiving the “request” command or by the intention of the ECU.

FIG. 7 is a flow chart showing an example of the processing when the first ECU 1 is in the data transmission mode, FIG. 8 is a flow chart showing an example of the processing when the first ECU 1 is in the data receiving / passing mode, and FIGS. 9 and 10. FIG. 3 is a functional block diagram of a first ECU 1 according to the first embodiment of the present invention. The operation of FIGS. 7 and 8 will be described with reference to FIGS. 9 and 10. The functions and operations of the second ECU 2 to the fourth ECU 4 are the same as those of the first ECU 1.

First, in FIG. 7, in step S1, a frame is created by the frame creating means 15 (FIG. 9). This frame creation is created using the vehicle data created by the vehicle data creation means 41.
This vehicle data is generated using the output data of the sensors 201, 202 ... Or the data output from the data processing means 16.

Succeedingly, in a step S2, it is determined whether or not the transmission line (line 5) of the data transmission system is in use. When the frame shown in FIG. 4 is transmitted (step S5, which will be described later), a start bit (synchronization pulse) is transmitted prior to the transmission, but one frame transmission time (scheduled time) from the start bit reception. ), The line 5 can be determined to be in the "open" state when the signalless state continues. Specifically, when the start bit is received by the start bit detecting means 42, the timer 43 is started. When the timer 43 determines that the scheduled time has elapsed, the timer 43 produces an output and the line 5 The "open" state is determined. According to this determination, the start bit detection means 42 is reset and the frame generation means 15 is in a frame output ready state.

When it is determined that all the ECUs are in the data receiving / passing mode and the line is in the "open" state, in step S3, the frame generating means 15
An output command of "L" is issued from the gate control means 45, whereby the gate control means 45 causes the second input terminal 1 to operate.
Outputs "L" to 3B. That is, the AND gate 13 is closed.

In step S4, the count value N of the counter 49 is reset to 0, and then in step S5, the frame generated by the frame generation means 15 is transferred to the transmission register 11 and the transmission register 11 is transferred.
From the other E through the OR gate 14 and the output terminal 1A.
A frame is transmitted to the CU. The transmission is
It is sequentially performed bit by bit by a clock pulse or a pulse corresponding to the pulse. The same applies when retransmitting received data, which will be described later. At the time of this frame transmission, the other ECU is in the data reception / passage mode and its AND gate 13 is open. Therefore, for each 1-bit transmission of the frame, the bit circulates in the data transmission system and is stored in the reception register 12. Be received. Therefore, at the same time when the transmission of the frame ends, the reception of the frame into the reception register 12 also ends. In FIG. 11, the first ECU 1
ECU1 to 4EC when the vehicle outputs a frame
An example of the output signal of U4 is shown.

Prior to the frame transfer from the frame generation means 15 to the transmission register 11, if necessary, the reset signal generation means 46 is used to reset the contents of the transmission register 11. Further, since the serial data output terminal and the serial data input terminal of the transmission register 11 are connected, even if a frame is transmitted from the transmission register 11, the frame is not lost.

In step S6, the transmitting ECUN
o. The second block of the frame received by the reception register 12 by the detection means 47 is the local station (the first ECU 1).
The ECU number is determined. If the second block is the ECU number of the own station, it can be determined that the received frame is the frame sent from the ECU. In this case, the check bit inversion detection means 48 is activated, and step S7 is performed. Move to.

In step S7, the check bit inversion detection means 48 determines whether or not the bits of the area other than the own station in the fifth block of the received frame are inverted. If the bits of the stations other than the own station are inverted, it can be determined that the transmitted frame has normally passed through another ECU. In this case, the process ends. After that, the data reception / passage mode
The process proceeds to step S21 in FIG. 8 and the check bit inversion detection means 48 sends “H” to the gate control means 45.
Is output, and the AND gate 13 is opened.

If the determination in step S7 is negative, that is, if the check bits of all the other ECUs are not inverted, the counter 49 is energized to set the count value N of the counter 49 to 1 in step S8. Is added, and in step S9, the comparison unit 50 determines whether or not the count value N of the counter 49 exceeds the number of repetitions (for example, 3) set in the number-of-repetitions storage unit 51. If the number of repetitions has not been exceeded, the process returns to step S5 and, if necessary, after detecting the "open" of the line 5, the transmission register 11 is re-energized to transmit the frame.

If the number of repetitions has been exceeded, the routine proceeds to step S10, where the abnormal signal output means 52 is energized to generate an abnormal signal, after which the processing ends and proceeds to step S21 in FIG. To do. The abnormality signal is used by the first ECU 1 or by being transferred to another ECU to perform a predetermined abnormality processing.

Now, when all the ECUs are in the data receiving / passing mode, it is conceivable that a plurality of ECUs transmit frames at substantially the same time. Since the AND gate 13 of each ECU that transmits a frame is closed, for example, when the first ECU 1 and the third ECU 3 simultaneously transmit a frame, as described above, the first ECU 1
The frame transmitted by is received by the reception register 12 of the third ECU 3.
Is not received, and is not transmitted to the fourth ECU 4 and thereafter. Similarly, the frame transmitted by the third ECU 3 is the first E
It is received by the receiving register 12 of the CU1 and the second E
It is not transmitted after CU2. In other words, the reception register 12 of each of the first ECU 1 and the third ECU 3 does not receive the transmission frame of its own station, and the third ECU of the other station does not receive the transmission frame.
3 and the transmission frames of the first ECU 1 are received. In such a case, that is, the transmission side ECU No. detection means 47
However, if it is determined that the content of the second block is the ECU number of another ECU (in this example, an ECU other than the first ECU 1), the reception side ECU No. detection means 53 is activated, and the processing is started from step S6. Control goes to step S11.

In step S11, the receiving ECU
The No. detection means 53 determines whether or not the third block of the received frame is the ECU number of its own station (the first ECU 1). If the third block is the ECU number of your station,
After step S12, the process proceeds to step S13. If it is the ECU number of another station, the process directly proceeds to step S13.

In step S12, the data code and vehicle data stored in the fourth block of the frame stored in the reception register 12 are stored in the memory 54 (FIG. 3).
RAM 22) of the above. This data is appropriately used for the calculation executed by the data processing means 16.

In step S13, the first EC of the fifth block of the frame stored in the reception register 12
Invert the check bit of U1, and then step S
At 14, the contents of the reception register 12 are transferred to the transmission register 11. Then, the process is step S
Return to 5. Specifically, when the content (frame) of the reception register 12 is transferred to the transmission register 11 by the data transfer means 56, by the operation of the check bit control means 55 urged by the reception side ECU No. detection means 53,
The check bit of the first ECU 1 in the fifth block is inverted.

Before the frame transfer from the reception register 12 to the transmission register 11, the reset signal generating means 46 is activated as necessary to reset the transmission register 11.

In this way, the transmission frame of the third ECU 3 received by the reception register 12 is the transmission register 1
1 is transmitted to the OR gate 14 from the transmission register 11.
And to the second ECU 2 via the output terminal 1A.
As a result, this frame is returned to the transmission source, the third ECU 3. The same processing is performed in the third ECU 3 as well, so the reception register 12 of the first ECU 1
Also, finally, the frame output from the first ECU 1 is received.

Next, referring to FIG. 8, first, step S21.
Then, the first input terminal 13A of the AND gate 13 is "H".
It is said that. In FIG. 9 and FIG. 10, this operation is performed when the check bit inversion detection means 48 detects inversion, or when the abnormal signal output means 52 outputs an abnormal signal. Then, the AND gate 13 is opened by this, and the frame input from the input terminal 1B is
It is received by the second ECU 2 and is output from the output terminal 1A to the second ECU 2 via the OR gate 14.

In step S22, it is determined whether the start bit is detected by the start bit detecting means 42. When the start bit is detected, it is determined in step S23 whether or not one frame has been completely received by the reception register 12 and the passage of the first ECU 1 has been completed.

When the frame is passing through the first ECU 1, the first ECU 1 inverts the check bit corresponding to the first ECU 1 in the fifth block of the passing frame. This inversion is performed by the check bit control means 44 when the start bit detection means 42 detects the start bit in the data receiving / passing mode.
It is done by energizing. Specifically, the check bit control means 44 controls the gate control means 45 at the timing when the check bit passes through the AND gate 13 to set the second input terminal 13B to "L" and close the AND gate 13. This is done by sending the inverted bit of the check bit to the OR gate 14. The check bit control means 44 sets the second input terminal 13B to "H" again after passing the check bit.

When the completion of reception / passage of one frame is confirmed in step S23, the reception side ECU No. detection means 57 determines in step S24 that the third block of the reception frame is the ECU number of its own station (the first ECU 1). Is determined. If it is not the ECU number of the own station, the process returns to step S22, and if it is the ECU number of the own station, the reception side ECU No. detection means 57 activates the command detection means 58, and proceeds to step S25.

In step S25, whether the first block of the frame received by the reception register 12 by the command detection means 58 is a "transmission" command,
Alternatively, it is determined whether the command is a "request" command. If it is a "send" command, in step S26, FIG.
Similar to step S12 of the
The contents of the block (data code and vehicle data) are stored in the memory 54. This data is data processing means 1
6 is used as appropriate for the calculation executed by the above-mentioned 6. Then, the process returns to step S22.

When the command detecting means 58 detects the "request" command, the processing shifts to step S1 in FIG. That is, the frame generation means 15 is activated,
The necessary vehicle data is received from the vehicle data generation means 41, a predetermined frame is created, transferred to the transmission register 11, and output from the transmission register 11. When the first block is the "request" command, the data code of the requested vehicle data is set in the fourth block of the frame, so the frame generation means 15 is used.
Then, the vehicle data corresponding to the data code is received from the vehicle data generation means 41 to create a frame.

The third block of the frame (see FIG. 4) can be omitted. That is, if the data code (fourth block) of the frame received by the reception register 12 is constantly monitored, the vehicle data corresponding to the data code can be received or the vehicle data can be transmitted as necessary. It is possible. In this case, a data code detecting means is provided in place of the receiving ECU No. detecting means 53.

The check bit in the fifth block does not necessarily have to be inverted. That is, the fifth block can be omitted. Further, the check bit may be inverted only in the transmission destination ECU of the frame (that is, in the reception side ECU to be arranged in the third block).

Further, in the above description, the frame has been described as having a fixed bit length, but the fourth block or the like may be variable length data. In this case, data indicating the bit length of the frame or the fourth block may be added to an appropriate position of the frame.

Further, the respective ECUs constituting the data transmission system have been described as being connected in a ring by the line 5, but if the check bit inversion confirmation is not performed, they may not be connected in a ring. good. That is, for example, in the system of FIG. 2, one of the lines 5 connecting each ECU can be omitted.

In the above embodiment, when a frame is transmitted from one ECU, in principle, the other ECUs cannot transmit the frame until the transmission of the frame is completed. In the second embodiment of the present invention described below, when one frame passes through another ECU, other data is added by the other ECU to multiplex the data without waiting for the end of one frame transmission. Both enable other data transmission. In this embodiment, each EC
U is connected in a ring shape.

An example of a frame adopted in this embodiment is shown in FIG. In the figure, the frame is
It is composed of a command, a data length, a data code (or a data code and vehicle data), an ECU number for transmitting the frame, and a parity check unit. The data length is the total number of bits of the subsequent data code (or data code and vehicle data) and the transmission ECU number of the frame, and the parity check unit is a parity bit arrangement area.

Now, for example, as shown in FIG.
It is assumed that the first ECU 1 sends out the frame (the command is “transmission”) of FIG. 13A when four ECUs 1 to 4ECU 4 are annularly connected. After the frame transmission from the first ECU 1 is started,
FIG. 14 shows the operation when the second ECU 2 desires to transmit a frame (command is “transmission”) from its own station.

The second ECU 2 is in the data receiving / passing mode, the AND gate 13 is opened, and the received data is directly output from the output terminal 2A and received by the receiving register 12. The process of FIG. 14 is performed by interruption during the process of step S23 of FIG. 8, for example, and the process is executed in real time for each 1-bit reception.

First, in step S31, it is determined whether or not it is the reception timing of the data length. When the reception timing of the data length is reached, the second input terminal 13B of the AND gate 13 is set to "L" in step S32, and the AND gate 13 is closed. Then, in step S33, the data length is corrected by the second ECU 2 and transmitted from the output terminal 1A. The received data length is the first EC
Data code transmitted by U1 (or data code and vehicle data) and transmission side ECU number (and in FIG. 13)
The data length after correction is the second
The data length (data code and vehicle data) to be transmitted from the ECU 2 and the data length of the transmission side ECU number (and in FIG. 13) are added.

When the corrected data length is transmitted and the reception timing of the data code (or data code and vehicle data) is reached, the second input terminal 13B of the AND gate 13 is set to "H" in step S34. The gate 13 is opened, and in step S35, the first EC
It is determined whether or not the data and transmitted from U1 have passed. After these passages, step S36
And the AND gate 13 is closed again at step S37.
In, the second ECU 2 transmits the data and the data to be transmitted. As a result, the data is multiplexed.

Subsequently, in step S38, the parity check unit transmitted from the first ECU 1 and the parity check unit to be transmitted by the second ECU 2 are transmitted. Then, the process ends, and the process returns to step S21 of FIG. 8, for example. The frame thus transmitted from the second ECU 2 is as shown in FIG. 13 (B).

Next, the first ECU 1 will be shown in FIG.
Although a frame like this is returned, the following processing is executed by detecting the difference in data length. That is,
The data transmitted from the own station (first ECU 1) and the parity check unit output from the own station are deleted from the frame of FIG. 7B, and the remaining data is transferred.
At this time, the data length is rewritten. In this way, the first E
A frame as shown in FIG. 13C is transmitted from CU1.

It should be noted that such a data multiplexing function does not have to be provided in all the computers in the data transmission system, but may be provided only in a computer having a high priority.

Further, in FIG. 13B, it is shown that the data and the data to be added are arranged after the data and, but the data and the data to be added may be arranged before the data and, that is, immediately after the data length. Is also good.

Further, although the commands of the first ECU 1 and the second ECU 2 are both the same "transmission", data multiplexing is possible even when the commands are different.

It should be understood that the structure of each frame shown in each of the above embodiments is not limited to that shown in FIG. 4 or FIG. 13 (A). Modifications of the frame can be easily created by those skilled in the art.

Next, a third embodiment of the present invention will be described. In the data transmission system as described above, when the data transmitted from one ECU passes through another ECU, the width of the pulse forming the data becomes wider or narrower than the pulse width at the time of data transmission. It may happen.

If the pulse width becomes shorter each time it passes through the ECU, there is a possibility that the pulse may be erroneously discriminated or the worst pulse may disappear on the way. On the contrary, if the pulse width becomes longer as it passes through the ECU, there is a possibility that the pulse may be erroneously discriminated or the worst pulse may be connected to the adjacent pulse.
Then, such a tendency becomes serious when the number of ECUs forming the data transmission system is large.

The third embodiment of the present invention eliminates such a problem. FIG. 15 is a diagram showing the configuration of the third exemplary embodiment of the present invention with a simple function, and is a diagram similar to FIG. In the figure, the same reference numerals as those in FIG. 1 represent the same or equivalent portions, and thus the description thereof will be omitted.

In FIG. 15, each of the first ECU 1 to the fourth ECU 4E
A pulse width correcting means 17 is connected to the CU 4 between the output terminal of the AND gate 13 and the input terminal of the OR gate 14. This pulse width correcting means 17 is the ECU
Is in the data reception / transmission mode, the pulse width of the pulse input via the AND gate 13 is corrected by one pulse by a method described later and output to the adjacent ECU via the OR gate 14.

FIG. 16 is a block diagram showing a specific structure of the first ECU 1 in the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 3 represent the same or equivalent portions, and thus the description thereof will be omitted. As is clear from the comparison with FIG. 3, when the AND gate 13 is open, the data output from the AND gate 13 is
The data is once taken into the CPU 21, subjected to pulse width correction processing, and then outputted to the OR gate 14.

FIG. 17 shows the first EC of the third embodiment of the present invention.
It is a part of the functional block diagram of U1 and is combined with FIG. 9 to form the entire functional block diagram. In the figure, the same reference numerals as those in FIG. 10 represent the same or equivalent portions. The configuration of FIG. 17 is similar to that of FIGS.
The description is omitted because it is clear from the description of 5.

Now, the specific pulse width correction method will be described below. Note that the following description is a correction method by the second ECU 2 when the first ECU 1 transmits the data and the second ECU 2 receives the data and passes the data.

First, a coping method when the pulse width becomes short will be described. FIG. 18 is a flow chart showing an example of the pulse width correction operation of the third embodiment of the present invention, and FIG. 19 is a diagram showing how the pulse width is changed by the processing of FIG. The processing of FIG. 18 replaces the processing of steps S22 and S23 of FIG.

First, in FIG. 19, when a pulse (transmission pulse) transmitted from the first ECU 1 is received by the second ECU 2, the pulse width is shortened by ΔX1 as shown in FIGS. Suppose In this case, the pulse width is corrected by the second ECU 2 (that is, extended by ΔX1), and the transmission pulse width of the second ECU 2 is the same as the transmission pulse of the first ECU 1 as shown in FIG. Width.

In FIG. 18, first, in step S41, it is determined whether or not the input signal becomes "1" (that is, "H"). If it is "1", "1" is output via the OR gate 14 in step S42.

In step S43, it is determined whether or not the input signal has become "0" (that is, "L").
If "0", it is determined in step S44 whether or not ΔX1 has elapsed since the input signal became "0". Then, after ΔX1 has elapsed, in step S45,
“0” is output via the OR gate 14.

Thereafter, in step S46, it is determined whether or not the reception of the data for one frame is completed. If not completed, the process returns to step S41, and if completed, the process proceeds to step S24.

Although not shown in the processing of FIG. 18, the input signal is also fetched in the reception register 12.
Then, the captured data is sent to the relevant EC as necessary.
Used for various U processing.

FIG. 20 is a functional block diagram of the processing shown in FIG. In the figure, first, an input signal is input to the set input terminal S of the flip-flop 71. Therefore, when the input signal becomes "1", "1" is output from the output terminal Q thereof. The input signal is the inverter 7
It is also input to the pulse generating means 73 via 2. Therefore, when the input signal changes from "1" to "0", the pulse generating means 73 is energized to generate a pulse, which starts the timer 74A. This timer 74A
Measures ΔX1 and resets the timer 74A and the flip-flop 71 after the measurement. As a result, the output signal of the flip-flop 71 becomes "0".

In this configuration, when the reception data is narrow, the pulse width is corrected to the initial width regardless of whether the transmission data is the RZ system or the NRZ system.

A pulse generating means for directly resetting the output of the inverter 72 in the flip-flop 71 and generating a pulse or the like by ΔX1 after the reset may be provided.
Further, instead of using the method of FIG. 18 described above, the method of FIG. 21 described later may be used.

Next, a coping method when the pulse width becomes long will be described. In this case, the pulse transmission method is RZ
The coping method differs depending on whether it is the system or the NRZ system. In the case of the RZ method, since the width of the "1" pulse is known in advance, the first pulse width can be reproduced by generating a pulse having a constant width in synchronization with the detection of the rising edge of the pulse.

FIG. 21 is a flow chart showing another example of the pulse width correction operation of the third embodiment of the present invention, and FIG. 22 is FIG.
FIG. 6 is a diagram showing how the pulse width is changed by the process of 1. The process of FIG. 21 replaces the processes of steps S22 and S23 of FIG. 8 similarly to the process of FIG.

First, in FIG. 22, it is assumed that the reception pulse (B) of the second ECU 2 becomes longer by ΔX2 than the transmission pulse (A) of the first ECU 1. In this case, the pulse width is corrected by the second ECU 2 (that is, the pulse width is cut by ΔX2), and the transmission pulse width of the second ECU 2 is changed to the 1E as shown in FIG.
It has the same width as the transmission pulse of CU1.

In FIG. 21, first, when it is confirmed in step S51 that the input pulse is "1", "1" is output and transmitted in step S52. Step S
At 53, it is determined whether the time X has elapsed since the input pulse became "1". When the passage of time X is detected, "0" is output in step S54. Then, in step S55, it is determined whether or not the reception of the data for one frame is completed. If not completed, the process returns to step S51, and if completed, the process proceeds to step S24.

In the process of FIG. 21, the input signal is also fetched by the reception register 12, and the data is used for various processes of the ECU as needed.

FIG. 23 is a functional block diagram of the processing shown in FIG. In the figure, the same reference numerals as those in FIG.
Represents the same or equivalent part. In the figure, first, an input signal is input to the set input terminal S of the flip-flop 71. Therefore, when the input signal becomes "1", "1" is output from the output terminal Q thereof. The Q output is also input to the pulse generating means 73. Therefore,
When the Q output changes from "0" to "1", the timer 74
B is activated. This timer 74B measures the time X,
After the measurement, the timer 74B and the flip-flop 71 are reset. As a result, the flip-flop 71
Output signal of "0" becomes "0".

In this configuration, when the transmission data is the RZ system, the pulse width of the reception data is corrected to the initial width even if the reception data has a narrow width.

Next, in the case where the pulse transmission method is the NRZ method, when the input signal of "1" is continuously input, the pulse width varies depending on the number of consecutive "1". It is impossible to reproduce the pulse width by the method shown in FIG. Therefore, in this case, for example, the processing shown in FIG.

FIG. 24 is a flow chart showing still another example of the pulse width correcting operation of the third embodiment of the present invention, FIG.
FIG. 25 is a diagram showing how the pulse width is changed by the processing of FIG. 24. The process of FIG. 24 replaces the process of steps S22 and S23 of FIG. 8 similarly to the process of FIGS. 18 and 21. In the NRZ method, the delay of the falling edge of the pulse is constant regardless of the continuous length of "1" bits.

First, in FIG. 25, it is assumed that the fall of the reception pulse (B) of the second ECU 2 is delayed by ΔX3 as compared with the transmission pulse (A) of the first ECU 1. In this case, the pulse width is corrected by the second ECU 2,
The transmission pulse width of the second ECU 2 has the same width as the transmission pulse width of the first ECU 1, as shown in FIG.

In FIG. 24, first, in step S61, it is determined whether or not a synchronization pulse (start pulse) has been input. At the beginning of one frame, a sync pulse irrelevant to the content of the frame data is arranged. FIG.
20 to 20 and FIGS. 21 to 23,
A sync pulse is arranged at the beginning of each frame.
When the sync pulse is detected, "1" is output in step S62.

In step S63, it is determined whether or not the falling edge of the sync pulse is detected. When the falling edge is detected, it is determined in step S64 whether or not the time α has further elapsed from the falling edge. α
When the progress of is detected, a timing signal is generated in step S65 and "0" is output in step S66. The timing signal is output by the microcomputer of the ECU that executes the process at each elapse of a predetermined time X from the occurrence. Further, the predetermined time X is the duration of each pulse constituting each frame.

In step S67, it is determined whether or not a timing signal has been generated (step S67 corresponds to step S67).
If it is performed immediately after the process of 66, it is determined whether or not the timing signal next to the timing signal generated in step S65 has occurred. When the timing signal is generated, the input signal is read in step S68. Then, in step S69, it is determined whether the input signal is "1" or "0", and if the input signal is "1", the input signal is "1" in step S70 and the input signal is "0". If so, "0" is output in step S71.

In step S72, after the sync pulse is detected, the number of bits constituting one frame (N bits)
Is detected. 1 in this example
The number of bits that make up the frame is a preset fixed value. If N bits have not been detected, the process returns to step S67, and if N bits have been detected, the process proceeds to step S24. That is, the process of step S72 is a process of determining whether the detection of one frame is completed.

In this example, the pulse width of the sync pulse is longer than the initial pulse width, but the predetermined time X is maintained between the sync pulse and the data pulse following the sync pulse (reference numeral D in FIG. 25). No reference is made to the identification of the data pulse.

FIG. 26 is a functional block diagram of the processing shown in FIG. In the figure, the same reference numerals as those in FIGS. 20 and 23 represent the same or equivalent portions. FIG. 26
First, the input signal is input to the set input terminal S of the flip-flop 71 via the switching means 75. Since the initial state of the switching means 75 is the closed state, the Q output of the flip-flop 71 becomes "1" at the same time when the synchronizing pulse is input, and the signal is the OR gate 7.
It is output via 6.

The sync pulse is also input to the inverter 72. As a result, the timer 74C is started when the sync pulse disappears, and the timer 74C starts measuring the predetermined time α. The timing signal generating means 77 is activated after the elapse of the predetermined time α and generates a timing signal at every predetermined time X. This timing signal generating means 77
The first timing signal is generated, the flip-flop 71 is reset, the output of the OR gate 76 becomes "0" (that is, the synchronizing pulse disappears), the switching means 75 opens, and the flip-flop of the input signal after that is opened. The input to block 71 is cut off.

The switching means 78 is opened for a very short time each time the timing signal is output, and the input signal is taken into the pulse generating means 79. The pulse generating means 79 is
When the input signal is "1", it is "1" only during the time X
Which is output through the OR gate 76.
The pulse generation by the pulse generating means 79 is stopped after receiving a predetermined number of bits of data, that is, after receiving one frame of data.

Although the pulse width correction shown in FIGS. 18 to 26 is explained as being executed by the second ECU 2,
All other ECUs may be provided with the function, or may be provided only with a preselected ECU among the ECUs forming the data transmission system.

Of the pulse width corrections described above, FIG.
20 to 23 and the embodiments shown in FIGS. 21 to 23, the pulse width is controlled by matching the rising and falling edges of the pulse with the transmission pulse, and FIGS. In the embodiment shown in FIG. 26, the pulse width is controlled by controlling the rising and falling timings of the pulse. In addition to such pulse width control, each ECU has the function of adjusting the pulse height.
Alternatively, a so-called 3 is added to a selected predetermined ECU.
R correction may be performed.

Now, FIGS. 1, 3, 10, 15 to 1
The AND gate 13 shown in FIG. 7 may be, for example, switching means whose opening and closing is controlled by a control signal to be input to the second input terminal 13B of the AND gate 13. Further, the OR gate 14 may be any one as long as it prevents the backflow of data to the output terminals 1A to 4A.

Further, although the above-mentioned embodiment is applied to a vehicle control device, for example, as shown in FIG.
It may be used in a system such as entertainment installed in a vehicle, or in a field such as home electronics. In FIG. 27, reference numeral 501 is a controller and monitor, and reference numerals 502 to 506 are a navigator, an air conditioner, a CD player, a radio (tuner and amplifier), and an optical fiber, respectively.

Furthermore, it goes without saying that the present invention is applicable not only to optical communication but also to communication systems using electric signals.

[0123]

According to the data transmission system of the first aspect, the transmitted data is received in real time by a computer other than the computer that transmitted the data. That is, each time 1-bit data is transmitted, the data reaches the computer at the final end of the system, so that it is possible to perform data transmission at extremely high speed (that is, without delay in transmission) without having a complicated configuration. .. As a result, even if a large number of computers are connected and data is transmitted between these computers, there is no delay in data processing.

(2) According to the data transmission system of the second aspect, since the systems are connected in a ring,
When data is sent from the computer, the data circulates through the system bit by bit and returns to the computer. That is, data can be transmitted at extremely high speed from any computer in the system.

(3) According to the data transmission system of claims 3 and 4, when the computer that has passed or received the data does not invert the check bit, the data is retransmitted by the computer that has transmitted the data. That is, when an abnormality occurs in a computer that receives or passes data, or when noise is superimposed on the data to be transmitted, the data is retransmitted. This improves the reliability of the data transmission system.

(4) According to the data transmission system of the fifth aspect, since the data retransmission is not performed a predetermined number of times or more, the data processing delay of the data transmission side computer can be prevented.

(5) According to the data transmission system of the sixth aspect, the data can be multiplexed with respect to the data being circulated in the system. Generally, when data transmission is started, a start bit is transmitted after a predetermined time has passed since there is no data passing through a line (transmission path), and then data transmission is possible only after that.
In the data transmission system of the sixth aspect, data can be transmitted without waiting for the predetermined time and the start bit transmission time to elapse. Therefore, speeding up of data transmission by the data transmission system is further improved.

(6) According to the data transmission system of claim 7, when the data is multiplexed, the individual data included in the multiplexed data is regenerated every time the data transmission system makes one round. It is deleted by the computer that transmitted the data. That is, even if the data is multiplexed,
The individual data included in the multiplexed data disappears after one round of the system. Therefore, the waiting time for the transmission is the shortest for the computer that transmits the data by detecting the "open" state of the transmission path.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of FIG. 2 with a simple function.

FIG. 2 is a schematic block diagram of a first embodiment of the present invention.

FIG. 3 is a first ECU 1 according to the first embodiment of the present invention.
3 is a block diagram showing a specific configuration of FIG.

FIG. 4 is an ECU applied to a first embodiment of the present invention.
It is a figure which shows the data structure of the frame which is the transmission data of this.

FIG. 5 is a chart showing the contents of commands.

FIG. 6 is a chart showing an example of a data code and vehicle data.

FIG. 7 is a flowchart showing a process when the first ECU 1 is in a data transmission mode according to the first embodiment of the present invention.

FIG. 8 is a flowchart showing a process when the first ECU 1 is in a data reception / passage mode according to the first embodiment of the present invention.

FIG. 9 is a part of a functional block diagram of the first ECU 1 according to the first embodiment of the present invention, and is combined with FIG. 10 to form the entire functional block diagram.

FIG. 10 is a part of a functional block diagram of the first ECU 1 according to the first embodiment of the present invention, and is combined with FIG. 9 to form the entire functional block diagram.

FIG. 11 is a diagram showing an example of output signals of the first to fourth ECUs 1 to 4 when the first ECU 1 outputs a frame.

FIG. 12 shows the first EC in the first embodiment of the present invention.
A frame structure stored in the transmission register 11 of the first ECU 1 when a frame is transmitted from U1 (A in the figure),
2 is a diagram showing a frame structure (B in the same figure) when the frame is circulated in the data transmission system and received by a reception register 12 of the first ECU 1.

FIG. 13 shows a frame structure (A in the same figure) applied to the second embodiment of the present invention, and a frame structure (B in the same figure) when other data is multiplexed in the frame and changes thereof. It is a figure (the same figure C) which shows.

FIG. 14 is a flowchart showing a method of data multiplexing in the second exemplary embodiment of the present invention.

FIG. 15 is a diagram showing the configuration of the third exemplary embodiment of the present invention with a simple function.

FIG. 16 is a first ECU according to a third embodiment of the present invention.
It is a block diagram which shows the concrete structure of 1.

FIG. 17 is a part of a functional block diagram of the first ECU 1 according to the third embodiment of the present invention, and is combined with FIG. 9 to form the entire functional block diagram.

FIG. 18 is a flowchart showing an example of a pulse width correction operation according to the third embodiment of the present invention.

19 is a diagram showing how the pulse width is changed by the processing of FIG.

FIG. 20 is a functional block diagram of the processing shown in FIG.

FIG. 21 is a flow chart showing another example of the pulse width correction operation of the third embodiment of the present invention.

22 is a diagram showing how the pulse width is changed by the processing of FIG.

FIG. 23 is a functional block diagram of the processing shown in FIG. 21.

FIG. 24 is a flowchart showing still another example of the pulse width correction operation according to the third embodiment of the present invention.

FIG. 25 is a diagram showing how the pulse width is changed by the processing of FIG. 24.

FIG. 26 is a functional block diagram of the processing shown in FIG. 24.

FIG. 27 is a block diagram showing an example of an entertainment system.

[Explanation of symbols]

1 to 4 ... First to fourth ECUs, 1A to 4A ... Output terminals, 1
B to 4B ... Input terminal, 5 ... Line, 11 ... Transmission register, 12 ... Reception register, 13 ... AND gate, 14 ...
OR gate, 15 ... Frame generating means, 16 ... Data processing means, 21, 22A, 21B ... CPU, 22 ... RA
M, 44, 55 ... Check bit control means, 45 ... Gate control means, 47 ... Transmission side ECU No. detection means, 48 ...
Check bit inversion detection means, 49 ... Counter, 50 ...
Comparator, 51 ... Repeat count memory, 53, 57 ...
Receiving side ECU No. detecting means, 54 ... Memory, 56 ... Data transferring means, 58 ... Command detecting means

Claims (7)

[Claims] 1. A data transmission system comprising a plurality of computers for transmitting data between the computers, wherein each computer is connected to a data input terminal and an output terminal and the output terminal, and is connected to another computer. Data transmission means for transmitting data to the computer, data reception means connected to the input terminal for receiving data transmitted from another computer, and connected between the input terminal and the output terminal, the computer Gate means configured to be closed for transmission and opened for other data reception and data transmission, wherein at least one of the computers has an input terminal other than that. Connected to the output of a computer, and that output is connected to the input of another computer. A data transmission system characterized in that 2. The system according to claim 1, wherein each of the computers is connected to an adjacent computer so that the input terminal and the output terminal are connected to each other so that the system is formed in an annular shape. Data transmission system. 3. The transmitted data comprises a check bit area, wherein at least one of the respective computers transmits data transmitted from another computer through the gate means and the output terminal. Check bit control means for inverting the bit in the check bit area of the data as necessary, and determination for determining whether the data received by the data receiving means is data output from the computer. A check bit inversion detection means for detecting the presence or absence of inversion of a bit in a check bit area in the data when the data received by the data receiving means is data output from the computer; If the bit inversion is not properly performed, the data already transmitted using the data transmission means is used. Data transmission system according to claim 2, characterized by further comprising a data retransmission means for transmitting again. 4. The check bit control means inverts the bit in the check bit area only when the data transmitted from another computer is the data addressed to the computer, and the data re-transmission means comprises 4. The data transmission system according to claim 3, wherein the transmitted data is transmitted again when the computer, which is the transmission destination of the, does not invert the bits in the check bit area. 5. The data transmission system according to claim 3, wherein the data retransmitting unit is configured not to retransmit the data more than a predetermined number of times. 6. The data to be transmitted comprises a data length area, and at least one of the computers includes data adding means for adding predetermined data to data transmitted from another computer, A means for rewriting and transmitting the data length in transmission data from another computer, wherein new data is multiplexed with the transmission data from the other computer. The data transmission system according to any one of 2 to 5. 7. At least one of the computers includes a determination unit that determines whether or not the data received by the data receiving unit is data output from the computer, and the data receiving unit. When the data received by the computer is the data output from the computer, the multiplexing detection means for detecting whether the data is multiplexed, and the data reception when the data is multiplexed 7. The transmission means for deleting the data output from the computer from the data received by the means, rewriting the data length in the received data, and transmitting them. Data transmission system.