JPH0583164A - Reception circuit for transmission signal - Google Patents

Reception circuit for transmission signal

Info

Publication number
JPH0583164A
JPH0583164A JP24538091A JP24538091A JPH0583164A JP H0583164 A JPH0583164 A JP H0583164A JP 24538091 A JP24538091 A JP 24538091A JP 24538091 A JP24538091 A JP 24538091A JP H0583164 A JPH0583164 A JP H0583164A
Authority
JP
Japan
Prior art keywords
signal
circuits
circuit
equalizer
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24538091A
Other languages
Japanese (ja)
Inventor
Yoshihiro Hori
好弘 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24538091A priority Critical patent/JPH0583164A/en
Publication of JPH0583164A publication Critical patent/JPH0583164A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To improve the signal transmission quality by implementing optimum amplitude equalization. CONSTITUTION:Pre-filters 2, 10 in a digital line circuit 1 and a terminal equipment 9 connected by a transmission line eliminate a noise component from a received transmission signal (setting equalization characteristic) and outputs the result as a 1st signal. Automatic gain control circuits 3, 11 output information representing a gain to make the amplitude of the 1st signal constant and a 2nd signal whose amplitude is made constant. Equalizer circuits 4, 12 equalize a frequency characteristic of the 2nd signal according to a setting signal (a) and outputs the result as a 3rd signal. Waveform comparator circuits 6, 14 calculate a difference between the 3rd signal and a reference value at which a data error to be identified by data identification circuits 5, 13 is minimized and outputs the result as difference information. Equalizer control circuits 7, 15 output the setting signal (a) according to the gain information and the difference information.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は伝送信号の受信回路に関
し、特にデジタルライン回路及び端末間で伝送する伝送
信号の受信回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission signal receiving circuit, and more particularly to a transmission signal receiving circuit for transmitting between a digital line circuit and terminals.

【0002】[0002]

【従来の技術】従来の伝送信号の受信回路は、図2に示
すようにデジタルライン回路1aの端末9aは、受信の
伝送信号からノイズ成分を除去するプリフイルタ回路
2,10と、プリフイルタ回路2,10が出力する信号
の振幅を一定にする自動利得制御回路3,11と、自動
利得制御回路3,11が出力する信号の周波数特性の補
正を行うイコライザ回路4,12と、イコライザ回路
4,12が出力する信号のデータを識別するデータ識別
回路5,13と、出力回路8,16とを有しており、イ
コライザ回路4,12は予め設定された数種類の等化特
性のうち、自動利得制御回路3,11の利得に対応した
等化特性を選択していた。
2. Description of the Related Art In a conventional transmission signal receiving circuit, as shown in FIG. 2, a terminal 9a of a digital line circuit 1a includes a pre-filter circuit 2 and a pre-filter circuit 2 for removing noise components from a received transmission signal. The automatic gain control circuits 3 and 11 that make the amplitude of the signal output from the signal 10 constant, the equalizer circuits 4 and 12 that correct the frequency characteristics of the signal output from the automatic gain control circuits 3 and 11, and the equalizer circuits 4 and 12 Has data identification circuits 5 and 13 for identifying the data of the signal output by the output circuit 8 and output circuits 8 and 16. The equalizer circuits 4 and 12 have automatic gain control among several preset equalization characteristics. The equalization characteristic corresponding to the gain of the circuits 3 and 11 was selected.

【0003】[0003]

【発明が解決しようとする課題】従来の伝送信号の受信
回路において、イコライザ回路の特性が予め設定された
数種類の等化特性の中から自動利得制御回路の利得に対
応して等化特性を選択しているため、予め用意されてい
る等化特性が伝送路の周波数特性を補正できない場合に
は伝送信号の品質が劣化するという問題点があった。
In the conventional receiving circuit for a transmission signal, the equalizer characteristic is selected according to the gain of the automatic gain control circuit from among several preset equalizer characteristics of the equalizer circuit. Therefore, there is a problem that the quality of the transmission signal is deteriorated when the equalization characteristic prepared in advance cannot correct the frequency characteristic of the transmission line.

【0004】[0004]

【課題を解決するための手段】本発明の伝送信号の受信
回路は、受信の伝送信号から雑音成分を除去し第1の信
号として出力するフィルタと、前記第1の信号の振幅を
一定にする利得の情報と一定の振幅にされた第2の信号
とが出力される自動利得制御回路と、設定信号に従って
前記第2の信号の周波数特性を等化し第3の信号として
出力するイコライザ回路と、前記第3の信号のデータを
識別するデータ識別回路と、前記識別するデータの誤り
が最小になる基準値と前記第3の信号との差分を計算し
差分情報として出力する波形比較回路と、前記利得の情
報と前記差分情報とに従って前記設定信号を出力するイ
コライザ制御回路とを有する。
A transmission signal receiving circuit according to the present invention has a filter for removing a noise component from a reception transmission signal and outputting the first signal as a first signal, and a constant amplitude of the first signal. An automatic gain control circuit that outputs gain information and a second signal having a constant amplitude; an equalizer circuit that equalizes the frequency characteristic of the second signal according to a setting signal and outputs the equalized third signal; A data discriminating circuit for discriminating the data of the third signal; a waveform comparing circuit for calculating a difference between the third signal and a reference value that minimizes an error in the discriminating data; And an equalizer control circuit that outputs the setting signal according to gain information and the difference information.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例のブロック図、図3は本実
施例の等化特性を設定する伝送信号のフォーマット図で
ある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 3 is a format diagram of a transmission signal for setting the equalization characteristic of the present embodiment.

【0006】伝送路で接続されるデジタルライン回路1
及び端末9において、プリフィルタ2,10は図3に示
す受信の伝送信号(等化特性を設定する)から雑音成分
を除去し第1の信号として出力する。自動利得制御回路
3,11は第1の信号の振幅を一定にする利得の情報
と、一定の振幅にされた第2の信号とを出力する。イコ
ライザ回路4,12は設定信号aに従って第2の信号の
周波数特性を等化し第3の信号として出力する。波形比
較回路6,14はデータ識別回路5,13が識別するデ
ータの誤りが最小になる基準値と第3の信号との差分を
計算し差分情報として出力する。イコライザ制御回路
7,15は利得の情報と差分情報とに従って設定信号a
を出力する。
Digital line circuit 1 connected by a transmission line
Further, in the terminal 9, the pre-filters 2 and 10 remove noise components from the reception transmission signal (which sets the equalization characteristic) shown in FIG. 3 and output it as the first signal. The automatic gain control circuits 3 and 11 output gain information for making the amplitude of the first signal constant and a second signal having a constant amplitude. The equalizer circuits 4 and 12 equalize the frequency characteristic of the second signal according to the setting signal a and output it as a third signal. The waveform comparison circuits 6 and 14 calculate the difference between the third signal and the reference value that minimizes the error of the data identified by the data identification circuits 5 and 13, and outputs it as difference information. The equalizer control circuits 7 and 15 set the setting signal a according to the gain information and the difference information.
Is output.

【0007】次に本実施例の動作について説明する。デ
ジタルライン回路1及び端末9は、電源投入あるいはリ
セットがなされるとデジタルライン回路1及び端末9の
各回路に対して初期設定をおこなう。次いで、デジタル
ライン回路1の出力回路8及び端末9の出力回路16は
図3に示す同期用のフラグと予め定められた一定パター
ンの伝送信号を出力する。デシジタルライン回路1及
び、端末9は、受信した信号に対しそれぞれプリフイル
タ2,10によりノイズ成分を除去し、自動利得制御回
路3,11により振幅を一定に補正し、自動利得制御回
路3,11により適当なイコライザ特定を選択したイコ
ライザ回路4,12により等化されデータ識別回路5,
13により受信信号の0.1が識別され同期用のフラグ
の検出により、デジタルライン回路1及び端末9の同期
が確立される。
Next, the operation of this embodiment will be described. The digital line circuit 1 and the terminal 9 perform initial setting for each circuit of the digital line circuit 1 and the terminal 9 when the power is turned on or reset. Next, the output circuit 8 of the digital line circuit 1 and the output circuit 16 of the terminal 9 output the flag for synchronization shown in FIG. 3 and the transmission signal of a predetermined fixed pattern. The digital line circuit 1 and the terminal 9 remove noise components from the received signals by the prefilters 2 and 10, respectively, and correct the amplitude to a constant level by the automatic gain control circuits 3 and 11, and then the automatic gain control circuits 3 and 11 are used. Data equalizer circuit 5, which is equalized by the equalizer circuits 4 and 12 in which an appropriate equalizer specification is selected by
13 identifies 0.1 of the received signal, and the detection of the synchronization flag establishes the synchronization between the digital line circuit 1 and the terminal 9.

【0008】次いでイコライザ回路4,12が出力する
受信信号の中で予め定められた一定パターンのデータと
データ識別回路5,13でデータと識別するに際し最も
データエラーが少くなる予め設定された基準値との差分
を波形比較回路6,14は計算し、計算値に従いイコラ
イザ制御回路7,15はイコライザ回路4,12のイコ
ライザ特性を制御し、データ識別をするに際し、最もデ
ータエラーが少くなるようにイコライザ特性を変更す
る。次いで、デジタルライン回路1,端末9は、通常の
データの送受信をおこなう。
Next, in the received signals output from the equalizer circuits 4 and 12, data of a predetermined fixed pattern and the data identification circuits 5 and 13 discriminate between the data and the preset reference value which minimizes the data error. The waveform comparison circuits 6 and 14 calculate the difference between and, and the equalizer control circuits 7 and 15 control the equalizer characteristics of the equalizer circuits 4 and 12 in accordance with the calculated values so that the data error is minimized when performing data identification. Change the equalizer characteristics. Next, the digital line circuit 1 and the terminal 9 perform normal data transmission / reception.

【0009】[0009]

【発明の効果】以上説明したように本発明は、受信回路
の振幅等化特性の設定を予め設定されたデータエラーが
最も少くなくなる基準値との比較により行うことによ
り、伝送路の種類、伝送路の接続方法等の伝送特性に依
らず、最適な振幅等化特性を設定できるので伝送品質の
向上が図れるという効果を有する。
As described above, according to the present invention, the amplitude equalization characteristic of the receiving circuit is set by comparing it with a preset reference value at which the data error is the smallest, so that the type of transmission line and the transmission The optimum amplitude equalization characteristic can be set regardless of the transmission characteristics such as the path connection method, so that the transmission quality can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来の伝送信号の受信回路の一例のブロック図
である。
FIG. 2 is a block diagram of an example of a conventional receiving circuit for a transmission signal.

【図3】本実施例の等化特性を設定する伝送信号のフォ
ーマット図である。
FIG. 3 is a format diagram of a transmission signal for setting the equalization characteristic of the present embodiment.

【符号の説明】[Explanation of symbols]

1 デジタルライン回路 2 プリフィルタ 3,11 自動利得制御回路 4,12 イコライザ回路 5,13 データ識別回路 6,14 波形比較回路 7,15 イコイザ制御回路 8,16 出力回路 9 端末 1 Digital Line Circuit 2 Pre-filter 3,11 Automatic Gain Control Circuit 4,12 Equalizer Circuit 5,13 Data Discrimination Circuit 6,14 Waveform Comparison Circuit 7,15 Equalizer Control Circuit 8,16 Output Circuit 9 Terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 受信の伝送信号から雑音成分を除去し第
1の信号として出力するフィルタと、前記第1の信号の
振幅を一定にする利得の情報と一定の振幅にされた第2
の信号とが出力される自動利得制御回路と、設定信号に
従って前記第2の信号の周波数特性を等化し第3の信号
として出力するイコライザ回路と、前記第3の信号のデ
ータを識別するデータ識別回路と、前記識別するデータ
の誤りが最小になる基準値と前記第3の信号との差分を
計算し差分情報として出力する波形比較回路と、前記利
得の情報と前記差分情報とに従って前記設定信号を出力
するイコライザ制御回路とを有することを特徴とする伝
送信号の受信回路。
1. A filter for removing a noise component from a received transmission signal and outputting the first signal as a first signal, gain information for keeping the amplitude of the first signal constant, and a second for making the amplitude constant.
, An equalizer circuit for equalizing the frequency characteristics of the second signal according to a setting signal and outputting the third signal, and a data identification for identifying the data of the third signal. A circuit, a waveform comparison circuit that calculates a difference between the third signal and a reference value that minimizes an error in the identifying data, and outputs the difference as difference information, and the setting signal according to the gain information and the difference information. And an equalizer control circuit for outputting the signal.
JP24538091A 1991-09-25 1991-09-25 Reception circuit for transmission signal Pending JPH0583164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24538091A JPH0583164A (en) 1991-09-25 1991-09-25 Reception circuit for transmission signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24538091A JPH0583164A (en) 1991-09-25 1991-09-25 Reception circuit for transmission signal

Publications (1)

Publication Number Publication Date
JPH0583164A true JPH0583164A (en) 1993-04-02

Family

ID=17132801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24538091A Pending JPH0583164A (en) 1991-09-25 1991-09-25 Reception circuit for transmission signal

Country Status (1)

Country Link
JP (1) JPH0583164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8860527B2 (en) 2011-01-28 2014-10-14 Hitachi, Ltd. Equalizer circuit and printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8860527B2 (en) 2011-01-28 2014-10-14 Hitachi, Ltd. Equalizer circuit and printed circuit board

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