JPH0583053A - Automatic gain control amplifier - Google Patents

Abstract

PURPOSE:To decrease locking stable time of an output amplitude by operating the amplifier at an amplification factor stored corresponding to an input signal when lots of kinds of signals with a known fixed amplitude are inputted and the input signal is switched. CONSTITUTION:A peak hold circuit 2 detects a peak voltage of an output So of an amplifier 1 to output a Vp. An operational amplifier 3 applies operational amplification to a difference between the Vp and a Vr to output a Vc. An A/D converter 5 converts the Vc into a digital signal, which is stored in a storage circuit 6 by using an address signal ADR and a write enable signal WE. The digital signal led out of the storage circuit 6 is converted into an analog signal by a D/A converter 7 and a gain control signal Vm is outputted. A system changeover circuit 8 selects either the Vc or the Vm by using a selection signal SEL to control a gain changeover circuit 4. The amplifier 1 amplifies an input signal Si with an amplification factor controlled by the gain changeover circuit 4 to output an output signal So.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to automatic gain control amplifiers.

[0002]

2. Description of the Related Art Automatic gain control amplifiers having a feedback loop are generally used to obtain a predetermined output amplitude signal for various unknown levels of input signals. FIG. 3 is a block diagram showing an example of a conventional automatic gain control amplifier, and FIG. 4 is a waveform diagram of an example of the input / output signals of FIG.

A conventional automatic gain control amplifier has an input signal S
The amplifier 1 that amplifies i at the amplification degree controlled by the gain switching circuit 4 and outputs the output signal So, and the peak voltage of the output signal So of the amplifier 1 are detected to detect the peak hold voltage Vp.
Of the output of the peak hold circuit 2, an operational amplifier 3 that amplifies the difference between the peak hold voltage Vp of the output of the peak hold circuit 2 and the reference voltage Vr and outputs a gain control voltage Vc, and an output of the operational amplifier 3. The gain switching circuit 4 controls the gain of the amplifier 1 by the gain control voltage Vc.

Next, the operation of this example will be described with reference to FIG. A peak hold circuit 2 for converting a peak voltage of a signal with a predetermined discharge time constant into a voltage detects a peak voltage of an output signal So of an amplifier 1 and outputs a peak hold voltage Vp. The operational amplifier 3 arithmetically amplifies the difference between the peak hold voltage Vp of the output of the peak hold circuit 2 and the reference voltage Vr set to obtain a predetermined output amplitude of the output amplitude of the output signal So of the amplifier 1, and the reference voltage Vr.
It outputs the gain control voltage Vc added to. Gain switching circuit 4
Controls the gain of the amplifier 1 by the gain control voltage Vc of the output of the operational amplifier 3. The amplifier 1 amplifies the input signal Si with an amplification degree controlled by the gain switching circuit 4 and outputs a signal So.

When the peak hold voltage Vp is higher than the reference voltage Vr, the gain switching circuit 4 outputs the gain control voltage Vc which is the difference between the peak hold voltage Vp and the reference voltage Vr, and which is subtracted from the reference voltage Vr. The amplification degree of the amplifier 1 to be controlled is reduced to converge the output amplitude of the output signal So of the amplifier 1 to the output amplitude set by the reference voltage Vr. When the peak hold voltage Vp is lower than the reference voltage Vr, the gain control voltage Vc added to the reference voltage Vr is output by amplifying the difference between the peak hold voltage Vp and the reference voltage Vr, and the gain switching circuit 4 controls the gain. The amplification degree of 1 is increased to converge the output amplitude of the output signal So of the amplifier 1 to the output amplitude set by the reference voltage Vr. When the input signal Si has no amplitude, the output signal So of the amplifier 1 has no amplitude regardless of the amplification degree controlled by the gain switching circuit 4. The peak hold circuit 2 detects the peak voltage of the output signal So having no amplitude and outputs the peak hold voltage Vp of 0V. The operational amplifier circuit 3 performs operational amplification of the difference between the peak hold voltage Vp of 0 V and the reference voltage Vr and outputs the gain control voltage Vc added to the reference voltage Vr. Here, since the peak hold voltage Vp is 0V, the gain control voltage Vc outputs the maximum voltage. With the maximum voltage gain control voltage Vc, the gain switching circuit 4 maximizes the amplification degree of the amplifier 1. That is, if the input signal Si has no amplitude, the output signal So also has no amplitude, and the amplification degree controlled by the gain switching circuit 4 becomes maximum.

Then, when the input signal Si suddenly changes in amplitude from no amplitude, the gain of the gain switching circuit 4 changes from the maximum amplification state to the peak hold circuit 2, the operational amplifier circuit 3, and the gain switching circuit 4 of the feedback loop. It changes with a delay of the response time of. Particularly, the peak hold circuit 2 voltageizes the line connecting the peak voltage of the signal with a constant discharge time constant, and the change of the signal changes the peak hold circuit 2
Since the output signal So is equal to or larger than the discharge time constant of, the output signal So which is equal to or larger than the output amplitude set by the reference voltage Vr is gradually output from the amplifier 1 and gradually converges to the set output amplitude while drawing a gentle curve.

[0007]

Since this conventional automatic gain control amplifier uses the peak hold circuit and the operational amplifier in the feedback loop, the input signal is switched when various known fixed amplitudes are input. In this case, there is a drawback that it takes a long pull-in stabilization time, which is the time until the output amplitude signal stabilizes at a predetermined level.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic gain control amplifier with a memory which eliminates the above drawbacks and minimizes the pull-in settling time.

[0009]

An automatic gain control amplifier according to the present invention includes an amplifier for amplifying a signal according to an amplification degree designated by a gain switching circuit, and a peak hold circuit for detecting a peak voltage of an output signal of the amplifier. An automatic gain control amplifier comprising: an operational amplifier that performs operational amplification of a difference between an output voltage of the peak hold circuit and a reference voltage; and a gain switching circuit that controls the gain of the amplifier by the output of the operational amplifier. An analog / digital conversion circuit for converting an output signal into a digital signal, a storage circuit for storing a digital signal output from the analog / digital conversion circuit, and a digital / analog conversion for converting a digital signal from the storage circuit into an analog signal A circuit, an output of the operational amplifier, and an output of the digital-analog conversion circuit It switched and a system switching circuit for outputting to said gain switching circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of an automatic gain control amplifier of the present invention, and FIG. 2 is a waveform diagram of an example of input / output signals in FIG.

In this embodiment, the input signal Si is fed to the gain switching circuit 4
The amplifier 1 that amplifies the output signal So by the amplification degree controlled by, the peak hold circuit 2 that detects the peak voltage of the output signal So of the amplifier 1 and outputs the peak hold voltage Vp, and the peak hold circuit 2 An operational amplifier 3 that amplifies the difference between the peak hold voltage Vp of the output of V.sub.p and the reference voltage Vr and outputs the gain control voltage Vc to the system switching circuit 8 and the analog / digital conversion circuit (hereinafter referred to as A / D converter) 5. Gain control voltage Vc of the output of the operational amplifier 3
A / D converter 5 for converting the
A storage circuit 6 that stores the digital signal output from the / D converter 5, and a digital-analog conversion circuit that converts the digital signal from the storage circuit 6 into an analog signal and outputs the gain control voltage Vm to the system switching circuit 8 D / A converter) 7 and the gain control voltage V of the output of the operational amplifier 3
System switching circuit 8 for switching between c and the gain control voltage Vm of the output of the D / A converter 7 and outputting it to the gain switching circuit 4.
And a gain switching circuit 4 for controlling the gain of the amplifier 1 by the gain control voltage selected by the system switching circuit 8. That is, in this embodiment, the A / D converter 5, the storage circuit 6, the D / A converter 7 and the system switching are provided between the output of the operational amplifier 3 and the input of the gain switching circuit 4 in the conventional example shown in FIG. It is configured by adding a circuit 8.

Next, the operation of this embodiment will be described with reference to FIG. The peak hold circuit 2 detects the peak voltage of the output signal (hereinafter, So) of the amplifier 1 and outputs the peak hold voltage (hereinafter, Vp). The operational amplifier 3 arithmetically amplifies the difference between Vp and a reference voltage (hereinafter Vr) and adds the gain control voltage (hereinafter Vc) to Vr to the system switching circuit 8 and the A / D.
Output to the converter 5. The A / D converter 5 performs analog-digital conversion on Vc and outputs a digital signal to the storage circuit 6. The memory circuit 6 stores the digital signal output from the A / D converter 5 by an address signal (hereinafter ADR) and a write enable signal (hereinafter WE) corresponding to an externally controlled input signal. Also, the stored digital signal is extracted and output to the D / A converter 7. The D / A converter 7 digital-analog converts the digital signal output from the storage circuit 6 and outputs a gain control voltage (hereinafter Vm) to the system switching circuit 8. The system switching circuit 8 outputs either Vc or Vm to the gain switching circuit 4 by a selection signal (hereinafter, SEL) controlled from the outside. The gain switching circuit 4 is Vm selected by the system switching circuit 8.
Controls the gain of the amplifier 1. The amplifier 1 amplifies an input signal (hereinafter, Si) with an amplification degree controlled by the gain switching circuit 4 and outputs So.

The operation of storing the amplification degree corresponding to the input signal Si to be amplified in the memory circuit 6 is performed as follows. The system switching circuit 8 selects to output Vc to the gain switching circuit 4 by SEL. When Vp is higher than Vr, an amplifier 1 for controlling the gain switching circuit 4 by outputting Vc which is obtained by subtracting the voltage obtained by calculating and amplifying the difference between Vp and Vr from Vr.
To reduce the output amplitude of So of the output of amplifier 1 to V
It converges to the output amplitude set by r.

When Vp is lower than Vr, Vc obtained by adding the voltage obtained by arithmetically amplifying the difference between Vp and Vr to Vr is output to increase the amplification degree of the amplifier 1 controlled by the gain switching circuit 4 to increase the amplification degree of the amplifier 1. The output amplitude of the output So is converged to the output amplitude set by Vr.

When Si has no amplitude, S of the output of the amplifier 1
Similarly, o has no amplitude regardless of the amplification degree controlled by the gain switching circuit 4. The peak hold circuit 2 detects the peak voltage of the non-amplitude signal So and outputs Vp of 0V. The operational amplifier circuit 3 performs operational amplification of the difference between Vp of 0V and Vr and outputs Vc added to Vr. Where Vp is 0V
Therefore, Vc outputs the maximum voltage. The gain switching circuit 4 maximizes the amplification degree of the amplifier 1 by the maximum voltage Vc. That is, if Si has no amplitude, So also has no amplitude, and the amplification degree controlled by the gain switching circuit 4 becomes maximum.

Next, when Si has a sudden amplitude from no amplitude, the gain of the gain switching circuit 4 changes from the maximum amplification state to the response time of the peak hold circuit 2, the operational amplifier 3, and the gain switching circuit 4 of the feedback loop. It changes with a delay of. Particularly, the peak hold circuit 2 voltageizes the line connecting the peak voltage of the signal with a constant discharge time constant, and since the change of the signal is faster than the discharge time constant of the peak hold circuit 2, it exceeds the output amplitude set by Vr. So is gradually output from the amplifier 1 and converges to the set output amplitude while drawing a gentle curve.

At a predetermined time when the output So of the amplifier 1 is expected to have converged stably, the storage circuit 6 sets the ADR set for the Si being input at this time and the effective W.
The digital signal of the output of the A / D converter 5 is stored by E. That is, the gain control voltage for setting the amplification degree of the gain switching circuit 4 for controlling the gain of the amplifier 1 is stored in the storage circuit 6 as a digital signal. Similarly, addresses corresponding to various fixed amplitude input signals can be set and the corresponding Vc digital signals can be stored in the memory circuit 6.

The amplification factor stored in the memory circuit 6 is Si.
When amplifying, the following operation is performed. The system switching circuit 8 selectively outputs the Vm output from the D / A converter 7 to the gain switching circuit 4 by SEL. In addition, the memory circuit 6
WE is invalidated. The digital signal stored in the memory circuit 6 is extracted by the ADR of the memory circuit 6 corresponding to various input signals and output to the D / A converter 7. D /
The A converter 7 digital-analog converts the digital signal extracted from the storage circuit 6 and outputs Vm to the system switching circuit 8. The system switching circuit 8 is set to D / by SEL.
The output Vm of the A converter 7 is selectively output to the gain switching circuit 4. The gain switching circuit 4 is the D selected by the system switching circuit 8.
The gain of the amplifier 1 is controlled by the output Vm of the / A converter 7. As a result, the amplification degree corresponding to the input Si is controlled by the gain switching circuit 4, and the output So of the amplifier 1 having a predetermined output amplitude is obtained.

Even when Si has a sudden amplitude from a non-amplitude, the amplification degree controlled by the gain switching circuit 4 depends on the gain control voltage obtained by digital-analog converting the digital data of the memory circuit 6 of the address corresponding to Si. Since it has already been set, it converges with damping of several amplitudes.

[0020]

As described above, according to the present invention, when various known fixed-amplitude signals are input, when the input signals are switched, the amplification factor stored corresponding to the input signals is used. The advantage is that the pull-in stabilization time of the output amplitude can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic gain control amplifier of the present invention.

FIG. 2 is a waveform diagram of an example of input / output signals in FIG.

FIG. 3 is a block diagram showing an example of a conventional automatic gain control amplifier.

FIG. 4 is a waveform diagram of an example of input / output signals in FIG.

[Explanation of symbols]

1 amplifier 2 peak hold circuit 3 operational amplifier circuit 4 gain switching circuit 5 analog / digital conversion circuit (A / D converter) 6 memory circuit 7 digital / analog conversion circuit (D / A converter) 8 system switching circuit Si input signal So output Signal Vp Peak hold voltage Vr Reference voltage Vc Gain control voltage Vm Gain control voltage SEL selection signal WE Write enable signal ADR address signal

Claims (1)

[Claims] 1. An amplifier for amplifying a signal according to an amplification degree designated by a gain switching circuit, a peak hold circuit for detecting a peak voltage of an output signal of the amplifier, and a difference between an output voltage of the peak hold circuit and a reference voltage. In an automatic gain control amplifier comprising an operational amplifier for performing operational amplification of the operational amplifier and a gain switching circuit for controlling the gain of the amplifier by the output of the operational amplifier, an analog-digital conversion circuit for converting an output signal of the operational amplifier into a digital signal. A storage circuit for storing a digital signal output from the analog-digital conversion circuit; a digital-analog conversion circuit converting a digital signal from the storage circuit into an analog signal; an output from the operational amplifier and the digital-analog System switching for switching between output of conversion circuit and output to the gain switching circuit An automatic gain control amplifier comprising: a circuit.