JPH0583034A - Frequency conversion circuit - Google Patents

Frequency conversion circuit

Info

Publication number
JPH0583034A
JPH0583034A JP24128791A JP24128791A JPH0583034A JP H0583034 A JPH0583034 A JP H0583034A JP 24128791 A JP24128791 A JP 24128791A JP 24128791 A JP24128791 A JP 24128791A JP H0583034 A JPH0583034 A JP H0583034A
Authority
JP
Japan
Prior art keywords
circuit
signal
differential pair
current source
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP24128791A
Other languages
Japanese (ja)
Inventor
Hajime Iwatsuki
元 岩附
Hideo Sugawara
秀夫 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24128791A priority Critical patent/JPH0583034A/en
Publication of JPH0583034A publication Critical patent/JPH0583034A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To obtain a frequency conversion circuit with an excellent noise figure whose configuration is suitable for circuit integration by taking large isolation between input and output signals with respect to the frequency conversion circuit suitable for circuit integration. CONSTITUTION:The conversion circuit is provided with a differential pair 101 including transistors (TRs), load resistors 102, 103, bias resistors 104, 105, and a current source 106, with a distribution circuit 112 which applies a high frequency signal and a local oscillation signal to each input terminal of the differential pair 101 and extracts an inverting high frequency signal and an inverting local oscillation signal at each output terminal, with a TR 107, a load resistor 108 and a current source 109, and with two single end mixer circuits 110, 111 receiving an output of the distribution circuit 112 at its input terminal and synthesizing the outputs at its output terminal as an intermediate frequency signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は携帯用電話機等に用いら
れる集積回路(IC)化に適した周波数変換回路に関す
る。携帯電話等に用いられる移動用高周波回路は超小型
化が要求されており、従来個別部品で構成していた回路
もIC化が望まれるようになっている。本発明はこのよ
うな実状にかんがみてなされたものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit suitable for an integrated circuit (IC) used in a mobile phone or the like. High-frequency mobile circuits used in mobile phones and the like are required to be ultra-miniaturized, and circuits that are conventionally composed of individual parts are also required to be integrated. The present invention has been made in view of such circumstances.

【0002】[0002]

【従来の技術】従来型のトランジスタを使用した周波数
変換回路は、図4に示されるように2つの周波数の異な
る発振電圧例えば高周波信号RFと局部発振信号Loを
非直線回路に同時に加え、Lo信号電圧によって入力コ
ンダクタンスが周期的に変化し両周波数の和と差の信号
が出力されるのを利用するものである。また、バリィ・
ギルバートにより1968年に発表されたギルバート・
セルと呼ばれる乗算回路もIC化されて周波数変換に用
いられている。(日経エレクトロニクス、1989,
7.10(No.477)参照)
2. Description of the Related Art As shown in FIG. 4, a conventional frequency conversion circuit using a transistor applies an oscillating voltage having two different frequencies, for example, a high frequency signal RF and a local oscillating signal Lo to a non-linear circuit simultaneously to obtain a Lo signal. It utilizes the fact that the input conductance changes periodically according to the voltage and the signals of the sum and difference of both frequencies are output. Also,
Gilbert announced in 1968 by Gilbert
A multiplication circuit called a cell is also integrated into an IC and used for frequency conversion. (Nikkei Electronics, 1989,
See 7.10 (No. 477))

【0003】[0003]

【発明が解決しようとする課題】しかしながら、図4の
回路は各ポート間のアイソレーションがとれていないと
いう欠点がある。そのため、RF信号、Lo信号の同調
回路、およびIF(中間周波)出力ポートにはRF信
号、Lo信号を除去するフィルタ等の対策が必要であっ
た。これらはIC化が困難であり、図4の回路はIC化
には不適当であった。また、ギリバート・セルはIC化
には適当であるが、雑音指数(NF)に問題があった。
従って本発明の目的は、入出力信号相互間のアイソレー
ションがとれ、トランジスタ、抵抗、キャパシタで構成
されIC化に適し、かつ雑音指数が優れた周波数変換回
路を得ることにある。
However, the circuit of FIG. 4 has a drawback in that isolation between ports is not achieved. Therefore, measures such as a filter for removing the RF signal and the Lo signal are required for the tuning circuit for the RF signal and the Lo signal and the IF (intermediate frequency) output port. These are difficult to be integrated into an IC, and the circuit of FIG. 4 is unsuitable to be integrated into an IC. Also, although Gilibert cell is suitable for IC, it has a problem in noise figure (NF).
Therefore, it is an object of the present invention to obtain a frequency conversion circuit which has isolation between input and output signals, is composed of a transistor, a resistor and a capacitor, is suitable for an IC, and has an excellent noise figure.

【0004】[0004]

【課題を解決するための手段】本発明においては、図1
に例示されるように、トランジスタ対を含む差動対10
1と、該差動対に対する負荷抵抗102,103と、該
差動対に対するバイアス抵抗104,105と、該差動
対に対する電流源106を具備し、該差動対101のそ
れぞれの入力端に高周波(RF)信号および局部発振
(Lo)信号を印加し、それぞれの出力端で逆相の高周
波信号および逆相の局部発振信号を取り出す分配回路1
12、および、それぞれ、1つのトランジスタ107、
該トランジスタの負荷抵抗108、および該トランジス
タ107の電流源109を具備し、それぞれの入力端に
前記分配回路112の出力を受け、その出力端で合成し
中間周波(IF)信号とする2個のシングルエンドミキ
サ回路110,111を具備する周波数変換回路が提供
される。
In the present invention, as shown in FIG.
And a differential pair 10 including a transistor pair, as illustrated in FIG.
1, load resistors 102 and 103 for the differential pair, bias resistors 104 and 105 for the differential pair, and a current source 106 for the differential pair, and are provided at respective input terminals of the differential pair 101. A distribution circuit 1 which applies a high frequency (RF) signal and a local oscillation (Lo) signal, and extracts a high frequency signal and a local oscillation signal of the opposite phase at respective output terminals.
12 and one transistor 107, respectively
Two load resistors 108 of the transistor and a current source 109 of the transistor 107 are provided, each input terminal receives the output of the distribution circuit 112, and the output terminals combine the two to generate an intermediate frequency (IF) signal. A frequency conversion circuit including single-ended mixer circuits 110 and 111 is provided.

【0005】[0005]

【作用】上述の回路を用いれば、周波数変換回路がトラ
ンジスタ、抵抗、キャパシタのみで構成できIC化が容
易となる。また2つの入力信号は相殺されて出力信号と
して出力されず、入力信号間のアイソレーションもトラ
ンジスタのコレクタ・ベース間のアイソレーションによ
り確保される。また雑音指数も従来型の回路より改善さ
れる。
When the above circuit is used, the frequency conversion circuit can be composed of only a transistor, a resistor, and a capacitor, which facilitates the formation of an IC. Further, the two input signals are canceled out and not output as an output signal, and the isolation between the input signals is secured by the isolation between the collector and the base of the transistor. The noise figure is also improved over conventional circuits.

【0006】[0006]

【実施例】本発明の第1実施例としての周波数変換回路
の回路図が図1に示される。この回路は、2つのトラン
ジスタを含む差動対101、差動対101に対する負荷
としてのトランジスタのコレクタに接続された抵抗10
2,103、トランジスタのベースに接続されたバイア
ス抵抗104,105、およびトランジスタのエミッタ
に接続された電流源106を具備する分配回路112
と、1つのトランジスタ107、トランジスタ107の
負荷としての抵抗108、トランジスタ107のエミッ
タに接続された電流源109から構成されるシングルエ
ンドミキサ回路110と、他の1つの全く同じ構成のシ
ングルエンドミキサ回路111で構成される。なおシン
グルエンドミキサ回路の電流源はキャパシタにより側路
される。
1 is a circuit diagram of a frequency conversion circuit as a first embodiment of the present invention. This circuit includes a differential pair 101 including two transistors, and a resistor 10 connected to the collectors of the transistors as a load for the differential pair 101.
2, 103, bias resistors 104, 105 connected to the bases of the transistors, and a distribution circuit 112 comprising current sources 106 connected to the emitters of the transistors.
And a single-ended mixer circuit 110 including one transistor 107, a resistor 108 as a load of the transistor 107, and a current source 109 connected to the emitter of the transistor 107, and another single-ended mixer circuit 110 having exactly the same configuration. It is composed of 111. The current source of the single-ended mixer circuit is bypassed by the capacitor.

【0007】差動対101の入力端には、それぞれ高周
波(RF)信号および局部発振(局発:Lo)信号を与
え、差動対の一方の出力を負荷抵抗102とシングルエ
ンドミキサ回路110の入力端に与え、差動対101の
他方の出力を負荷抵抗103とシングルエンドミキサ回
路111の入力端に与える。さらに、シングルエンドミ
キサ回路110および111の出力を出力端で合成し、
中間周波(IF)信号出力端へ供給する。なお、図にお
いてVCCは電源電圧、VB1からVB4はバイアス電圧をそ
れぞれ示す。
A high frequency (RF) signal and a local oscillation (local oscillation: Lo) signal are applied to the input ends of the differential pair 101, and one output of the differential pair is supplied to the load resistor 102 and the single end mixer circuit 110. The other output of the differential pair 101 is applied to the load resistor 103 and the input end of the single-ended mixer circuit 111. Furthermore, the outputs of the single-ended mixer circuits 110 and 111 are combined at the output end,
Supply to the intermediate frequency (IF) signal output. In the figure, V CC indicates a power supply voltage, and V B1 to V B4 indicate bias voltages.

【0008】差動対101に入力された局発信号は2つ
の出力端でそれぞれ逆相に分配され、分配された2つの
局発信号をそれぞれシングルエンドミキサ回路110,
111に与える。差動対101に入力されたRF信号も
同様に逆相でシングルエンドミキサ回路110,111
に入力される。シングルエンドミキサ回路110,11
1の出力端ではRF信号、局発信号共互いに逆相である
ため、キャンセルされる。これにより雑音が軽減され
る。シングルエンドミキサ回路110,111で両信号
を乗算して得られるIF信号は同相で出力されるため、
合成されて、IF信号出力端よりIF信号が取り出され
る。RF信号入力端と局発信号入力端のアイソレーショ
ンはトランジスタのコレクタ・ベース間のアイソレーシ
ョンによって決められている。
The local oscillator signals input to the differential pair 101 are distributed in opposite phases at the two output terminals, and the two distributed local oscillator signals are respectively fed to the single-end mixer circuit 110,
Give to 111. Similarly, the RF signals input to the differential pair 101 are also in anti-phase with the single-ended mixer circuits 110 and 111.
Entered in. Single-end mixer circuits 110, 11
At the output terminal of No. 1, the RF signal and the local oscillation signal have opposite phases to each other, and thus are canceled. This reduces noise. Since the IF signal obtained by multiplying both signals by the single end mixer circuits 110 and 111 is output in the same phase,
After being combined, the IF signal is taken out from the IF signal output terminal. The isolation between the RF signal input end and the local signal input end is determined by the isolation between the collector and base of the transistor.

【0009】図2には本発明の第2実施例が示される。
この回路は図1の2個のシングルエンドミキサ回路のそ
れぞれのトランジスタのコレクタを共通、エミッタを共
通にし(201,202)、負荷抵抗、電流源を共有し
て抵抗203、電流源204としたものである。これ以
外は図1の回路と同様である。
FIG. 2 shows a second embodiment of the present invention.
In this circuit, the collectors of the transistors of the two single-end mixer circuits of FIG. 1 are common, the emitters are common (201, 202), and the load resistance and the current source are shared to form the resistance 203 and the current source 204. Is. Other than this, the circuit is similar to that of FIG.

【0010】図3には本発明の第2実施例の変形例が示
される。この回路は第2実施例の回路にバッファ増幅器
310を付加したものである。すなわち、差動対30
1、負荷抵抗302,303、バイアス抵抗304,3
05、電流源306から構成された分配回路と、トラン
ジスタ対309、負荷抵抗307、電流源308から構
成されたシングルエンドミキサ回路と、3個のトランジ
スタ、2個の抵抗、2個のキャパシタから構成されたバ
ッファ増幅器310から成っている。バッファ増幅器3
10は知られた回路であって、通常のエミッタフォロワ
回路に比べ少ない電流値で利得が得られるため、IC回
路に適している。
FIG. 3 shows a modification of the second embodiment of the present invention. This circuit is obtained by adding a buffer amplifier 310 to the circuit of the second embodiment. That is, the differential pair 30
1, load resistors 302 and 303, bias resistors 304 and 3
05, a distribution circuit including a current source 306, a single-end mixer circuit including a transistor pair 309, a load resistor 307, and a current source 308, three transistors, two resistors, and two capacitors Buffer amplifier 310. Buffer amplifier 3
Reference numeral 10 is a known circuit, which is suitable for an IC circuit because a gain can be obtained with a smaller current value as compared with a normal emitter follower circuit.

【0011】[0011]

【発明の効果】本発明によれば、入出力信号相互間のア
イソレーションが大きくとれ、トランジスタ、抵抗、キ
ャパシタで構成されIC化に適し、かつ雑音指数の優れ
た周波数変換回路が得られる。
According to the present invention, it is possible to obtain a frequency conversion circuit which has a large isolation between input and output signals, is composed of a transistor, a resistor and a capacitor, is suitable for an IC, and has an excellent noise figure.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の周波数変換回路の回路図
である。
FIG. 1 is a circuit diagram of a frequency conversion circuit according to a first embodiment of the present invention.

【図2】第2実施例の周波数変換回路の回路図である。FIG. 2 is a circuit diagram of a frequency conversion circuit according to a second embodiment.

【図3】第2実施例の周波数変換回路の変形例の回路図
である。
FIG. 3 is a circuit diagram of a modification of the frequency conversion circuit of the second embodiment.

【図4】従来型の周波数変換回路の回路図である。FIG. 4 is a circuit diagram of a conventional frequency conversion circuit.

【符号の説明】[Explanation of symbols]

101…差動対 102,103…負荷抵抗 104,105…バイアス抵抗 106…電流源 107…トランジスタ 108…負荷抵抗 109…電流源 110,111…シングルエンドミキサ回路 112…分配回路 201,202…トランジスタ 203…負荷抵抗 204…電流源 301…差動対 302,303…負荷抵抗 304,305…バイアス抵抗 306…電流源 307…負荷抵抗 308…電流源 309…トランジスタ対 310…バッファ増幅器 VB1,VB2,VB3,VB4…バイアス電圧 VCC…電源電圧101 ... Differential pair 102,103 ... Load resistance 104,105 ... Bias resistance 106 ... Current source 107 ... Transistor 108 ... Load resistance 109 ... Current source 110,111 ... Single end mixer circuit 112 ... Distribution circuit 201,202 ... Transistor 203 ... load resistance 204 ... current source 301 ... differential pair 302, 303 ... load resistance 304, 305 ... bias resistance 306 ... current source 307 ... load resistance 308 ... current source 309 ... transistor pair 310 ... buffer amplifier V B1 , V B2 , V B3 , V B4 ... Bias voltage V CC ... Power supply voltage

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 トランジスタ対を含む差動対(101)
と、該差動対に対する負荷抵抗(102,103)と、
該差動対に対するバイアス抵抗(104,105)と、
該差動対に対する電流源(106)を具備し、該差動対
(101)のそれぞれの入力端に高周波(RF)信号お
よび局部発振(Lo)信号を印加し、それぞれの出力端
で逆相の高周波信号および逆相の局部発振信号を取り出
す分配回路(112)、およびそれぞれ、1つのトラン
ジスタ(107)、該トランジスタの負荷抵抗(10
8)、および該トランジスタ(107)の電流源(10
9)を具備し、それぞれの入力端に前記分配回路(11
2)の出力を受け、その出力端で合成し中間周波(I
F)信号とする2個のシングルエンドミキサ回路(11
0,111)を具備することを特徴とする周波数変換回
路。
1. A differential pair (101) including a transistor pair.
And a load resistance (102, 103) for the differential pair,
Bias resistors (104, 105) for the differential pair,
A current source (106) for the differential pair is provided, and a high frequency (RF) signal and a local oscillation (Lo) signal are applied to each input terminal of the differential pair (101), and a reverse phase is applied at each output terminal. Distribution circuit (112) for extracting the high frequency signal and the local oscillation signal of the opposite phase, one transistor (107) and the load resistance (10) of the transistor, respectively.
8) and the current source (10) of the transistor (107).
9), and the distribution circuit (11
The output of 2) is received and combined at the output end to obtain the intermediate frequency (I
F) Two single-ended mixer circuits (11
0, 111).
【請求項2】 前記2個のシングルエンドミキサ回路の
それぞれのトランジスタのコレクタを共通にし、かつエ
ミッタをも共通にし、負荷抵抗と電流源を共有にするよ
うにした請求項1の周波数変換回路。
2. The frequency conversion circuit according to claim 1, wherein the collectors of the respective transistors of the two single-ended mixer circuits are made common, the emitters thereof are made common, and the load resistance and the current source are shared.
JP24128791A 1991-09-20 1991-09-20 Frequency conversion circuit Withdrawn JPH0583034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24128791A JPH0583034A (en) 1991-09-20 1991-09-20 Frequency conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24128791A JPH0583034A (en) 1991-09-20 1991-09-20 Frequency conversion circuit

Publications (1)

Publication Number Publication Date
JPH0583034A true JPH0583034A (en) 1993-04-02

Family

ID=17072025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24128791A Withdrawn JPH0583034A (en) 1991-09-20 1991-09-20 Frequency conversion circuit

Country Status (1)

Country Link
JP (1) JPH0583034A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014240768A (en) * 2013-06-11 2014-12-25 Necネットワーク・センサ株式会社 Frequency shift method of simulating mobile object

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014240768A (en) * 2013-06-11 2014-12-25 Necネットワーク・センサ株式会社 Frequency shift method of simulating mobile object

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Legal Events

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Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981203