JPH0582536A - Method of manufacturing bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To provide the title method of manufacturing bipolar semiconductor device wherein outer base regions in small para-citic capacitance are formed by simple steps while capable of displaying excellent emitter base junction characteristics. CONSTITUTION:An oxide film 3 is formed on a silicon substrate 1 and then a protruded n-type collector layer 4 is epitaxially grown on the substrate surface exposed by forming an aperture part in a true transistor region. Next, a p<+> type polycrystalline silicon 60 is deposited on the whole surface to be buried in a self-alignment manner around the collector layer 4 making the whole surface flat so as to form a base lead-out layer 6 and then a p<+>type base layer 7 and an n-type emitter layer 8 are continuously and epitaxially grown on these collector layer 4 and the base lead-out layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar semiconductor device using a thin film base layer.

[0002]

2. Description of the Related Art It has been reported that a high-speed bipolar transistor can be obtained by using an ultra-thin base layer doped with a high concentration of impurities due to the progress of semiconductor thin film forming technology. In particular, in the case of Si-based bipolar transistors, it has been reported that a heterojunction bipolar transistor having an extremely high operating speed can be obtained by using a thin silicon-germanium (SiGe) alloy film having a thickness of about 0.05 μm as a base layer. With these ultra-thin base layers,
Taking out the base electrode becomes a problem. This is because, when the base layer and the emitter layer are continuously epitaxially grown and then the base layer is exposed, it is difficult to etch the emitter layer leaving the thin base layer in view of controllability.

As one method for solving this problem, the following method has been proposed. After growing the base layer, an external base layer is formed around the nitride film mask in the emitter formation region. After that, the nitride film mask is removed, polycrystalline silicon doped with impurities at a high concentration is deposited, and an emitter layer is formed by diffusing impurities from the polycrystalline silicon (JP-A-2-40923 or JP-A-2-151031). (See the official gazette).

However, in this method, since the emitter layer is basically formed by diffusion, it becomes difficult to control the thickness (base width) of the base layer composed of an ultrathin film.
Further, since the surface of the base layer is once exposed to the outside air and a treatment such as mask formation and its removal is performed on the surface of the base layer, it is difficult to obtain a good pn junction.

On the other hand, a method of forming an external base layer in advance before forming a thin film base layer has also been proposed (see Japanese Patent Laid-Open No. 2-106937). According to this method, since the base layer and the emitter layer can be continuously grown, the thickness of the base layer can be easily controlled, and the pn junction characteristics of the base-emitter can be excellent.

However, this method has a problem how to easily form the external base layer having a small parasitic capacitance. For example, in order to reduce the parasitic capacitance of the external base region, a step of burying an insulating film is required before forming the external base, which complicates the exposure process.

[0007]

As described above, in the conventional method for manufacturing a bipolar transistor using the ultra-thin base layer, the external base region having a small parasitic capacitance is formed while ensuring good emitter-base junction characteristics. There was a problem that it could not be built by a simple process.

The present invention has been made in consideration of the above circumstances, and it is possible to easily form an external base region having a small parasitic capacitance and to obtain excellent emitter-base junction characteristics. An object is to provide a method for manufacturing a device.

[0009]

A method of manufacturing a bipolar semiconductor device according to the present invention is of a first conductivity type in which an intrinsic transistor region on a semiconductor substrate has a convex shape with its periphery covered with an insulating film. After the collector layer is grown, a low-resistance base extraction layer is deposited on the entire surface, the base extraction layer is buried around the collector layer, and the surface of the collector layer is exposed. A second conductive type base layer and then a first conductive type emitter layer are continuously grown on the extraction layer.

[0010]

According to the method of the present invention, since the base layer and the emitter layer are continuously formed, it is easy to control the thickness of the ultrathin base layer, and the emitter-base junction characteristics are excellent. Be done. Further, in a state where the collector layer is formed in a convex shape and the substrate surface around the collector layer is covered with an insulating film,
A base extraction layer is formed in self-alignment with an outer base region around the collector layer. Therefore, the step of burying the base lead layer is simple, and the parasitic capacitance is small because the base lead layer is an insulating film below.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a manufacturing process of a Si / SiGe heterojunction bipolar transistor according to an embodiment of the present invention.

As shown in FIG. 1 (a), n ^{+ is formed} on the p-type silicon substrate 1. After forming the mold sub-collector layer 2, the thermal oxide film 3 on the entire surface is formed. A part of this thermal oxide film, that is, a part which becomes an intrinsic transistor region is removed by etching, and a convex n-type silicon collector layer 4 is epitaxially grown on the exposed substrate to continuously thin the non-doped silicon layer 5. Grow. The growth of the n-type collector layer 4 is
By the CVD method using disilane gas and arsine gas.
The growth conditions are, for example, a substrate temperature of 630 ° C. and a disilane gas pressure of 3 × 10 ⁻² Pa in the growth container. The As concentration of the n-type collector layer 4 is 3 × 10 ¹⁷ / cm ³ And The non-doped (i-type) silicon layer 5 has a thickness of, for example, about 15 nm, and this is for reducing the pn junction capacitance between the external base layer and the collector which will be formed later.

Thereafter, the dopant gas is switched to diborane, and as shown in FIG. 1 (b), a high concentration of p ⁺ used as a base extraction layer is used. The type silicon layer 60 is grown to the same thickness as the convex collector layer 4. The growth conditions are a diborane partial pressure of 3 × 10 ^-2 Pa and a substrate temperature of 830 ° C.
And The silicon layer 60 obtained under these conditions is single crystal on the collector layer 5 and becomes polycrystalline silicon on the oxide film 3 around it. The concentration of the obtained silicon layer 60 is 1 × 10 ²⁰ / cm ³ The degree.

After that, the substrate was taken out from the growth apparatus, and as shown in FIG.
As shown in (c), the silicon layer 60 is buried around the collector layer 4 to obtain a state where the surface is flattened with the collector layer 4 exposed. This structure can be obtained, for example, by applying a photoresist so that the surface becomes flat and then performing dry etching under the condition that the etching rates for the photoresist and silicon are equal. That is, with respect to the collector layer 4 having a convex shape, p having a low resistance is provided around the collector layer 4.
⁺ A base lead-out layer 6 of type polycrystalline silicon is self-aligned and buried.

Subsequently, the substrate is again introduced into the growth apparatus,
After the surface cleaning treatment by heat treatment in a hydrogen atmosphere, as shown in Fig. 2 (a), p ⁺ Type silicon-germanium alloy base layer 7 is grown to a thickness of 80 nm, and then n-type silicon emitter layer 8 is continuously grown to 500 nm.
Grow to nm thickness. The impurity concentrations of the base layer 7 and the emitter layer 8 are 5 × 10 ¹⁹ / cm ³ respectively. , 1 × 10 ¹⁸ /
cm ³ And

Then, the substrate is taken out from the growth apparatus,
As shown in FIG. 2 (b), the emitter layer 8 is etched into a mesa shape, and the collector extraction region is further etched to form n ⁺ After exposing the mold subcollector layer 2 and covering the element surface with an oxide film 9, an electrode contact hole is opened to form an emitter electrode 10, a base electrode 11, and a collector electrode 12.

According to this embodiment, the p-type base layer 7 and n
Since the type emitter layer 8 is continuously formed, the film thickness controllability of the base layer 7 by the ultrathin film, that is, the base width controllability is excellent, and the surface of the p-type base layer 7 may be exposed to the atmosphere. And a good emitter-base junction is obtained. In addition, the base extraction layer 6 is buried in the periphery of the convex collector layer 4 in a self-aligned manner without requiring a complicated exposure process. The base electrode 11 is a thin p-type base layer 7
Since there is a thick low-resistance external base layer 6 underneath, reliable contact can be made. Since the oxide film 3 is formed under the base extraction layer 6, the parasitic capacitance between the base and the collector is also small. In this embodiment, an i-type silicon layer 5 is further formed around the n-type collector layer 4,
Since this enters between the base extraction layer 6 and the n-type collector layer 4, this also contributes to the reduction of the parasitic capacitance between the base and the collector.

The present invention is not limited to the above embodiment. For example, in the embodiment, i is formed around the n-type collector layer 4.
Although the type silicon layer 5 is formed, an insulating film may be formed instead of the i type silicon layer 5. The structure corresponding to FIG. 1 (c) in that case is shown in FIG. An oxide film 13 is formed between the collector layer 4 and the base extraction layer 6 buried in the periphery thereof. This state can be obtained by performing thermal oxidation instead of forming the i-type silicon layer 5 in the step of FIG. An oxide film is also formed on the upper surface of the collector layer 4, but this oxide film is removed in the steps described with reference to FIGS. 1B and 1C, and a state where it is left only on the side surface of the collector layer 4 can be obtained. By doing so, the parasitic capacitance between the base and the collector can be further reduced.

Further, the formation of the i-type silicon layer 5 and the oxide film 13 instead of the i-type silicon layer 5 may be omitted. Even with this, since the oxide film 3 is provided between the base extraction layer 6 and the substrate 1, the effect of reducing the parasitic capacitance is sufficiently large.

Further, in the embodiment, the heterojunction bipolar transistor using the silicon-germanium alloy for the base layer has been described, but the present invention can be similarly applied to the homo-matching bipolar transistor using only silicon, for example.

In the embodiment, the bipolar transistor of the emitter top is explained, but the present invention can be applied to the bipolar transistor of the collector top in the same manner. Furthermore, the present invention can be implemented with various modifications such as using a conductor instead of a semiconductor as the base extraction layer without departing from the spirit of the present invention.

[0022]

As described above, according to the present invention, in a bipolar transistor having a thin film base structure, a base extraction layer is formed in an external base region in a simple process with a small parasitic capacitance in a self-aligned manner. In addition, excellent emitter-base junction characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the embodiment.

FIG. 3 is a cross-sectional view corresponding to FIG. 1 (c) of another embodiment.

[Explanation of symbols]

1 ... p-type silicon substrate, 2 ... n ⁺ Type subcollector layer, 3 ... Oxide film, 4 ... N type collector layer, 5 ... i type silicon layer, 6 ... P ⁺ Mold base drawer layer, 7 ... p ⁺ N-type emitter layer, 9 ... Oxide film, 10 ... Emitter electrode, 11 ... Base electrode, 12 ... Collector electrode, 13 ... Oxide film.

Claims (1)

[Claims] 1. An intrinsic transistor region on a semiconductor substrate,
A step of growing a first conductive type collector layer having a convex shape with the periphery covered with an insulating film, and depositing a low resistance base lead layer on the entire surface and burying it around the collector layer. A step of planarizing the collector surface with the collector surface exposed, and a step of continuously growing a second conductive type base layer and subsequently a first conductive type emitter layer on the collector and the base extraction layer. A method of manufacturing a bipolar semiconductor device, comprising: