JPH0581936B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a multiprocessor system comprised of symmetric homogeneous processors adapted to perform serialization of system resources.

[Technical background of the invention]

Conventionally, system resources with short exclusive exclusive use times have been serialized as follows. (1) In a single processor system, resources are serialized by disabling interrupts and ensuring that other programs are never run in parallel. (2) In a multiprocessor system, serialization is achieved by setting the lock word to indicate that the resource is in use.
In this case, parallel processing is possible if the resources are separate.

[Problems with background technology]

The method shown in (1) cannot be used in a multiprocessor system, and the method (2) becomes complicated to use as the number of lock types increases, and the lock overhead is lower than that of method (1). It had some drawbacks, such as being large. Another disadvantage is that it takes a lot of effort to relocate a program developed using method (1) to adapt it to the serialization method of a multiprocessor system.

[Object of the Invention] In view of the above-mentioned drawbacks, the object of the present invention is to provide a multiprocessor system consisting of symmetric homogeneous processors that can serialize system resources at the same level as the interrupt disabling method of a single processor. Our goal is to provide the following.

[Summary of the invention]

In the present invention, a multiprocessor system consisting of a plurality of symmetrical and homogeneous processors includes CPU status detection hardware that detects whether each processor is normal or abnormal, and whether each processor is normal or not detected by this CPU status detection hardware. , one processor is designated as the serialization processor from among the normally operating processors based on the abnormality information, and when the designated serialization processor becomes abnormal, one of the other normally operating processors is designated as the serialization processor. serialization processor designation hardware for designating a processor as a serialization processor anew; If the serialization task detecting means detects that serialization is not specified, the task is executed, while if it is detected that serialization is specified, the serialization processor specified hardware is executed. The above object is achieved by providing a task execution means that executes the task in an interrupt-disabled state only when the task is specified by the software.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a system resource serialization method in a multiprocessor system according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the system resource serialization method in a multiprocessor system of the present invention is applied. A symmetric homogeneous processor (below
(referred to as CPUs) 1 to 4 and a main storage device 5 are connected to a common bus 6. Reference numeral 7 denotes serialization processor designation hardware (for example, a depth switch) that selects only one processor from among the CPUs 1 to 4 as a serialization processor.
CPUs 1 to 4 are provided with flags 71 to 74 corresponding to each CPU to indicate whether or not the CPU is a serialization processor, and the serialization processor designation hardware 7 is a CPU designated for serialization. flags can be set for serialization.

FIG. 2 shows an example of a data structure used by a task dispatcher of an operating system (OS) operating according to the system shown in FIG. 21 indicates a task queue in an executable state, and 220 to 240 indicate TCBs representing tasks.
(task control block), 221
.about.241 indicates a field indicating whether or not this task is specified to be serialized.

Next, the operation of this embodiment will be explained. At the time of system startup or when the execution of a group of serialized tasks is started, the hardware 7 selects an appropriate one from CPUs 1 to 4 as the serialized execution processor, and sets the flag corresponding to this selected CPU. Set for serialization. Each CPU 1 to 4 has an executable task queue 2 stored in the main memory 5.
Select the task with the highest priority from 1. TCB220-24 in Task Queue 21
Since 0 is entered in order of priority, the first TCB 220 is selected. At this time, the field 221 is checked and if serialization is not specified, the task is executed. If field 221 specifies serialization, the CPU checks its corresponding flag and thereby
If the CPU is for serialization, execute that task,
If it is not the serialization CPU, the next TCB 230 is selected and a similar check is performed. Not for serialization
The CPU never executes serialized tasks.
On the other hand, the serialization CPU executes tasks in priority order without distinguishing between serialization-designated tasks and non-serialization-designated tasks.

According to this embodiment, a task group that requires serialization regarding a specific data structure or logic is executed by a single processor designated by the serialization processor designation hardware 7 from among the multiprocessors 1 to 4, and By operating this serialization execution processor with interrupts disabled, it is possible to perform serialization at the same level as a single processor with interrupts disabled. Therefore, the effort required to transfer a program developed on a single processor system to a multiprocessor system can be reduced. Furthermore, compared to the conventional method of serialization by locking, the overhead for serialization can be reduced and the method of use can be simplified. Furthermore, in this embodiment, tasks other than the task group that requires serialization can be processed by other processors without being affected in any way.

Although the above embodiment describes an example in which a multiprocessor system is configured with four CPUs, the same effect can be obtained even if the number of CPUs is arbitrary.
However, a flag is required for each CPU.

FIG. 3 is a block diagram showing another embodiment of a multiprocessor system to which the system resource serialization method in a symmetric homogeneous multiprocessor system of the present invention is applied. Symmetrically homogeneous processors (CPUs) 1 to 4 and a main memory 5 are connected to a common bus 6. Reference numeral 7 denotes serialization execution processor designation hardware that selects the only normally operating processor from among the CPUs 1 to 4 as the serialization processor. This hardware 7
CPU state detection hardware 8 is connected to detect whether or not the CPUs 1 to 4 operate normally. CPUs 1 to 4 have flags 71 to 74 indicating whether the CPU is a serialization processor or not.
The hardware 7 is provided corresponding to the CPU, and sets the flag of the designated CPU for serialization. The example data structure used by the task dispatcher of the operating system operating according to the system shown in FIG. 3 is the same as that shown in FIG.

Next, the operation of this embodiment will be explained. The CPU specification hardware for serialization selects and serializes only one CPU from among the CPUs that are operating normally, based on the normal/abnormal information of CPUs 1 to 4 detected by the CPU status detection hardware 8. specified for
Set the corresponding flag for serialization. Each CPU
selects the task to be executed from the task dispatcher from the executable task queue 21 (see Figure 2), but at this time, the task specified as the serialization CPU
Only the CPU can execute the serialization designated tasks shown in fields 221-241.

It is now assumed that the CPU 1 has been designated as a serialization CPU, the flag 71 is on, and the flags 72 to 74 are off. At this time, when an abnormality occurs in the CPU 1 and the CPU 1 stops, the CPU status detection hardware 8 detects the abnormality in the CPU 1, and this information is notified to the serialization processor designation hardware 7. Then, the serialization processor designation hardware 7 immediately releases CPU1 from the designated CPU for serialization and turns off the flag 71, and further designates a normal CPU, for example, CPU2, as the CPU for serialization and turns on the flag 72. . Similarly, if this CPU2 causes an error and stops, the next CPU
3 is designated as the serialization CPU.

The embodiment shown in FIG. 1 has the disadvantage that if the processor designated for serialization stops due to an error, the tasks in the task group designated for serialization will not be executed. For example, if a processor that specifies serialization fails,
The CPU status detection hardware 8 detects this information, and upon receiving this information, the serialization processor designation hardware 7 sequentially designates the only serialization processor from among the normal processors, and processes the tasks that have been designated for serialization. Therefore, it is possible to continue serialization processing by disabling interrupts without any software awareness. Note that other effects of this embodiment are similar to those of the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, one processor is designated as a serialization processor from among the processors that operate normally based on the normality/abnormality information of each processor, and the designated serialization processor is If an error occurs, one processor is designated as the serialization processor from among the other normally operating processors, so the serialization execution of tasks may be interrupted due to an error in the specified serialization processor. It will continue without interruption. In addition, the task is executed with interrupts disabled only when the serialization processor specification hardware specifies the task, so even though it is a multiprocessor system,
Serialization of system resources is achieved through simple control. In other words, since system resources are serialized under the same control as in a single processor, it is suitable for adapting a program developed on the premise of serialization of system resources due to the interrupt disabled state in a single processor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the system resource serialization method in a multiprocessor system of the present invention is applied;
FIG. 2 is a diagram showing an example of a data structure used by the task dispatcher of an operating system that operates according to the system shown in FIG. 1, and FIG. 3 is a system resource serialization method in the multiprocessor system of the present invention. FIG. 2 is a configuration diagram showing another embodiment of a multiprocessor system to which the above is applied. 1 to 4...Processor, 5...Main storage device, 6
...Common bus, 7...Serialization processor specification hardware, 8...CPU status detection hardware,
71-74...Flag.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a plurality of symmetrical and homogeneous processors, there is CPU status detection hardware that detects whether each processor is normal or abnormal; One processor is designated as the serialization processor based on the processor normality/abnormality information, and if the specified serialization processor becomes abnormal, it is designated as the serialization processor among the normally operating processors. serialization processor designation hardware for re-designating one processor as a serialization processor, and each processor includes serialization task detection means for detecting whether serialization has been designated for a task. When this serialization task detection means detects that serialization is not specified, the task is executed, and when it is detected that serialization is specified, the serialization task is executed. A multiprocessor system comprising: task execution means for executing a task in an interrupt-disabled state only when designated by processor designation hardware.