JPH0581888A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction with a power source noise by enhancing a resistance for the power source noise and simultaneously reducing the generation of the power source noise in a semiconductor integrated circuit, e.g. an EPROM. CONSTITUTION:The resistance for the power source noise is enhanced by an ATD circuit 87 and a data latch circuit 86 and the generation of the VSS noise is suppressed by a noise filter 105, the ATD circuit 106 and an output presetting circuit 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more specifically, in a semiconductor integrated circuit, fluctuations in internal power supply voltage generated when output changes, that is, reduction of power supply noise and resistance to such power supply noise. Regarding the strengthening of.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits are required to operate at high speed regardless of whether they are logic integrated circuits or memory integrated circuits. To this end, it is necessary to increase the current supply capacity and current absorption capacity of the output circuit that drives the load, and to charge and discharge the load capacity at high speed.

However, if the charging and discharging of the load capacitance is performed too fast, the peak value of the current flowing from the Vcc power supply terminal on the high voltage side and the current flowing out to the Vss power supply terminal on the low voltage side becomes too large. This may act on the inductance component of the wiring such as the bonding wire to cause the internal power supply voltage of the semiconductor integrated circuit to fluctuate greatly, resulting in malfunction. This point will be described in more detail.

FIG. 6 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit. This semiconductor integrated circuit has a semiconductor chip stored in a package.
1 is a semiconductor chip, 2 is a package, 3 is a package 2
Input signal external terminals 4 provided on the semiconductor chip 1 are input signal pads provided on the semiconductor chip 1.

Reference numeral 5 denotes an output buffer, which is DATA
Is an internal data signal, Z is a high impedance control signal based on the logic of an input control signal for output, 6 is an inverter, and 7 is
Is a NAND circuit, 8 is a NOR circuit, 9 is a pMOS, and 10
Is an nMOS. Further, 11 is a pad for an output signal,
12 is an external terminal for an output signal, DO is an output signal, and CL is a load capacitance.

Reference numeral 13 is a Vcc power source, for example, 5 [V].
, 14 is an external power supply line for supplying
Reference numeral 15 is a pad for the Vcc power supply, 16 is a bonding wire connecting the external terminal 14 and the pad 15, and L ₁ is an inductance component of a current path from the external terminal 14 to the pad 15.

Also, 17 is a Vss power source, for example, 0 [V].
External power supply line for supplying Vss, external terminal for Vss power supply,
Reference numeral 19 is a Vss power supply pad, 20 is a bonding wire connecting the external terminal 18 and the pad 19, and L ₂ is an inductance component of a current path from the external terminal 18 to the pad 19.

In this semiconductor integrated circuit, the high impedance control signal Z is at a low level (hereinafter referred to as "L") and the internal data signal DATA is at a high level (hereinafter, referred to as "L").
In the case of “H”), the outputs of the NAND circuit 7 and the NOR circuit 8 both become “L”, and the pMOS 9 turns on (O).
N), the nMOS 10 is turned off, so that the output signal DO becomes “H”.

On the other hand, when the high impedance control signal Z is "L" and the internal data signal DATA is "L", the outputs of the NAND circuit 7 and NOR circuit 8 are both "H", and the pMOS 9 is off. Since the nMOS 10 is turned on, the output signal DO becomes "L".

When the high impedance control signal Z is "H", the output of the NAND circuit 7 is "H" and the output of the NOR circuit 8 is "H" regardless of whether the internal data signal DATA is "H" or "L". Output becomes "L" and pMOS
Since 9 and nMOS 10 are both off, the output is in a high impedance state.

Here, the output signal DO changes from "L" to "H".
Load capacitance CL changes from the external power supply line 13 to the external terminal 14, the bonding wire 16, the pad 1
5, the current I ₁ flowing through the pMOS 9, the pad 11 and the external terminal 12 charges the battery from 0 [V] to 5 [V].

In this case, the current I ₁ acts on the inductance component L ₁ , so that the voltage of the pad 15 becomes lower than the power supply voltage 5 [V] supplied from the external power supply line 13. However, this point does not matter so much unless the output signal DO is changed at high speed.

On the contrary, when the output signal DO changes from "H" to "L", the load capacitance CL changes from the load capacitance CL to the external terminal 12, the pad 11, the nMOS 10, the pad 19, the bonding wire 20, and The current I ₂ flowing out to the external power supply line 17 for the Vss power supply via the external pin 18 causes the discharge from 5 [V] to 0 [V].

In this case, the current I ₂ acts on the inductance component L ₂ so that the voltage of the pad 19 is 0 V which is set by the external power line 18.
It becomes higher than [V].

Here, in this semiconductor integrated circuit,
Since the input signal is given with reference to 0 [V] of the external power supply line 17 supplied to the external terminal 19, when the Vss power supply pad 19 becomes higher than 0 [V], the input signal from the pad 19 is The level may fluctuate, and the internal circuit may erroneously read the input signal and erroneously output it.

Therefore, conventionally, as a countermeasure against this, after detecting a change in the input signal, in response to this, the output signal is slowly changed to "L" to be 0 [V] in advance, and then the normal signal is applied. The method of outputting the data of was taken. According to this method, when the output signal changes from "H" to "L", the voltage fluctuation generated in the Vss power supply pad 19, that is, Vss noise can be suppressed.

FIG. 7 shows an EPR obtained by adopting such a method.
OM (Electrically programmable read only memory)
3 is a circuit diagram showing a main part of FIG. In the figure, 21 is an EPROM chip, 22 is a package, 23 is an external terminal for address signals, and 24 is a pad for address signals.

Reference numeral 25 is an address buffer, 26 is a decoder, 27 is a cell array, 28 is a sense amplifier, and 29 is a sense amplifier.
Is an output buffer, 30 is an address transition detection circuit (hereinafter,
Reference numeral 31 denotes an output preset circuit, and their functions and circuit configurations will be described later. Further, 32 is an output signal (data) pad, 33 is an external terminal for output signal, DO is an output signal, and CL is a load capacitance.

Further, 34 is an external power source line for Vcc power source, 3
5 is an external terminal for the Vcc power supply, 36 is a pad for the Vcc power supply, 37 is a bonding wire connecting the external terminal 35 and the pad 36, L ₃ is an inductance component of a current path from the external terminal 35 to the pad 36, 38 Is a Vcc power supply line in the EPROM chip 21.

Reference numeral 39 denotes an external power supply line for Vss power supply, 4
0 is an external terminal for the Vss power supply, 41 is a pad for the Vss power supply, 42 is a bonding wire connecting the external terminal 40 and the pad 41, L ₄ is an inductance component of a current path from the external terminal 40 to the pad 41, 43 Is a Vss power supply line in the EPROM chip 21.

The address buffer 25 outputs internal address signals a ₀ and / a ₀ (a ₀ bar) obtained by converting the address signal A ₀ input to the pad 24 into a complementary signal, as shown in FIG. The circuit diagram is shown in FIG. In the figure, 44 and 45 are inverters.

Further, the decoder 26 receives the word line X _{0 of} the cell array 27 from the internal address signals a ₀ and / a ₀ output from the address buffer 25 and the output Ai of another address buffer (not shown). The selection and non-selection of X ₁ are performed, and the circuit diagram thereof is shown in FIG. In the figure, 46 and 47 are NAND circuits, and 48 and 49 are inverters.

The cell array 27 is formed by arranging EPROM cells, and its circuit diagram is shown in FIG. In the figure, 50 to 53 are EPROMs
Cells, 54 and 55 are bit lines, and 56 and 57 are nMOSs that select and deselect bit lines.

Further, Y ₀ and Y ₁ are gate lines for selecting and deselecting the nMOSs 56 and 57, and BUS is a bus line. That is, the cell array 27 selects the EPROM cells 50 to 53 by the word lines X ₀ and X ₁ and the gate lines Y ₀ and Y ₁ .

The sense amplifier 28 also includes a decoder 26.
It is detected whether the EPROM cell selected by "1" stores "1" (whether current is passed when selected) or "0" is stored (whether current is not passed when selected). Yes, the circuit diagram is shown in FIG.

In the figure, 58 to 60 are nMOS, 61 is pM.
OS and PC are precharge pulses supplied from the ATD circuit 30, BIAS is a bias voltage, and SO is the output of this sense amplifier 28, that is, sense out.

Here, the precharge pulse PC becomes "H" for a predetermined time when the address signal changes, as described later. In this case, the nMOS 58 is turned on and the bus line BUS is charged via the nMOSs 58 and 59.

After that, the word lines X ₀ and X ₁ and the gate line Y
_{When the} EPROM cell is selected by ₀ and Y ₁ , the precharge pulse PC becomes “L”. In this case, pM
Selected EPRO via OS61 and nMOS60
It is detected whether or not a current flows through the M cell.

That is, the sense amplifier 28 outputs "1" as the sense-out SO when the selected EPROM cell passes the current, and senses when the selected EPROM cell does not pass the current. "0" is output as the out SO.

The bias voltage BAIS is determined by the bus line B
In order to prevent erroneous writing during precharging of US and reading of EPROM cells 50 to 53, nMOS 59, 6
0 for controlling the drain voltage of these EPROM cells 50 to 53.

The output buffer 29 is constructed as shown in the circuit diagram of FIG. In the figure, 63 is an inverter, 64 is a NAND circuit, 65 is a NOR circuit, and 66.
Is a pMOS, 67 is an nMOS, and ZP is a high impedance control signal supplied from the ATD circuit 30.

In the output buffer 29, the high impedance control signal ZP is "L", and the sense out S
When O is “H”, the NAND circuit 64 and the NOR circuit 6
Outputs of 5 are both "L", pMOS 66 is on, n
Since the MOS 67 is turned off, the output signal DO becomes "H".

On the other hand, when the high impedance control signal ZP is "L" and the sense output SO is "L",
The outputs of the NAND circuit 64 and the NOR circuit 65 both become "H", the pMOS 66 turns off, and the nMOS 67 turns on, so the output signal DO becomes "L".

When the high impedance control signal ZP is "H", the output of the NAND circuit 64 is "H" and the NOR circuit 65 is irrespective of whether the sense output SO is "H" or "L". Output becomes "L" and pMO
Since both S66 and nMOS67 are turned off, the output is in a high impedance state.

As shown in FIG. 13, the ATD circuit 30 detects a change in the output a ₀ of the address buffer 25, internally generates an ATD pulse AP, and externally supplies it to a sense amplifier 28. Precharge pulse PC,
The high impedance control signal ZP supplied to the output buffer 29 and the output preset signal DP supplied to the output preset circuit 31 are output.

Reference numeral 68 is an exclusive OR circuit, and 69 to 7
Reference numeral 1 is a delay circuit, 72 is a NOR circuit, and 73 is an inverter. Here, in particular, 70 and 71 are CR type delay circuits, 74A, 74B, 75A and 75B are inverters and 7
Reference numerals 6 and 77 are resistors, and 78 and 79 are capacitors. Further, as described above, Z is a high impedance control signal based on the logic of an input signal for normal output control.

The output preset circuit 31 outputs the output signal D when the output preset signal DP is set to "H".
O is gradually set to 0 [V], and its circuit diagram is shown in FIG. In the figure, 80 is an inverter, 81 is a delay circuit, 82 is an inverter, and 83
Is a resistance and 84 is a capacitance. Further, 85 is an nMOS.

FIG. 15 is a time chart showing the operation of the EPROM. In such EPROM,
For example, when the address signal A ₀ changes, the ATD circuit 3
0 detects this, internally generates the ATD detection signal AP, and based on this, sets the output preset signal DP, the precharge pulse PC and the high impedance control signal ZP to “H” externally. ..

Here, the output preset signal DP is "H".
When the output signal DO is at “H” in the case of being set to “0”, the output preset circuit 31 gradually sets the output signal DO to “L”.

The precharge pulse PC is "H".
Then, the cell array 27 is turned on via the sense amplifier 28.
Of the bus line BUS is selected, the word lines X ₀ and X ₁ are selected and non-selected, and the gate lines Y ₀ and Y ₁ are selected.
Deselection is done. After that, precharge pulse PC
Returns to “L”, and the sense out SO output from the sense amplifier 28 is fixed.

That is, in this EPROM, when the address signal changes, the address signal is taken in and the output signal is gradually set to "L", and then the regular data from the address designated by the address signal is read.

Therefore, when the output signal DO changes from "L" to "H", the voltage of the pad 36 for the Vcc power supply fluctuates and Vcc noise occurs, but the output signal DO changes to "H". When changing from “L” to “L”, the voltage of the pad 41 for Vss power supply does not change, and Vss noise does not occur.

Here, from "L" to "H" of the output signal DO.
If the change to is not so steep, the Vcc noise is small, no erroneous reading of the address signal occurs, and no particular problem occurs.

However, as shown in FIG. 16, when the output signal DO changes abruptly from "L" to "H" in order to increase the speed, the external power supply line 34 to the external terminal 35,
The peak value of the current flowing through the bonding wire 37 and the pad 36 becomes large, and this acts on the inductance component L ₃ of the current path from the external terminal 35 to the pad 36, causing the voltage of the pad 36 to fluctuate greatly.
That is, the Vcc noise becomes large.

Therefore, in the address buffer 25, the address signal input to the pad 24 is shown in FIG.
It appears to change as indicated by x, and the address signal is read as changed. Therefore, the read operation is performed and erroneous output is performed.

Thus, in this EPROM, H,
Noise generated on the Vss power supply pad 41, that is, Vss
Although the noise can be suppressed, the noise generated in the pad 36 for the Vcc power supply, that is, the Vcc noise cannot be reduced, and when such Vcc noise occurs, an erroneous reading of the address signal may occur. is there. In other words, this EPROM is not very resistant to Vcc noise.

Here, as a method for improving the resistance to the power supply noise, for example, there is a method in which the delay time of the address buffer 25 is lengthened so as not to react to the power supply noise. However, in this method, the reading speed becomes slow. There is an inconvenience that it ends up.

Therefore, as a method of improving resistance to power supply noise, a change in the address signal is detected, and in response to this, the previous data, that is, the data before the change in the address signal is latched, and the address signal changes. A method has been proposed in which the latch of the previous data is released after a lapse of time from the determination of the sense-out SO.

According to this method, when the change of the address signal due to the power supply noise occurs, the previous data (normal data) is latched and continuously output, and thereafter,
When the address signal changes due to power supply noise, the data at the read address will be output, but this address should be the same address as the address at which the previous data was output. The data output by the generated address is the same as the previous data. Therefore, erroneous output of the output signal due to power supply noise can be prevented.

An EPROM adopting this method is shown in FIG. This EPROM does not have the output preset circuit 31 provided in the EPROM of FIG. 7. Instead of this, a data latch circuit 86 is provided between the sense amplifier 28 and the output buffer 29, and the ATD shown in FIG.
An ATD circuit 87 having a circuit configuration different from that of the circuit 30 is provided. The other parts are configured similarly to the EPROM of FIG.

Here, the data latch circuit 86 is connected to the ATD.
Based on the latch pulse LP supplied from the circuit 87,
The data D of the previous cycle output by the current cycle is latched until the sense-out SO of the current cycle is determined, and the circuit is shown in FIG.
In the figure, 88 and 89 are digital switches, and 90 to 92 are inverters.

As shown in the circuit diagram of FIG. 19, the ATD circuit 87 detects a change in the output a ₀ of the address buffer 25 and internally generates the ATD pulse AP,
Externally, the precharge supplied to the sense amplifier 28
It outputs a pulse PC and a latch pulse LP to be supplied to the data latch circuit 86.

Incidentally, 93 is an exclusive OR circuit, and 94 to 9
6 is a delay circuit. Here, in particular, 95 and 96 are CR
Type delay circuit, 97-100 are inverters, 10
Reference numerals 1 and 102 are resistors, and 103 and 104 are capacitors.

FIG. 20 is a time chart showing the operation of the EPROM. In such EPROM,
For example, when the address signal A ₀ changes, the ATD circuit 8
7 detects this, internally generates the ATD pulse AP, and externally sets the precharge pulse PC and the latch pulse LP to "H" based on this.

Here, when the precharge pulse PC is set to "H", the bus line BUS of the cell array 27 is precharged via the sense amplifier 28, and the word lines X ₀ and X ₁ are selected and non-selected. Selection and selection / non-selection of the gate lines Y ₀ and Y ₁ are performed. After that, the precharge pulse PC returns to "L", and the sense out SO output from the sense amplifier 28 is fixed.

On the other hand, in the data latch circuit 86,
By setting the latch pulse LP to "H", the data of the previous cycle is held. Then, after the sense-out SO is determined, the latch pulse LP is set to “L”, and the sense-out SO is transmitted to the output buffer 29.

In this EPROM, the output signal DO
Change from "L" to "H" causes a voltage fluctuation in the pad 36, and in the address buffer 25, the pad 2
Even if the address signal A ₀ input to 4 appears to fluctuate as shown in FIG. 20x and the address signal is read as changed, no erroneous output occurs.

Because, in this case, the reading is performed again, but first, after the normal data is latched, the reading is performed, and when the sense-out SO is determined, the power supply noise has subsided, and ,
This sense-out SO is the same data as the previous cycle (regular data), and since this data is transmitted, the output does not change and no erroneous output occurs.

If the power supply noise continues for a long time, the precharge pulse PC and the latch pulse LP also automatically become long, so there is no problem in this respect. That is, the time when the precharge pulse PC and the latch pulse LP return to "L" is based on the time when the change of the address signal A ₀ ends.

[0060]

PROBLEM TO BE SOLVED BY THE INVENTION The EP shown in FIG.
The ROM can increase the resistance to power supply noise, but cannot reduce the generation of power supply noise itself.
Note that the EPROM shown in FIG. 7 can reduce the occurrence of power supply noise, but is not highly resistant to power supply noise.

Here, if the resistance to the power supply noise is simply increased, the power supply noise is increased due to the increase in speed, the operation becomes unstable, and the power supply noise is generated only by reducing the generation of the power supply noise. If it happens, it will malfunction.

In view of the above point, the present invention has high resistance to power supply noise and reduces the occurrence of power supply noise.
An object of the present invention is to provide a semiconductor integrated circuit capable of preventing malfunction due to power supply noise and improving its reliability.

[0063]

In a semiconductor integrated circuit according to the present invention, a first input change detecting means for detecting a normal change of an input signal, and a first input output by the first input change detecting means. Output signal control means for controlling the output signal before the regular output signal is output according to the change detection signal,
Second input change detecting means for detecting a change in the input signal,
An internal operation control means for controlling the internal operation before the output section is included in accordance with the second input change detection signal output from the second input change detection means.

[0064]

In the present invention, the output signal control means reduces the generation of power supply noise, and the internal operation control means improves the resistance to power supply noise.

[0065]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 5 by taking the case where the present invention is applied to an EPROM as an example.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. This embodiment is an improvement of the EPROM shown in FIG. Therefore, in FIG. 1, parts corresponding to those in FIG. 17 are denoted by the same reference numerals, and duplicate description thereof will be omitted.

The present embodiment is different from the EPROM of FIG. 17 in that a noise filter 105, an ATD circuit 106 and an output preset circuit 107 are provided, and a high impedance control signal ZP output from the ATD circuit 106 is supplied to the output buffer 29. At the same time, the output signal pad 32 is connected to the output preset circuit 107, and the other points are configured similarly to the EPROM shown in FIG.

Here, the noise filter 105 is composed of a CR delay circuit, and is constructed as shown in the circuit diagram of FIG. In the figure, 108 and 109 are inverters, 110 and 111 are resistors, 112 is a capacitance, and AF is the output of this noise filter 105.

The noise filter 105 detects the fluctuation of the internal address signal a ₀ due to the power supply noise and the ATD circuit 106.
To prevent the output preset circuit 107 from operating.

Further, as shown in the circuit diagram of FIG. 3, the ATD circuit 106 detects a change in the address signal A ₀ from the output AF of the noise filter 105, and internally detects the ATD.
The pulse AFP is generated, and the high impedance control signal ZP supplied to the output buffer 29 and the output preset signal DP supplied to the output preset circuit 107 are output to the outside.

Incidentally, 113 is an exclusive OR circuit, 11
Reference numerals 4 and 115 are delay circuits, 116 is a NOR circuit, and 117 is an inverter. Here, in particular, 115 is a CR type delay circuit, 118 and 119 are inverters, 120 is a resistor, 121 is a capacitor, and Z is a high impedance control signal based on the logic of an input signal for normal output control as described above. Is.

Further, the output preset circuit 107 gradually sets the output signal DO to 0 [V] when the output preset signal DP is set to "H", and the EPR of FIG.
The output preset circuit 31 provided in the OM is configured as shown in FIG.

FIG. 4 is a time chart showing the operation of the EPROM of this embodiment. In this embodiment, for example, when the address signal A ₀ changes, the ATD circuit 87 detects it and internally, the ATD detection signal A 0 is detected.
P is generated, and based on this, precharge
The pulse PC and the latch pulse LP are set to “H”.

Here, when the precharge pulse PC is set to "H", the bus line BUS of the cell array 27 is precharged via the sense amplifier 28, and the word lines X ₀ and X ₁ are selected and non-selected. Selection and selection / non-selection of the gate lines Y ₀ and Y ₁ are performed. After that, the precharge pulse PC returns to “L”, and the sense amplifier 28 outputs the sense-out SO.

On the other hand, in the data latch circuit 86,
By setting the latch pulse LP to "H", the data of the previous cycle is held. Then, after the sense-out SO is determined, the latch pulse LP is set to “L”, and the sense-out SO is transmitted to the output buffer 29.

In this case, the fluctuation of the internal address signal a ₀ due to the power supply noise is canceled by the noise filter 105 and is not transmitted to the ATD circuit 106. Therefore, as a result, the ATD circuit 106 sets the high impedance control signal ZP and the output preset signal DP to "H".
Not.

Therefore, in the present embodiment, a voltage change occurs in the pad 36 due to the change of the output signal DO from "L" to "H", and the address signal A input to the pad 24 in the address buffer 25 is generated. ₀ appears to fluctuate as shown in FIG. 4x, and the address signal A ₀
Erroneous output does not occur even if is read as changed.

That is, in this case, the reading is performed again, but first, the data before the address signal changes,
That is, reading is performed after the normal data is latched by the data latch circuit 86. Then, when the sense-out SO of the sense amplifier 28 is determined, noise has subsided, and this sense-out SO should have the same data (normal data) as in the previous cycle, so the output does not change at all. , No erroneous output occurs.

If the Vcc noise continues for a long time, the precharge pulse PC and the latch pulse LP are automatically lengthened, so that there is no problem. That is, the time when the precharge pulse PC and the latch pulse LP return to "L" is based on the time when the change of the address signal A ₀ ends.

On the other hand, when the address signal A ₀ input to the pad 23 changes, that is, when the address signal A ₀ changes normally, this change is transmitted to the ATD circuit 106 via the noise filter 105. Here, the ATD circuit 106 sets the high impedance control signal ZP and the output preset signal DP to "H".

Here, the high impedance control signal ZP
Is set to "H", the output buffer 29 is in a high impedance state, and the connection with the pad 32 is electrically disconnected.

When the output preset signal DP is set to "H" and the output signal DO is "H",
The output preset circuit 107 gradually sets the output signal DO to "L".

That is, in the present embodiment, when the address signal changes, it is taken in and the output signal D
O is gradually set to "L", and then the regular data from the address designated by the address signal is read.

Therefore, when the output signal DO changes from "L" to "H", the voltage of the pad 36 for the Vcc power source fluctuates, but the output signal DO changes from "H" to "L". When changing, the voltage of the pad 41 for the Vss power supply does not change.

According to this embodiment, the ATD circuit 87 is used.
With the data latch circuit 86, the resistance to the power supply noise can be increased, and the noise filter 105,
The generation of Vss noise can be suppressed by the ATD circuit 106 and the output preset circuit 107. Therefore, malfunction due to noise can be prevented and its reliability can be improved.

In the above-mentioned embodiment, the output preset signal DP is detected by detecting the change of the address signal.
Is set to "H" and the output signal DO is gradually lowered to "L". Alternatively, the output signal DO may be gradually raised to "H". In this case, Vcc is set. Noise can be suppressed.

If the output preset circuit whose circuit diagram is shown in FIG. 5 is used, the level of the output signal DO becomes "H".
Can be in the middle between "L" and Vcc noise and Vss
Both of noise can be reduced. 122-
Reference numeral 124 is an inverter, 125 is a NAND circuit, 126 is a NOR circuit, 127 is a pMOS, and 128 is an nMOS.

Further, in the above embodiment, the case where the present invention is applied to the EPROM has been described.
The present invention can be applied to various semiconductor integrated circuits having an output buffer.

[0089]

According to the present invention, the first input change detecting means for detecting a change in the input signal and the normal input change detecting signal outputted by the first input change detecting means Output signal control means for controlling the output signal before the output signal is output, a second input change detection means for detecting a change in the input signal, and a second input change detection means for outputting the second input change detection means. By including the internal operation control means for controlling the internal operation before the output section according to the input change detection signal, the output signal control means can reduce the generation of noise and control the internal operation. By the means, it is possible to enhance resistance to noise, thereby preventing malfunction due to noise and improving reliability.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a noise filter that constitutes an embodiment of the present invention.

FIG. 3 is a circuit diagram of an ATD circuit that constitutes an embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the embodiment of the present invention.

FIG. 5 is a circuit diagram of another example of the output preset circuit.

FIG. 6 is a circuit diagram showing a main part of an example of a conventional semiconductor integrated circuit.

FIG. 7 is a circuit diagram showing a main part of an example of a conventional EPROM.

8 is a circuit diagram of an address buffer forming the EPROM of FIG.

9 is a circuit diagram of a decoder forming the EPROM of FIG. 7. FIG.

10 is a circuit diagram of a cell array forming the EPROM of FIG.

11 is a circuit diagram of a sense amplifier forming the EPROM of FIG.

12 is a circuit diagram of an output buffer included in the EPROM of FIG.

13 is a circuit diagram of an ATD circuit forming the EPROM of FIG.

FIG. 14 is a circuit diagram of an output preset circuit that constitutes the EPROM of FIG.

FIG. 15 is a time chart showing the operation of the EPROM shown in FIG. 7.

16 is a time chart showing a problem that the EPROM of FIG. 7 has.

FIG. 17 is a circuit diagram showing a main part of another example of a conventional EPROM.

18 is a circuit diagram of a data latch circuit that constitutes the EPROM shown in FIG.

19 is a circuit diagram of an ATD circuit forming the EPROM shown in FIG.

20 is a time chart showing the operation of the EPROM of FIG.

[Explanation of symbols]

 23 External terminal for inputting address signal 24 Pad for inputting address signal 32 Pad for output signal 33 External terminal for output signal 35 External terminal for Vcc power supply 36 Pad for Vcc power supply 40 Vss External terminal for power supply 41 Vss Power pad

Claims (3)

[Claims] 1. A first input change detecting means for detecting a normal change of an input signal, and a normal output signal according to the first input change detecting signal output from the first input change detecting means. Output signal control means for controlling an output signal before being output, second input change detection means for detecting a change in the input signal, and second input change detection output by the second input change detection means. A semiconductor integrated circuit, comprising: an internal operation control means for controlling an internal operation before an output section in accordance with a signal. 2. The semiconductor integrated circuit according to claim 1, wherein the output signal control means controls the state of the output signal before a normal output signal is output to a low level or a high level. 3. The semiconductor integrated circuit according to claim 1, wherein the output signal control means controls the state of the output signal before the output of the regular output signal to an intermediate level between a high level and a low level. circuit.