JPH0581877A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To provide a differential amplifier circuit capable of adjusting gain after manufacturing an LSI by providing a transistor for adjusting the gain between two pairs of an input differential transistor and constant power source. CONSTITUTION:The differential amplifier circuit is constituted by connecting two differential input parts having the input differential transistors M1, M2 and active load MOSFET M3, M4 in parallel and making constant current source CCO common. Then, between two pairs of the input differential transistors M1, M2 and the constant current source CCO, the transistors M9, M10 for adjusting the gain operating complementally respectively are provided. A bias current is changed by controlling the gate voltages G1, G2 of the transistors M9, M10 and simultaneously the bias point, as well of a load resistance is changed and the gain of the differential amplifier circuit is adjusted over wide range by applying control voltage to the gates from the outside even after manufacturing the LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology and a technology particularly effective when applied to a differential amplifier circuit.
For example, the present invention relates to an effective technology used when setting an absolute gain or requiring an automatic gain adjustment function.

[0002]

2. Description of the Related Art Conventionally, for example, a circuit as shown in FIG. 2 may be used as a differential amplifier circuit for amplifying a differential input signal and outputting it as a differential signal. In this differential amplifier circuit, an ordinary differential amplifier is connected in parallel and a constant current source CC0 is connected.
Is used in common and a high-gain differential output can be obtained. The differential amplifier circuit as described above is disclosed in, for example, Japanese Patent Publication No. 2-5999.
It is used as a sense amplifier that amplifies a read signal from a memory cell as described in Japanese Patent Publication No.

[0003]

However, the differential amplifier circuit described above is effective for a circuit in which the gain is desired to be higher than a certain level, but the gain tends to fluctuate due to variations in the manufacturing of elements, and therefore, it is desirable. There is a problem that it is unsuitable for use when it is difficult to design the circuit for obtaining the gain of, and it is desired to limit the gain.

The present invention has been made in view of the above problems, and an object thereof is to provide a differential output differential amplifier circuit capable of adjusting a gain after manufacturing an LSI. To do. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the input differential transistor and the load M
In a differential amplifier circuit in which two differential input sections having OSFETs are connected in parallel and a constant current source is commonly used, they operate complementarily between two input differential transistor pairs and a constant current source. A transistor for gain adjustment is provided. In addition, one of the load MOSFETs is diode-connected, and the drains of the diode-connected load MOSFETs are commonly connected so that the drain voltage is applied to the gate terminals of the other load MOSFETs.

[0006]

The larger the bias current and the larger the value of the load resistance, the larger the gain of the differential amplifier circuit can be made. However, according to the above means, the two input differential transistor pairs and the constant current are connected. The bias current can be changed by controlling the gate voltage of the gain adjusting transistor respectively connected to the source and the source, so that the gain can be widened by externally applying the control voltage even after the LSI is manufactured. The purpose of being adjustable over a range is achieved. Further, according to the above means, the value of the load resistance (bias point) can be changed by the change of the bias current, and the gain can be adjusted over a wider range.

[0007]

FIG. 1 shows an embodiment of a differential amplifier circuit according to the present invention. In the differential amplifier circuit of this embodiment, two differential input sections each having an input differential transistor and an active load MOSFET are connected in parallel, a constant current source is shared, and two input differential transistor pairs and a constant current are provided. A gain adjusting transistor that operates in a complementary manner is provided between the source and the source.

That is, the MOSFETs M5 and M6 form an input differential transistor pair of one differential input section, and
The MOSFETs 7 and M8 form an input differential transistor pair of the other differential input section. Further, M1 and M2 are active load MOSFETs connected to the drain terminals of the transistors M7 and M8, and M3 and M4 are active load MOSFETs connected to the drain terminals of the transistors M5 and M6.

In FIG. 1, among the transistor symbols of MOSFETs, the ones with arrows are P-channel MOSFETs, and those without arrows are N.
It is a channel MOSFET. That is, the transistors M1 to M4 are P-channel MOSFETs, and the transistors M5 to M8 are N-channel MOSFETs.

In this embodiment, a gain adjusting MOSFET M9 is provided between the source terminals of the input differential transistor pair M5 and M6 and the constant current source CC0, and the source terminal of the input differential transistor pair M7 and M8. And constant current source CC
A MOSFET M10 for gain adjustment is connected between 0 and each. And these MOSFET M9
Gain control DC voltages G1 and G2 are applied to the gate terminals of M10 and M10, respectively. The gain adjusting DC voltages G1 and G2 may be given from the outside, but a low pass filter or the like is provided in the next stage of the differential amplifier circuit and the output thereof is used as the gain adjusting DC voltages G1 and G2. By feeding back to the dynamic amplifier circuit, it is possible to configure an amplifier that outputs a voltage of a substantially constant level regardless of the level of the input voltage.

Further, in this embodiment, the load MOS is
Of the FETs M1 to M4, both M1 and M2 are gates
A so-called diode connection in which the drains are short-circuited is formed, and the drain voltage is applied to its gate terminal and also to the gate terminals of the other load MOSFETs M3 and M4. Moreover, in this embodiment, the input differential transistor pair M7 is used.
And M8 and load MOSFET M1 with diode connection
And M2 are commonly connected to the drains. The MOSFETs M1 and M2 can be replaced with one MOSFET.

Next, the operation of the differential amplifier circuit of this embodiment will be described. Now, MOSFETs M9 and M10 for gain adjustment
It is assumed that the DC voltages G1 and G2 applied to the gate terminals of are equalized (G1 = G2 = V ₀ ), and that M9 and M10 are similarly turned on. Then, the current flowing through the MOSFET M9 and M10 is equal I _0/2. At this time, the gain of the differential amplifier circuit becomes the same as the gain of the circuit shown in FIG.

Next, the gain adjusting DC voltage G1 is set to V ₀ + Δ.
It is assumed that V is set to V and G2 is set to V ₀ −ΔV. Then, the current flowing through the MOSFET M9 increases and M10
The current flowing through it decreases. As a result, the bias current of the differential input section composed of the input differential transistor pair M5 and M6 increases, and the gain is increased.

Moreover, when the current flowing through the MOSFET M10 decreases, the current flowing through the load MOSFETs M1 and M2 also decreases, so that the drain voltage of them and the gate voltages of the load MOSFETs M3 and M4 approach the power supply voltage Vcc. As a result, the load MOSFE
The impedance of T M3 and M4 becomes high. As a result, the MOSFE viewed from the output terminals OUT1 and OUT2 side
The gains of T M3 and M4 have increased, and the bias current of the differential input section composed of the input differential transistor pair M5 and M6 has increased to increase the gain. The higher the gain.

On the other hand, contrary to the above, it is assumed that the gain adjusting DC voltage G1 is set to V ₀ -ΔV and G2 is set to V ₀ + ΔV. Then, the current flowing through MOSFET M9 decreases and the current flowing through M10 increases. As a result, the bias current of the differential input section composed of the input differential transistor pair M5 and M6 is reduced and the gain is lowered. Then, when the current flowing through the MOSFET M10 increases,
Since the current flowing through the load MOSFETs M1 and M2 is increased, the bias point of the gate voltage of the load MOSFETs M3 and M4 is lowered and the load MOSFET M3 and
The M4 impedance is low. As a result, the MOSFETs M3, M seen from the output terminals OUT1, OUT2 side
4 becomes smaller, and the gain of the differential amplifier circuit becomes lower.

In the above embodiment, the gain adjusting transistors M9 and M10 are MOSFETs, but they may be bipolar transistors. Further, in the above embodiment, the gain adjustment MO is provided between the two differential input sections and the constant current source CC0.
Although the SFETs M9 and M10 are provided, it is possible to use only one of them.

As described above, in the above-described embodiment, two differential input circuits each having an input differential transistor and a load MOSFET are connected in parallel and a constant current source is commonly used. Since a gain adjusting transistor that operates in a complementary manner is provided between the input differential transistor pair and the constant current source, the bias current is changed by controlling the gate voltage of the gain adjusting transistor. Therefore, it is possible to adjust the gain by applying a signal from the outside even after the LSI is manufactured.

One of the load MOSFETs is diode-connected and the diode-connected MO is connected.
Since the drains of the SFETs are commonly connected and the drain voltage is applied to the gate terminals of other load MOSFETs, the value of the load resistance (bias point) can also be changed by changing the bias current, and a wider range is possible. The gain can be adjusted over the range.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the input differential transistor pair M7 and M8 is provided on the drain side of the MOSFET M10. However, the input differential transistor pair M7 and M8 is a MOSFET.
Vertically stacked MOSFETs on the drain terminal side of M9 and M10
It is inserted to match the numbers and to match the levels, and can be omitted.

Further, in the above embodiment, the drain voltages of the diode-connected MOSFETs M1 and M2 are applied to their gate terminals and other load MOSFEs are used.
The gate terminals of TM3 and M4 are also configured to be applied so that when the bias current is changed, the bias point of the load MOSFET is also changed. With respect to the load MOSFETs M1 to M4, It is also possible to make a connection similar to that of the conventional circuit (FIG. 2).

In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor integrated circuit which is the field of application of the background has been described, but the present invention is not limited thereto and the hybrid IC. It can also be used for etc.

[0022]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, even after the LSI is manufactured, the gain of the differential amplifier circuit can be adjusted over a wide range by applying a control voltage from the outside.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a differential amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional differential amplifier circuit.

[Explanation of symbols]

 M1, M2 Input differential transistor M3, M4 Load MOSFET CC0 Constant current source M9, M10 Gain adjustment transistor

Claims (2)

[Claims] 1. A difference in which two differential input sections each having two sets of input differential transistors and a load MOSFET connected to the drain terminal of each transistor are connected in parallel and their constant current sources are shared. In the dynamic amplification circuit, a gain adjustment transistor is provided at least between the one input differential transistor pair and the constant current source. 2. One of the load MOSFETs is diode-connected and the diode-connected load MO.
2. The differential amplifier circuit according to claim 1, wherein the drains of the SFETs are commonly connected and the drain voltage is applied to the gate terminals of the other load MOSFETs.