JPH0581221A - Device for supporting parallel program development - Google Patents

Abstract

PURPOSE:To support program developing work such as load distribution algorithm performance evaluation and debugging on parallel machines so as to easily execute it by collecting procedure information executed on the parallel machines and displaying the collected information correspondingly to respective processors so as to easily identify it. CONSTITUTION:This supporting device is provided with plural processors for operating parallel programs and an operation extracting part 2 for extracting and collecting procedure information 71 and operation information 8 for the parallel programs driven by these processors and constituted so as to display a procedure corresponding to each processor based upon both information 7, 8 collected in each processor through a series of processing by the extracting part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel program development supporting apparatus for collecting procedure information at the time of execution of a parallel program and displaying it in association with each processor. The present invention relates to a parallel program development support device that supports test, evaluation, and analysis of programs on the Internet.

Generally, program development on a parallel computer is carried out in the process of designing, programming, testing / evaluating / debugging a calculation load distribution algorithm. The design of distributed algorithm of calculation load is aimed at executing the program efficiently on the parallel computer.
It is important to distribute the calculation load while suppressing the communication volume between processors. For this reason, various dynamic load balancing schemes have been considered in which a computing load is automatically assigned to each processor, but these schemes have not yet been able to efficiently execute all programs.

Also, in testing, evaluation, and debugging, not only debugging that is not normally executed unlike sequential programs, but evaluation and debugging for dramatically improving calculation speed must be performed. I have to
The programming environment to support these has not been established. Therefore, under the present circumstances, programmers are designing and evaluating load balancing algorithms while repeating thought and error. Therefore, it is necessary to support these series of operations in order to reduce the load on the programmer.

[0004]

2. Description of the Related Art Executing a program on a parallel computer is more difficult than executing a computer with a single processor.
It is expected that the calculation speed will increase in proportion to the number of vehicles. In order to realize the improvement of the calculation speed according to the number of processors, it is necessary to efficiently execute a program on a plurality of processors at the same time. For this purpose, it is necessary to consider a method of dividing the calculation problem of the program into sub-problems and a method of allocating the divided sub-problems to each processor. In consideration of the partitioning method, it is important to partition the problem into units that can be calculated independently to some extent so that interprocessor communication does not increase by distributing the calculation load. Moreover, in the study of the allocation method, it is important to allocate the load evenly to each processor so that the calculation load is not concentrated on a specific processor. From these examination results, it is necessary to create the program while predicting the behavior of the goal on each processor in advance when implementing the load balancing algorithm. However, at present, it is difficult to predict the performance of programs running in parallel, so programmers are designing load balancing algorithms by repeating thought and error.

[0005]

Therefore, the programmer must repeat thought and error in designing a load balancing algorithm for efficiently executing a program on a parallel machine and in debugging for a correct operation. , There was a problem that there were insufficient tools to support efficient parallel program creation.

The present invention collects procedure information when it is executed on a parallel machine and displays it in association with each processor so that it can be easily understood, and program development such as performance evaluation and debugging of a load balancing algorithm on the parallel machine. The purpose is to support the work and make it easier.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, a plurality of processors operate parallel programs.

The operation extracting section 2 extracts and collects procedure information 71 and operation information 8 of a parallel program operated on a plurality of processors. The procedure management table 7 manages the number of executions of each procedure and provides a flag for managing display / non-display of the procedure.

The correspondence table 72 is for registering the correspondence between the procedure and the variable (for example, shared variable) designated in advance in the procedure information 71 and the movement information 8 extracted by the movement extracting section 2.

[0010]

As shown in FIG. 1, the present invention operates a parallel program on a plurality of processors, and based on the procedure information 71 and the operation information 8 for each processor collected by the operation extraction unit 2 for a series of processes. , The procedure is displayed in association with each processor.

Also, the parallel program is run on a plurality of processors, and the procedure extracting unit 2 collects the procedure information 7 for each processor in real time for a series of processes.
Based on 1 and operation information 8, the procedure is displayed in real time in association with each processor.

Further, the parallel program is operated on a plurality of processors, the procedure information 71 and the operation information 8 collected by the operation extraction unit 2 for a series of processes are stored, and the procedure information 71 and the operation information 8 are also stored. In addition, the moving images are sequentially displayed as time passes (or in the opposite direction).

In addition, the parallel program is operated on a plurality of processors, and the number of executions of each procedure is calculated based on the procedure information 71 and the operation information 8 collected by the operation extraction unit 2 for a series of processes, and the procedure management table 7
The procedure is displayed for each processor in a color corresponding to the number of executions managed by the procedure management table 7.

Further, a parallel program is operated on a plurality of processors, and a procedure and a variable (shared variable) designated in advance based on the procedure information 71 and the operation information 8 collected by the operation extracting unit 2 for a series of processes are stored. Is registered in the correspondence table 72, and the procedure in which the same variable as the variable of the designated procedure registered in the correspondence table 72 is registered is highlighted in association with each processor.

Further, the parallel program is operated on a plurality of processors, and the procedure display / non-display flag is set based on the procedure information 71 and the operation information 8 collected by the operation extraction unit 2 for a series of processing. Only the procedure with the flag set in the procedure management table 7 is displayed in association with each processor.

Therefore, by collecting the procedure information 71 and the operation information 8 when they are executed on the parallel machine and displaying them as a processor configuration diagram in association with each processor in an easy-to-understand manner, the load balancing algorithm on the parallel machine can be displayed. It becomes possible to support the program development work such as performance evaluation and debugging, and to make it easier.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a principle configuration diagram (1) of the present invention. In FIG. 1, the input device 1 loads a parallel program into the processor of PE # 0 to PE # 3 of the operation extraction unit 2, inputs various commands, and gives instructions.
Various inputs are performed.

The motion extraction unit 2 executes a parallel program for each PE.
The procedure information 71 and the operation information 8 at that time are loaded from # 0 to PE # 3 and executed, and the PE # 0 to PE # 3 and the extraction / collection unit 2 are collected.
1 and the like.

PE # 0 to PE # 3 are processors, which load a parallel program and execute the programs in parallel. The extraction / collection unit 21 uses PE # 0 to P #
The procedure information 71 and the operation information 8 when the parallel programs are executed in parallel by E # 3 are extracted and collected. Where the procedure is
A function, a subroutine, or a process with a line unit of a program is performed, and a procedure ID is assigned to each of them. The procedure information 71 collects the procedure name, the number of arguments, etc., counts the number having the same procedure ID as the number of executions, and stores it in the data file 3 on the disk device. In addition, the procedure information 71 is associated with the procedure ID, and the procedure calling sequence and the processor number at that time are collected as the operation information 8 to obtain the data file 3
Save to.

The data file 3 is extracted from PE # 0 to PE # 3 by the extraction / collection unit 21 and the procedure information 71 obtained by counting the number of times of execution of the same procedure ID is recorded.
Is registered and stored in the procedure management table 7, and the operation information 8 is also stored in association with the procedure ID.

The display 6 displays a processor block diagram and the like. The correspondence table 72 is for registering variables to be used in association with the procedure Id.

Next, the operation of the configuration of FIG. 1 will be described in detail according to the order shown in the flow chart of FIG. In (a) of FIG. 2, in S1, PE # 0 executes and allocates the procedure ID. In this case, PE # 0 loaded with the parallel program executes the parallel program and assigns a unique procedure ID to the procedure. For example, a unique procedure ID is assigned to a procedure (function, subroutine, etc.) of a parallel program.

In step S2, the procedure information and the operation information are stored in the own memory. This is to store the procedure name (eg, module name, procedure name, etc.) and the number of arguments as procedure information in association with the procedure ID assigned in S1, and call sequence (eg, procedure ID0 to procedure ID1 called as operation information). Saved) ((b) in Figure 2,
(See (c)).

In step S3, it is determined whether or not a series of processes has been completed. If YES, the process proceeds to S4. On the other hand, in the case of NO, S1 and S2 are repeated, and the procedure information and the operation information at the time of execution of the parallel program are stored in the own memory in association with the procedure ID.

Similarly, with respect to PE # 1, PE # 2, and PE # 3, the procedure information and the operation information at the time of execution of the parallel program are stored in the own memory in association with the procedure ID.

In step S4, each PE stores the procedure information and operation information in its own memory in association with the unique procedure ID in step S3.
0 data transfer to memory pool 9
Once stored in. At this time, when the same procedure ID exists, the number of times is incremented, and the procedure information after the second time is not stored in the data pool 9.

In step S5, the procedure information 71 and the operation information 8 which have been counted and stored in the data pool 9 in step S4 are saved in the data file 3 on the disk device. These S4 and S5 are performed by the extraction / collection unit 21 of FIG.

As described above, each of PE # 0 to PE # 3 stores in its own memory in association with the unique procedure ID assigned to the procedure when the parallel program is executed,
After the series of processing is completed, the main step is to transfer data to PE # 0, count the processor with the same procedure ID for each processor, and set the number of executions so that the procedure information 71 and the operation information 8 are shown without duplication. 2 (b),
As shown in (c), the data file 3 is stored in the disk device. Thereby, for example, the operation of the program in the program development process can be saved as a history, and the operation can be compared at the time of program development.

FIG. 2B shows an example of the procedure management table 7. This is for each PE in S4 of (a) of FIG.
The procedure information collected from # 0 to PE # 3 is stored. For the procedure information having the same procedure ID, the execution count is incremented by 1 to prevent duplicate storage. Here, the procedure ID is each PE
It is an identifier uniquely assigned from # 0 to PE # 3, and is associated with the procedure ID, and is the procedure module name, procedure name, the number of arguments, the number of times the procedure is executed, and the procedure is displayed or hidden. It is composed of a flag for setting or.

FIG. 2C shows an example of the motion information 8.
Here, as the calling sequence, for example, ID, [ID1, ID2] ... (1) are collected. This (1) is as shown on the right side when it is expressed as an execution tree. From procedure ID to procedure ID
1 and operation ID 2 represent operation information indicating that two are called as illustrated.

FIG. 3 shows a principle configuration diagram of the present invention (No. 2). Here, the input device 1, the motion extraction unit 2, and the data file 3 are the same as those in FIG.

In FIG. 3A, the operation display unit 4 is
The procedure information 71 and the operation information 8 collected and stored in the data file 3 as described with reference to FIGS. 1 and 2 are taken out, and PE # 0 to P
For each E # 3, the operating state of the procedure is easy to understand, and as a processor configuration diagram, for example, the display 5 as shown in FIG.
The one shown above.

The system controller 6 controls the display of the processor block diagram on the display 5. Figure 3
(B) indicates a configuration diagram of the motion extraction unit.

In FIG. 3B, PE # 0 to PE #
# 3 is a target processor for collecting procedure information and operation information during execution of the parallel program. me
The rger collects procedure information and operation information from PE # 0 to PE # 3 (see the flowchart of FIG. 2).

The extraction / collection unit 21 stores the procedure information and the operation information collected from each PE # 0 to PE # 3 by the merger in the data pool 9 (see the flowchart of FIG. 2).

The data file 3 is a file provided on a disk for storing the procedure information and operation information stored in the data pool 9. The interrupt instruction is an interrupt instruction from the input device 1 to the PE # 0 to PE # 3 executing the parallel program, and is for notifying the extraction / collection unit 21 of a message to abandon the execution. Is. Also, when an error occurs during program execution, a message to abandon the execution is similarly notified. Upon receiving the message notification, the extraction / collection unit 21 stops the execution of the program, collects the operation information up to the present time, and saves it in the data file 3. Therefore, even if the execution is interrupted by a deadlock, the execution does not end due to an infinite loop, or the execution fails due to an error, the procedure information and the operation information are collected and stored in the data file 3. It becomes possible.

The history records 1, 2, and 3 represent the procedure information 71 and the operation information 8 collected in association with the procedure ID described above. FIG. 4 shows a block diagram of an embodiment of the present invention.

In FIG. 4, the operation display unit 4 displays the procedure management table 7 and the operation information 8 for managing the procedure information 71 collected and stored in the data file 3 as described with reference to FIGS. 1 and 2. Take out the corresponding procedure ID based on the operation information 8
The procedure management table 7 is referred to for the procedure information 71 having "", and the operating state of the procedure is displayed on the display 5 as a processor block diagram for each PE # 0 to PE # 3 in an easily understandable manner. .. Here, the procedure management table 7 may be the one created and stored at the time of collecting the procedure information and the operation information according to the flowchart of FIG. When the procedure ID is the same, the number of executions may be increased by +1 to create it at this stage.

The procedure management table 7 sets Name (procedure name, eg, module name, procedure name, etc.), the number of executions, the number of arguments, etc. in association with the procedure ID.

The operation information 8 is a procedure calling sequence or the like, and is as shown in FIG. The display 5 displays a processor block diagram, and displays the processor block diagram as shown in FIG. 5, for example.

FIG. 5 shows a display example of the execution process of the program on the processor block diagram of the present invention. In this figure, □ represents the operating state of the procedure for the eight processors PE # 0 to PE # 7. For example, the processor PE # 0 has four procedures in operation. Processors PE # 1 and PE # 7
Has zero active procedures.

Next, the operation of the configuration of FIG. 4 will be described in detail with reference to the flowcharts of FIGS. 6 to 8. FIG. 6 shows a flowchart of the identification display by color-coding the graphics for each procedure of the present invention.

In FIG. 6, step S11 collects procedure information. It collects procedure information from each PE # 0 to PE # 3. In step S12, it is determined whether the procedure information is registered in the procedure management table 7. If YES, the number of executions is counted up (count = count + 1) in S14, and S15
If the execution is not completed in step S15 (NO in S15), step S12 is repeated. If the execution is completed in step S15 (NO in step S15), the process proceeds to step S16. On the other hand, in the case of NO in S12, the procedure information is registered in the procedure management table 7 in S13 (number of executions: count = 0), and if execution is not completed in S15 (NO in S15), S12 is repeated and S15 is executed. If the execution is completed (NO in S15), the process proceeds to S16.

In step S16, colors are assigned in descending order of the number of executions. This is, for example, in the descending order of the number of executions in the procedure management table 7 in FIG.
Assign dark colors in the order 1, 2, 3.

In step S17, the procedure is displayed in the color assigned in step S16. For example, as shown in (a) of FIG. 10, a procedure with a large number of executions is displayed in a dark color, and is displayed so that each processor PE # 0 to PE # 7 can easily find it.

As described above, the higher the number of executions of a procedure, the darker it is displayed as shown in (a) of FIG. 10, and the procedure having a large number of executions can be easily determined.
As a result, it becomes possible to easily inform the programmer which procedure is running on which PE and which procedure is the bottleneck due to the large number of executions.

FIG. 7 shows a flow chart of the real-time identification display of a procedure having a shared variable according to the present invention.
In FIG. 7A, S21 collects procedure information. This is for each PE # 0 to P in real time.
The procedure information (and operation information) is collected from E # 7 (see the flowchart of FIG. 2).

In step S22, the procedure information and the variable are registered and deleted from the correspondence table. This is the real-time procedure information collected in S21 as shown in FIG.
As shown in (b), the variables such as variables X and Y are registered in association with the procedure Id as illustrated.

In step S23, the graphic representing the procedure is displayed and deleted. This reduces the amount of procedure information that explosively increases by registering the procedure information that has been collected and deleting the procedure information that has been deleted.

In step S24, it is determined whether or not there is a user designation of execution interruption. If YES, the process proceeds to S25. N
In the case of O, S21 is repeated. In S25, in response to the input of the identification display command, the correspondence table 72 is referred to, and the procedure having the designated procedure and the shared variable is searched. This is done by referring to the correspondence table 72 in (b) of FIG. 7 and referring to, for example, the specified procedure Id.
Search for and find another procedure Id2 with 1 and a shared variable, here the variable Y.

In step S26, the retrieved procedure is highlighted. This highlights other procedures that share variables with the procedure designated by the arrow, such as the "designated procedure" in (b) of FIG. 10 (here, highlighted with the same concentration).

As described above, the correspondence between the procedure Id and the variable is registered in the correspondence table 72 while collecting the procedure information and the operation information in real time, and the variable on the processor block diagram is shared in response to the execution interruption instruction. By highlighting the procedure to be executed, it becomes possible to identify the procedure having the shared variable and to easily debug the parallel program, especially to detect the deadlock bug due to the typo of the variable.

FIG. 7B shows an example of the correspondence table 72. The correspondence table 72 is for registering variables as illustrated in association with the procedure Id. And
At the time of display, another procedure Id having the same variable as the designated procedure Id is searched and found, and these are highlighted.

FIG. 8 shows a display flowchart focusing on a certain procedure of the present invention. In FIG. 8, S31
Registers the procedure information in the procedure management table. For example, the collected procedure information is registered in the procedure management table 7 of FIG.

In step S32, it is determined whether or not the user has designated a procedure of interest. In the case of YES, the display flag of the procedure Id designated in the procedure management table 7 is set to 1 in S33. For example, in FIG.
The display / non-display flag of the procedure Id1 in the procedure management table 7 is set to 1. Then, the process proceeds to S32.

In step S34, the operation information is sent out. S35
Refers to the procedure management table 7. S36
Determines whether the flag of the procedure Id is 1 by referring to S35. If YES, S3
The display is made at 7, and S34 is repeated. On the other hand, S36
In the case of NO at S34, S34 is repeated without displaying.

As described above, as shown in (c) of FIG. 10, only the procedure in which the flag (display / non-display flag) is set to 1 can be displayed. As a result, when displaying the execution process of the program on the processor block diagram, only the procedure of interest can be displayed, and information such as how much the procedure is moving can be displayed in an easy-to-understand manner.

FIG. 9 shows a display example (1) of the present invention. FIG. 9A shows a display example of a graphic representing the processor by the initial state creation command. This is 8 × 4 =
An example in which a rectangular area corresponding to 32 processors is displayed on the display 5 is shown. A procedure described later is displayed in each rectangular area.

FIG. 9B shows a display example in which an element is added to the rearmost part in the figure representing the processor. In the figure, the procedures or data that are called are represented by rectangles indicated by arrows. Here, in response to the input of the procedure start state command call, the PE on the left side
As shown in # 0, one rectangle representing a procedure or data is added at the end. If one is added at the right end as shown in PE # 0 on the right side, a graphic is displayed at the beginning of the next line.

FIG. 9C shows a display example in which an element is deleted from the inside of the graphic representing the processor. This corresponds to the input of the procedure end command,
One procedure is deleted from PE # 0 on the left side of the figure to bring it to the central state, and the figure at the back is packed and displayed at this deleted position.

FIG. 9D shows a display example in which elements move between figures representing a processor. This is the left (A)
In response to the input of the procedure distribution command in this state, as shown in (B), the PE # 0 designated as the movement destination draws a locus and the PE # designated as the movement destination is drawn.
Move to the first position of 1. Then, as shown in (C), the graphic of the movement source is shifted to the left side and is displayed together.

FIG. 10 shows a display example (2) of the present invention. FIG. 10A shows an example of display by color coding for each procedure. This shows an example in which, in accordance with the flowchart of FIG. 6, a procedure that has been executed many times is displayed in a dark color in a rectangular area of the processor on the processor configuration diagram.

FIG. 10B shows a display example of a procedure having a shared variable. This shows an example in which a procedure having the same variable as the designated procedure is highlighted in the rectangular area of the processor on the processor block diagram according to the flowchart of FIG. 7.

FIG. 10C shows a display example focusing on a certain procedure. This shows an example in which only the same procedure as the designated procedure is displayed in the rectangular area of the processor on the processor block diagram according to the flowchart of FIG.

[0066]

As described above, according to the present invention,
Procedure information 71 when executed on a parallel machine
And the operation information 8 are collected and displayed in a processor configuration diagram that is easy to understand by associating with each processor, supporting the program development work such as performance evaluation and debugging of load balancing algorithms on parallel machines. It can be done easily. In particular, it is effective in finding a place that causes a program with inefficient calculation speed or a place that causes a bug peculiar to a parallel program such as deadlock or infinite loop, and is very useful for supporting the program development work.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram (1) of the present invention.

FIG. 2 is a flowchart for collecting procedure information / operation information according to the present invention.

FIG. 3 is a principle configuration diagram (2) of the present invention.

FIG. 4 is a configuration diagram of an embodiment of the present invention.

FIG. 5 is a display example of an execution process of a program on the processor block diagram of the present invention.

FIG. 6 is a flowchart of identification display by color-coding graphics for each procedure of the present invention.

FIG. 7 is a flowchart of real-time identification display of a procedure having a shared variable according to the present invention.

FIG. 8 is a display flowchart focusing on a certain procedure of the present invention.

FIG. 9 is a display example (1) of the present invention.

FIG. 10 is a display example (2) of the present invention.

[Explanation of symbols]

 1: Input device 2: Action extraction unit 21: Extraction / collection unit 3: Data file 4: Action display unit 5: Display 6: System control unit 7: Procedure management table 71: Procedure information 72: Correspondence table 10: System control unit

Front page continuation (72) Inventor Fumiko Matsuzawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (6)

[Claims] 1. A parallel program development supporting apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor. And the action extraction unit (2) that extracts and collects the procedure information (71) and the action information (8) of the parallel program, and the action information for each processor collected by the action extraction unit (2) for a series of processes. A parallel program development support device characterized in that a procedure is displayed in association with each processor based on (71) and operation information (8). 2. A parallel program development supporting apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor, wherein the parallel program is operated by a plurality of processors and the plurality of processors are operated by the plurality of processors. And a motion extraction unit (2) that extracts and collects the procedure information (71) and the motion information (8) of the parallel program in real time, and the procedure information (71) extracted in real time by the motion extraction unit (2). And a parallel program development support device configured to display a procedure corresponding to each processor in real time based on the operation information (8). 3. A parallel program development supporting apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor, the plurality of processors operating the parallel program, and the plurality of processors operating on the plurality of processors. And a motion extraction unit (2) that extracts and collects the procedure information (71) and the motion information (8) of the parallel program, and stores the information collected by the motion extraction unit (2).
These procedure information (71) and operation information (8)
A parallel program development support device, which is configured to be sequentially displayed as a moving image according to the passage of time (or in the opposite direction). 4. A parallel program development support apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor. An operation extraction unit (2) for extracting and collecting the procedure information (71) and operation information (8) of the parallel program, and a procedure management table for managing the number of executions of each procedure collected by the operation extraction unit (2) (7), and the parallel program development support device characterized in that the procedure is displayed for each processor in a color corresponding to the number of times of execution of the procedure managed by the procedure management table (7). 5. A parallel program development support apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor, the plurality of processors operating the parallel program, and the plurality of processors operating on the plurality of processors. An action extraction unit (2) that extracts and collects the procedure information (71) and action information (8) of the parallel program, and the procedure information (71) and action information (8) extracted by the action extraction unit (2) Of the specified procedure and the correspondence table (72) for registering the correspondence between the variable and the variable (shared variable), and the same variable as the variable of the specified procedure registered in the correspondence table (72). Parallels characterized by being configured to display registered procedures in association with each processor Program development support system. 6. A parallel program development support apparatus for collecting procedure information at the time of execution of a parallel program and displaying the procedure information in association with each processor, the plurality of processors operating the parallel program, and the plurality of processors operating on the plurality of processors. An operation extraction unit (2) for extracting and collecting procedure information (71) and operation information (8) of the parallel program, and a flag for managing display / non-display for each procedure collected by the operation extraction unit (2) And a procedure management table (7) provided with, and configured to display only the flag-set procedures of the procedure management table (7) in association with each processor. Development support device.