JPH0580693B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means and Effects for Solving the Problems Examples Correspondence between Examples and Figure 1 Structure of the embodiment Operation of the embodiment (i) Normal operation (ii) Interrupt operation when a parity error occurs Summary of the embodiment Modifications of the invention Effects of the invention [Summary] A portable terminal device, which is a data storage means. By performing a parity check on the stored data, and when detecting an error in the data, interrupting normal processing and writing error identification data in an area corresponding to the data, and then canceling the interrupt. Processing can be continued after error detection, and memory failure analysis can be performed.

[Industrial application field]

The present invention relates to a portable terminal device, and more particularly to a portable terminal device that continues processing when a parity error is detected during data processing and subsequently performs failure analysis.

[Conventional technology]

As a portable terminal, a hand-held terminal (hereinafter referred to as HHT) is conventionally known.

Such an HHT is a portable information processing and data management device that has data processing functions, data storage functions, and the like. For example, it is possible for an out-of-house sales person to store management information such as product sales and orders, and to calculate sales amounts, order amounts, and the like.

In order for a terminal device to perform a desired operation, data stored in a memory must be read and written accurately, and a parity check is used to detect data errors.

In the parity check, a parity bit corresponding to each byte of memory data is prepared, and errors are detected by comparing the sum of each bit of the byte (ignoring carry) with the parity bit. In this method, a parity area is provided inside or outside the memory, and a parity check is performed when reading data.

For example, when reading customer management information stored in the memory of the HHT, a parity check is performed on the read data according to an operator's instruction.

[Problem that the invention seeks to solve]

By the way, in the conventional method mentioned above,
When a parity check is performed on data read from the HHT's memory and a parity error is detected, the operator is notified of the error and processing is stopped, making it impossible to continue data processing. The point was hot. In particular, HHT
is often used on the go, and if it becomes unusable due to error detection, it will cause problems.

The present invention was created in view of the above points, and provides a portable terminal device that is capable of continuing processing after an error is detected and also capable of performing memory failure analysis. The purpose is to

[Means for solving problems]

FIG. 1 is a basic block diagram of the portable terminal device of the present invention.

In the figure, data storage means 161 in a portable terminal device having memory check parity
stores data and parity corresponding to the data.

The error detection means 111 is the data storage means 16
A parity check is performed on the data read from 1 to detect errors in the data.

The interrupt instruction means 121 is the error detection means 11
When a data error is detected in step 1, an interrupt instruction for interrupting normal processing is output.

The data writing means 131 includes the interrupt instruction means 1
An interrupt instruction from 21 is introduced, and error identification data is written in an area corresponding to the data in which the error has been detected by the error detection means 111.

The interrupt canceling means 141 is the data writing means 1
After the write operation in step 31 is completed, the interrupt is canceled.

Therefore, the overall configuration is such that when an error is detected by the parity check, an interrupt is generated and identification data of the error is written.

[Effect]

Data and parity corresponding to the data are stored in the data storage means 161, and the error detection means 111 performs a parity check on the data to detect errors.

When an error is detected by the error detection means 111,
The interrupt instruction means 121 outputs an interrupt instruction, and the data writing means 131 writes error identification data in an area corresponding to the data in which the error has been detected. Then, the interrupt canceling means 141 cancels the interrupt.

In the present invention, when an error is detected by the parity check in the error detection means 111, an interrupt is made to normal processing, and after writing identification data of the error, the interrupt is canceled. Therefore, processing can be continued after error detection, and memory failure analysis can be performed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a portable terminal device in an embodiment of the present invention.

Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The error detection means 111 corresponds to the parity checker 211.

The interrupt instruction means 121 corresponds to the parity checker 211.

The data writing means 131 is the central processing unit 2
Corresponds to 01.

The interrupt release means 141 is the central processing unit 20
Corresponds to 1.

The data storage means 161 includes a RAM 261,
Corresponds to RAM263.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

Configuration of Embodiment In FIG. 2, an HHT 200 as a portable terminal device according to an embodiment of the present invention includes a central processing unit 201 for overall control.

A basic load program for reading programs and data processed by the central processing unit 201 from a center (not shown) is written in the ROM 265. RAM261
has a capacity of, for example, 40 Kbytes, and stores an execution program for processing by the central processing unit 201 and parity corresponding to the program. Further, the RAM 263 has a capacity of, for example, 256 Kbytes, and stores data processed by the central processing unit 201.

A memory backup battery 269 is connected to the RAM 261 and RAM 263.
As long as this memory backup battery 269 is connected and in a normal voltage state,
Programs and data stored in RAM 261 and RAM 263 are maintained.

Parity checker 211 performs a parity check based on the program stored in RAM 261 or the data stored in RAM 263. In addition, Paritei Chietsuka 211 is
Store programs and data in RAM261 or RAM2
When writing to RMA 261 or RAM 263, parity calculated based on those byte data is output to RMA 261 or RAM 263.

The keyboard 251 is equipped with a plurality of keys, and operation instructions can be given to the central processing unit 201 by operating predetermined keys. Furthermore, if the user wishes to change or add to the initial setting data stored in the memory backup battery 269 depending on the usage status of the HHT 200, an instruction or data to that effect is input.

The display 253 displays data such as processing results when the HHT 200 is operated. The power supply section 273 supplies a predetermined operating voltage to each circuit section of the HHT 200 from its built-in battery (common to the memory backup battery 269 or a separate battery) when a start switch (not shown) is turned on.

The printer 255 prints calculation results and input/output data by the central processing unit 201.

This HHT 200 includes a line interface 271 and can be connected to an external line. Thereby, desired data processing can be performed by communicating with other HHTs 200 or the center via the line to exchange programs and data.

The central processing unit 201 is a parity checker 2.
11, ROM265, line interface 2
71, keyboard 251, display 25
3. Connected to the printer 255 by a bus. Also, Paritei Chietsuka 211 and RAM
261 and RAM263 are connected,
An interrupt signal line from parity checker 211 is connected to central processing unit 201 . Furthermore,
The memory backup battery 269 is
61 and RAM 263.

Operation of the Embodiment FIG. 3 shows the normal operation of the HHT in the embodiment. In addition, Figure 4 shows the HHT in the example.
This figure shows the interrupt operation when a parity error is detected.

Now, we will consider four normal operations of the HHT: external data writing, data reading, data transmission to the center, and parity error information transmission. Also, when a parity error is detected, normal operation is interrupted and the 16 bytes near the address where the parity error occurred are stored as “DD”.
shall be rewritten as .

The normal operation and the interrupt operation when a parity error occurs will be explained separately.

Reference will be made to FIGS. 2 to 4 below.

(i) Normal operation When the operator turns on the start switch of the HHT200, the central processing unit 201
Initializes each component circuit of the HHT 200 (step 311).

Next, the central processing unit 201 reads a program for performing a desired operation from an external center via the line interface 271. The parity checker 211 calculates the parity corresponding to each byte data of the read program and stores the parity in the RAM 261 together with the program (step 312).

When the program has been stored in the RAM 261, the central processing unit 201 reads a master file containing customer information from an external center via the line interface 271. Then, the parity checker 211 calculates the parity corresponding to each byte data of the master file, and stores the master file and the parity in the RAM 263 (step
313).

When the program loading (step 312) and master file loading (step 313) are completed, the HHT
200 is portable.

Next, the HHT 200 waits for input from the operator, and the central processing unit 201
Then, it is determined whether or not there is a key input from the keyboard 251 (step 314).

It is judged as negative if there is no key input from the keyboard 251, and steps continue until there is a key input.
Repeat judgment 314.

When the operator presses an instruction key for any operation from the keyboard 251, the central processing unit 2
01 makes an affirmative determination as to whether or not there is a key input, and then it is determined whether the pressed key is a data write instruction key (step 315).

When the data write instruction key is pressed on the keyboard 251, an affirmative determination is made in step 315, and then data is written.

Next, the operator inputs desired data from the keyboard 251 (step 316).
The central processing unit 201 is a parity checker 2.
11, the input data is transferred to RAM2
63 (step 317). Note that the parity checker 211 calculates parity corresponding to each byte of input data, and the parity is stored in the RAM 263 together with the input data.

When the input data and parity have been stored in the RAM 263, the HHT 200 again enters a state of waiting for input, and the central processing unit 201 repeats the processing from step 314 onwards.

When the operator presses a key other than the data write instruction on the keyboard 251,
The central processing unit 201 makes a negative determination in step 315, and then determines whether the pressed key is a data read instruction key (step 318).

When the data read instruction key is pressed on the keyboard 251, an affirmative determination is made in step 318, and then data is read.
(Step 319).

The central processing unit 201 processes the data.
The parity checker 211 performs a parity check on the data read from the RAM 263. If the result of the parity check is normal, the central processing unit 201 displays the corresponding data on the display 253.

When the data display on the display 253 is finished, the HHT 200 enters a state of waiting for input, and the central processing unit 201 repeats the processing from step 314 onward.

When the operator presses a key other than the data write command or data read command on the keyboard 251, the central processing unit 201 makes a negative determination in step 318, and then the pressed key is the stored data transmission command key. It is determined whether or not (step 321).

When the stored data transmission instruction key is pressed on the keyboard 251, an affirmative determination is made in step 321, and then the corresponding data (or the corresponding data area) read from the RAM 263 is transmitted (step 322).

First, the central processing unit 201 reads transmission data from the RAM 263, and the parity checker 211 performs a parity check on the data read from the RAM 263. If the result of the parity check is normal, the central processing unit 201 sends the corresponding data to the line interface 271. Line interface 271 transmits the input data to the center via an external line.

Once the data has been sent to the center,
The HHT 200 enters a state of waiting for input, and the central processing unit 201 repeats the processing from step 314 onwards.

When the operator presses a key on the keyboard 251 other than a data write instruction, data read instruction, or data transmission instruction, the central processing unit 201 makes a negative determination in step 321, and then the pressed key is It is determined whether or not this is the transmission instruction key for the parity error data that has occurred up to now (step 323).

When the parity error data transmission instruction key is pressed on the keyboard 251, the step
After making an affirmative determination in step 323, the parity error data is then read out from the RAM 263 and transmitted (step 324).

The central processing unit 201 sends the parity error data read from the RAM 263 to the line interface 271, and the line interface 271 sends the data to the center. In addition, when a parity error occurs, RAM26
The details of the parity error data stored in 3 will be explained later in "Interruption Operation When Parity Error Occurs".

When the parity error data has been sent to the center, the HHT 200 enters the input waiting state, and the central processing unit 201 sends the parity error data to the center in step 314.
Repeat the following process.

The operator also uses the keyboard 251 to instruct data writing, data readout,
If a key other than the data transmission instruction or the parity error data transmission instruction is pressed, the central processing unit 201 makes a negative determination in step 321. If a key other than these instruction keys is input,
It is determined that it is an incorrect key input, and HHT2
00 enters a state of waiting for input, and the central processing unit 201 repeats the processing from step 314 onwards.

(ii) Interrupt operation when a parity error occurs When a parity error occurs during a parity check when reading data from the RAM 263 (step 319 or step 322), the parity checker 211 issues an interrupt instruction signal via the interrupt signal line. is sent to the central processing unit 201. When the central processing unit 201 receives an interrupt instruction signal from the parity checker 211, it interrupts normal data processing, and
Execute interrupt operation.

First, the central processing unit 201 reads the address of the data in which the parity error has occurred (step 410).

Next, the central processing unit 201 reads the memory data stored at the address where the parity error has occurred, and saves the memory data to another area of the RAM 263 (step 411).

Next, the central processing unit 201 sets the lower 4 bits of the address data to "0" (step 412) and writes data "DD" for identifying a parity error to that address (step 413).

For example, if a parity error occurs in the data stored at address "3333",
At step 412, the lower 4 bits of data are set to “0”.
and get the address “3330”. step
At 413, data "DD" is written to the address "3330".

Next, the central processing unit 201 adds 1 to the address "3330" to obtain the address "3331" (step 414).

Then, the central processing unit 201
It is determined whether the lower 4 bits of the address "3331" obtained in step 414 are all "0", that is, whether the address is "xxxx0" (step 415). Step 414
Since it is the address "3331" obtained in step 4, a negative determination is made and the processing from step 413 (writing data "DD" to the address) is repeated.

When the central processing unit 201 finishes writing data "DD" to address "333F" in step 413, it obtains address data "3340" by adding 1 to address data "333F" in step 414. Next, step 415 (lower 4
If the bit data is all "0" or not, an affirmative determination is made and the interrupt processing when a parity error occurs is terminated.

Upon completion of the interrupt processing when a parity error occurs, the central processing unit 201 cancels the interrupt and resumes normal processing.

The memory data saved in the interrupt operation when a parity error occurs and the error identification data "DD" written in the 16 bytes near the address where the error occurred are processed in step 324 of the normal operation shown in Figure 3. , is sent to the center as error data. At the center, the location (address) where the parity error occurred can be determined by the 16-byte error identification data "DD" and failure analysis is performed based on the memory data.

Summary of the Embodiment As described above, when data is read from the RAM 263, the parity checker 211 performs a parity check, and when a parity error is detected, an interrupt instruction signal is sent to the central processing unit 201. When the central processing unit 201 receives the interrupt instruction signal, it interrupts normal data processing, saves the memory data where the parity error has occurred, and identifies the error in 16 bytes near the address where the parity error has occurred. Store data “DD”. Then, when the above interrupt processing is completed, normal processing is resumed.

Therefore, data processing can be continued after error detection, and memory failure analysis can be performed.

Modifications of the invention In the embodiments of the invention described above,
I thought about a parity check when reading data stored in RAM263, but the RAM
The same can be considered when reading a program stored in H.261.

Further, in the embodiment, the parity error identification data is "DD", but a value that is used less frequently may be appropriately assigned depending on the purpose of use, place of use, etc.

Furthermore, “Correspondence between Examples and Figure 1”
Although the correspondence relationship between FIG. 1 and the present invention has been explained in the above, those skilled in the art will easily infer that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, when a parity error in data stored in the data storage means is detected, normal processing is interrupted, error identification data is written in an area corresponding to the data, and then By canceling the interrupt immediately, processing can be continued and memory failure analysis can be performed, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a portable terminal device of the present invention, FIG. 2 is a block diagram of the configuration of a portable terminal device in an embodiment of the present invention, and FIG. 3 is a block diagram of a portable terminal device in an embodiment of the present invention. Diagram for explaining normal operation of the device, No. 4
The figure is an explanatory diagram of an interrupt operation of a portable terminal device according to an embodiment of the present invention. In the figure, 111 is an error detection means, 121
131 is an interrupt instruction means, 131 is a data writing means,
141 is an interrupt release means, 161 is a data storage means, 200 is an HHT, 201 is a central processing unit, 2
11 is parity chietsuka, 251 is keyboard,
253 is a display, 255 is a printer, 26
1,263 is a RAM, 265 is a ROM, 269 is a memory backup battery, 271 is a line interface, and 273 is a power supply unit.

Claims (1)

[Scope of Claims] 1. A portable terminal device having a memory check parity, comprising: a data storage means 161 for storing data and parity corresponding to the data; and a parity check for data read from the data storage means 161. an error detecting means 111 for detecting an error in the data; a data writing means 131 for writing error identification data in an area corresponding to the data in which an error has been detected by the error detecting means 111; Interrupt release means 1 that releases the interrupt after the write operation at 131 is completed
A portable terminal device comprising: 41;