JPH0580165A - Analog electronic clock - Google Patents

Abstract

PURPOSE:To know certainly the residual capacity of a secondary power supply by furnishing a residual capacity rechecking function, and providing a means to restrict the rechecking function to the specified number of times, means to prohibit the function for a specified period of time or until the function input pointer supply voltage is ended, and means to make pointer movement start delay at the time of initial entry. CONSTITUTION:The current from a power generating mechanism 1 is rectified by a charge control circuit 2 to charge a capacitor 3. A supply voltage sensing circuit 4 senses the voltage value therein, while a fast feed pulse circuit 5 is fed with signals accordingly from the circuit 4 to determine the number of fast feed pulses. Because the voltage value of the capacitor is related to its residual capacity as 1:1, the sensor circuit 4 senses the residual capacity of the capacitor 3 as the voltage value. A motor pulse selector circuit 7 prohibits input from a normal pointer feed pulse forming circuit 6 in conformity to a switch input signal given by a pulse control circuit 12, and drives a display mechanism 9 upon selecting fast feed pulses in accordance with the voltage value from the fast feed pulse circuit 5, and thus the residual capacity of the capacitor 3 is displayed. Thereby the residual capacity of secondary power supply can be known certainly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rechargeable timepiece using a secondary power supply, and a power supply remaining capacity display device for an analog electronic timepiece for displaying the remaining capacity of the secondary power supply by the movement amount of a pointer.

[0002]

2. Description of the Related Art Conventionally, as a means for knowing the remaining capacity of a secondary power source, as described in Japanese Patent Publication No. 61-61077, the input of a clock signal to a drive circuit is prohibited for a certain time by operating an external switch. The voltage detection means is operated to input a voltage display signal to the drive circuit to drive the pointer to perform a voltage display operation according to the moving amount of the pointer, and a correction signal is input to the drive circuit to drive the pointer. A method has been proposed in which the current time is returned to the current time.

[0003]

However, in the above-mentioned prior art, since the voltage display signal and the correction signal for returning the pointer to the present time are paired, the pointer indicates the remaining capacity display operation of the secondary power source. In order to check the remaining capacity again after the operation, it was necessary to wait until the pointer returned to the current time by the correction signal. For example, if the sum of the number of power supply display signals and the number of correction signals is set to 60 seconds for one rotation of the second hand, the remaining capacity display operation of the secondary power source of the second hand after the switch input is overlooked. There is a problem that it is necessary to wait a minute before checking the capacity again.

Therefore, the present invention is intended to solve such a problem, and an object thereof is to add a reconfirmation function to the remaining capacity display device and to reliably recognize the remaining capacity of the secondary power source. Is in the place of providing.

[0005]

An analog electronic timepiece according to the present invention includes a power supply voltage detecting means for outputting a voltage display signal according to an output voltage value of a power supply section and a fast-forwarding pulse number according to the voltage display signal. With the fast-forward pulse creating circuit, the input of the normal time display signal to the drive circuit is stopped by the switch input signal by the external operation, and the fast-forward pulse signal is input to the drive circuit to set the output voltage value of the power supply unit. According to the number of fast-forward pulses corresponding to the fast-forward pulse, the motor pulse selection means for performing a voltage display operation according to the amount of movement, the number of fast-forward pulses corresponding to the voltage display signal and the switch input signal from the time of input. Pulse control for detecting the difference between the number of pulses of the time signal and displaying the voltage of the power supply unit by fast-forwarding the pointer and then returning the pointer to the current time. Path and the pulse control circuit inputs a switch input signal by an external operation before the pointer returns to the present time, the power supply voltage detecting means performs the voltage display operation again and the number of pulses of the voltage display signal. And a pulse control circuit for detecting a difference between the number of pulses of the clock signal and a unit for adding the number of pulses of the voltage display signal according to the output voltage value of the power supply unit, and externally. After displaying the power supply voltage by fast-forwarding the pointer with the counter circuit that counts the switch input signal by operation and the switch input signal,
A pulse control circuit for resetting the counter when the pointer returns to the current time, and a means for inhibiting the input of the switch input signal when the counter circuit for the switch input signal reaches a predetermined number of times. At the same time, there is provided means for inhibiting the input of the switch input signal for a predetermined period from the input of the switch input signal by an external operation to the fast-forwarding drive of the pointer by the power supply voltage detection means to finish the display of the power supply voltage. With the switch input signal by external operation,
A means for detecting that it is a switch input signal for shifting from the normal time display of the pointer to the first fast-forward drive operation,
When the detection is made, it is characterized by having a control means for prohibiting the start of the fast forward drive of the pointer by the power supply voltage detection means from the input of the switch input signal for a predetermined time, and by the input of the switch input signal by an external operation. A counter circuit that counts a predetermined time period after the pointer is fast-forward-driven to end the power supply voltage display, and a control unit that prohibits the input of the switch input signal during the period from the input of the switch input signal to the end of the predetermined time period. It is characterized by having.

[0006]

EXAMPLE A large-capacity electric double layer capacitor (hereinafter referred to as a capacitor) is used as a power source section, and the movement of a rotary weight as described in JP-A-52-82478 is used as a power generation means by a small generator to generate electric energy. An embodiment of the present invention, which uses the method of converting to the above and charging the capacitor through the charge control circuit, will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the configuration of this embodiment. 13 is an oscillation circuit for a wristwatch 327
A 32768 Hz signal is sent to the frequency dividing circuit 14 using an ultra-small crystal oscillator with a source frequency of 68 Hz as a reference source. The frequency dividing circuit 14 sequentially divides the 32768 Hz signal to generate a signal necessary for circuit operation. The current generated by the power generation mechanism 1 including an automatic winding generator is rectified by the charge control circuit 2 and charged in the capacitor 3. The power supply voltage detection circuit 4 detects the voltage value of the capacitor 3, and the fast-forward pulse forming circuit 5 inputs a signal from the power supply voltage detection circuit 4 according to the voltage value of the capacitor 3 to determine the number of fast-forward pulses. Here, the relationship between the voltage value and the capacitance ratio of the capacitor 3 will be described with reference to FIG. The vertical axis is the voltage value of the capacitor,
The horizontal axis represents the capacitance ratio of the capacitor, and as can be seen from this figure, the voltage value of the capacitor gradually increases as the capacitance increases. In this way, since the capacitor has a one-to-one correspondence between the voltage value and the remaining capacity, it is easy to know the remaining capacity from the voltage value of the capacitor. The remaining capacity of 3 is detected as a voltage value. The normal hand movement pulse forming circuit 6 sends a 1 Hz clock signal to the motor pulse selecting circuit 7
The motor pulse selection circuit 7 selects the signal from the normal hand movement pulse forming circuit 6 and outputs it to the motor drive circuit 8 during normal hand movement. The display mechanism 9 has a well-known step motor, and displays a normal time by a pulse from the motor drive circuit 8. The switch 10 is a switch input means by an external operation, and the switch input control circuit 11 controls the input of the switch and outputs a switch input signal to the pulse control circuit 12. When the switch input signal is output from the pulse control circuit 12, the motor pulse selection circuit 7 prohibits the input of the 1 Hz clock signal from the normal hand movement pulse forming circuit 6 and responds to the voltage value of the capacitor 3 from the fast-forward forming circuit 5. The fast-forward pulse is selected and output to the motor drive circuit 8, and the pointer of the display mechanism 9 is fast-forward driven to display the remaining capacity of the capacitor 3. When the switch input control circuit 11 outputs a switch input signal pulse, the pulse control circuit 12 inputs the number of fast-forwarding pulses from the fast-forward forming circuit 5, and the normal hand movement prohibited from being input by the pulse number and the motor pulse control circuit 7. The difference from the number of 1 Hz clock signals from the pulse forming circuit 6 is detected,
When the number of fast-forwarding pulses from the fast-forward forming circuit 5 and the number of 1 Hz clock signals from the normal hand movement pulse forming circuit 6 match, a match signal is output to the motor pulse control circuit 7. The motor pulse control circuit 7 restarts the input of the 1 Hz clock signal from the normal hand movement pulse forming circuit 6 when the coincidence signal is input, and the pointer of the display mechanism 9 restarts the normal hand movement through the motor drive circuit 8 Return to time.

Next, an embodiment corresponding to claim 1 will be described in detail. FIG. 3 is a detailed circuit diagram relating to the generator of the fast-forward pulse 105 in the block diagram of FIG. FIG. 4 is a time chart for explaining the operation. The number of fast-forwarding pulses is determined by the outputs 104a and 104b of the power supply voltage detection circuit 4, which is a known 2-bit A / D conversion circuit,
In this embodiment, the relationship between the remaining capacity of the capacitor 3, the moving amount of the pointer, and the signals 104a and 104b is set again as follows.

[0009] First, when the switch 10 is input, the signal 100 is converted into the signal 101 synchronized with the falling edge of the signal φ16 by the switch input control circuit 11 which is a known chattering prevention circuit. (Here, the potential on the + side of the capacitor 3 is defined as V _DD , and the potential on one side is defined as V _SS, and V _DD is expressed as “1” and V _SS is expressed as “0” in the description of the logic operation. The outputs of the frequency dividing circuit 14 of FIG. 1 are 512 Hz, 256 Hz, 16 Hz and 1 H, respectively.
z is defined as φ512, φ256, φ16, φ1. )
When the signal 101 becomes "1", the one-shot waveform of the signal 301 is formed by the rising differentiating circuits 306 and 307. The signal 301 is connected to the set input of the SR latch 308 and the reset input of the counter 312, respectively.
Output 303 becomes "1", and the counter 312 is initialized. When the signal 303 becomes "1", the AND gate 3
11 becomes active and outputs the φ16 signal as 304. The counter 312 that has been initialized here is 304
It counts up in synchronization with the falling edge of. On the other hand, 104a and 104b corresponding to the remaining capacity of the capacitor are converted into the following bit strings (D _{1 to} D ₆ ) by the decoder 314.

104a 104b D ₁ D ₂ D ₃ D ₄ D ₅ D ₆ (decimal) 0 0 1 0 1 1 0 0 0 (= 5) 1 0 0 1 1 0 1 0 0 (= 10) 0 1 1 1 1 1 1 0 0 (= 15) 1 1 0 0 1 1 0 1 0 (= 20) Here, the comparison circuit 313 is a known bit string comparison circuit, and the signal 305 is output only when the output bit string of the decoder 314 and the output bit string of the counter 312 are equal. "1" is output. Therefore, when the value of the counter 312 reaches the output value of the decoder 314 corresponding to the number of fast-forwarding pulses, the signal 305 becomes "1", and a one-shot waveform is output to the output 302 of the rising differentiating circuits 309 and 310. Since the signal 302 is connected to the reset input of the SR latch 308, the signal 303 becomes “0”, the gate 311 becomes non-active, and φ 16 output to 304 stops output. With the above operation, a predetermined number of fast-forward pulses are output as the signal 304. Again the differentiating circuit 315,
At 316, each pulse of the signal 304 is converted into a pulse width of 3.9 msec suitable for driving the motor, and the signal 105
And the motor pulse selection circuit 7 in FIG.
Will be input to the motor drive circuit 8. Note that FIG. 4 shows a time chart when the number of fast-forwarding pulses = 5.

FIG. 5 is a diagram for explaining the details of the normal hand movement pulse forming circuit 6 and the motor pulse selecting circuit 7 in FIG. Further, FIG. 6 shows a time chart for explaining the operation of the normal hand movement pulse forming circuit 6. First, as the operation of the normal hand movement pulse forming circuit 6, the pulse signal 104 having a pulse width of 3.91 msec and a period of 1 sec synchronized with the falling edge of φ1 is formed by the φ1 falling differentiating circuits 501 and 502. The motor pulse selection circuit 7 is composed of a known selector, and normally operates the hand movement pulse signal 104,
The fast-forward pulse signal 105 is switched by the output signal 103 of the pulse control circuit 12 to form an input signal 106 to the motor drive circuit 8. Here, the pulse control circuit 1
2 controls the signal 103 by counting the fast-forward pulse signal 105 and the normal hand movement pulse signal 104. The detailed operation of the pulse control circuit 12 will be described below with reference to FIG. Further, FIG. 8 shows a time chart for explaining the operation of the pulse control circuit 12. First, signal 1
02, it is the same signal as the signal 101 which is the output of the switch input control circuit 11 in the embodiment of claim 1.
Therefore, the signal 102 is input according to the switch input. Signal 10 synchronized with the falling edge of φ16
2 becomes a signal 713 delayed by the delay circuits 701 and 702 until the rising edge of φ16. During this delay period (the signal 102 is “1” and the signal 713 is “0”), if the signal 103 is “0”, the gate signal 715 outputs the pulse signal 714. Signal 714 is counter 7
05, connected to the reset input of the counter 707 to initialize each counter. This operation means that the counters 705 and 707 are initialized only when the switch is input during the normal hand movement (signal 103 = "0"). Next, the rising differential circuits 703 and 7
04 forms a one-shot waveform 711 synchronized with the rising edge of the signal 713 and is connected to the set input of the SR latch 710, and sets the output signal 103 of the SR latch 710 to "1". As a result, the motor pulse selection circuit 7 selects the fast-forward pulse side, and the fast-forward pulse 105 is output to the motor drive circuit 8. At the same time, signal 10
Reference numeral 5 is also connected to the clock input of the counter 707 to count the number of fast-forwarding pulses. Further, the clock input of the counter 705 is connected to the normal hand movement pulse 104 which is a signal once per second, so that it is possible to count the elapsed time from the start of the fast-forward operation. Again, the output values of the counter 707 and the counter 705 are compared and compared by the comparator 706, so that it is possible to detect that the current time has reached the advanced position of the second hand by the fast forward hand movement. That is, when the values of both counters match, the output signal 7 of the comparator 706
12 becomes "1", and the SR latch 7 is passed through the gate 709.
Reset 10. As a result, the signal 103 can be returned to "0" and the hand movement can be returned to the normal state without disturbing the time. Here, by configuring the pulse control circuit 12 as described above, it becomes possible to add the number of outputs of the fast-forward pulse 105 to the counter 707. Referring to FIG. 8 as an example, the counter 707 counts five fast-forward signals 105 by the first switch input signal 102, and the second switch input signal 102.
By this, 5 shots of the fast-forward signal 105 are added again. This means that the counters 707 and 705 are not initialized by the second switch input, so that the value of "5 + 5 = 10" is held in the counter 707. At this time, since the counter 705 counts the signal 104 until it matches the value of 10, the normal hand movement state is not restored for 10 seconds, and the time is not changed. The above function means that the remaining capacity display can be reconfirmed. That is, when the moving amount of the pointer cannot be read well by the first switch input, the switch can be input again to cause the pointer to perform the fast-forward operation again and reliably read the moving amount, that is, the remaining capacity. Become. In addition, the reconfirmation function does not disturb the time.

According to the embodiment of claim 1, although the operability for the user is improved, if the reconfirmation function is repeatedly executed, a problem occurs that the malfunction occurs due to the overflow of the counter 707, and the counter is lost. Even if the number of bits of 707 is increased, even if it is used in a state where it does not overflow, by executing the reconfirmation function, the amount of advancement of the pointer from the true time becomes large, and the holding time until the normal hand movement state is restored. It has a problem that it becomes long.

Therefore, as an invention for solving the above problems,
An embodiment corresponding to claim 2 will be described with reference to FIG. Further, FIG. 10 shows a time chart for explaining the operation. The other block configuration in FIG. 1 is the same as that of the first embodiment. First, during normal hand movement (signal 103 =
The operations to switch to the confirmation function when the switch is "0" are the same as those of the first embodiment. Here, the signal 714 is a signal that is output only when the confirmation function is first entered from the time of normal hand movement, and the signal 711 is the confirmation function (first time,
It is a signal that is output every time when entering (reconfirmation). Utilizing this, the signal 714 is input to the initialization terminal R of the counter 901, the signal 711 is input to the clock input terminal C of the counter 901, and the counter 901 is used as the counter of the number of times the reconfirmation function is activated. It becomes possible.
In the present embodiment, the first bit output D of the counter 901
₁ output D ₂ of 2bit is by resetting the switch input control circuit 11 inside the flip-flop output signal 905 of AND gate 906 as a "1" when it is "1", respectively. This prohibits the switch input from the fourth time as shown in the timing chart of FIG.
The reconfirmation function is performed many times to solve the problem that it takes a long time to return to the normal time. In this embodiment, the switch input is prohibited after the fourth time.
By changing the decoding condition of the gate 906, it is easy to change to any number of times.

Next, an embodiment corresponding to claim 3 will be described with reference to FIG. The circuit characteristic of this embodiment is that the signal 303 in the fast-forward pulse forming circuit 5 in FIG. 3 is connected to the reset input of the flip-flop in the switch input control circuit 11. As shown in FIG. 4, the signal 303 is a signal that becomes “1” only during the fast-forwarding operation in response to the switch input. With the circuit configuration shown in FIG. 11, the signal 303 becomes “1”, That is, the switch input during the fast-forwarding hand movement is prohibited. As a result, the fast-forwarding pulse forming circuit 5 is again activated during the fast-forwarding movement.
It is possible to prevent erroneous display due to start-up.

Next, an embodiment corresponding to claim 4 will be described with reference to a circuit diagram 12 and a time chart diagram 13. In the embodiments corresponding to claims 1, 2 and 3, the output signals 101 and 102 of the switch input control circuit 11 are exactly the same signals, but in the present embodiment, they are output to the fast-forward pulse forming circuit 5. The signal 101 and the signal 102 output to the pulse control circuit 12 are different signals. First, when a switch input is made, the output signal 102 of the chattering prevention circuit 120 is input to the pulse control circuit 12 and the signal 103.
Becomes "1" and the normal hand movement pulse 104 is not output. Next, when the signal 103 becomes "1", the inverter 12
The output of 7 becomes "0", and the flip-flops 121, 1
The reset applied to 22 is released. From this time point on, the flip-flop 121 operates as a circuit that divides φ1 in half, and the output signal 129 of the flip-flop 122 is output at the first falling edge of the output signal 128.
Becomes "1". When the signal 129 becomes “1”, the one-shot signal 130 is generated by the rising differentiating circuits 123 and 124.
And is output as the signal 101 through the OR gate 126. The above operation means that a delay of 1 to 2 seconds occurs from the input of the signal 102 to the output of the signal 101, as shown in the time chart FIG. 13, and the signal 101 is a trigger signal of the fast-forward pulse signal 105. Therefore, it means that the fast-forwarding hand is moved only after a waiting time of 1 to 2 seconds from the switch input to the fast-forwarding operation. This is to avoid the possibility of erroneous reading of the movement amount if the fast-forwarding operation is performed without inserting hair when the confirmation function is operated by switch input during normal hand movement. In addition, at the time of reconfirmation, it is preferable to immediately perform the fast-forward operation again with the switch input, because the already stopped pointer is only fast-forwarded again. Here, at the time of reconfirmation, signal 12
By utilizing that 9 is already "1", the signal 10
2 and the signal 129 are input to the AND gate 125 to obtain the output signal 131. The signal 131 becomes a signal which is first output at the switch input after the second time, and becomes the signal 101 by obtaining the OR gate 126. As a result, at the time of reconfirmation, the fast-forwarding hand movement will be performed immediately. In this embodiment, since the waiting time is controlled by the input clock φ1 of the flip-flop 121, it is easy to change this input clock and set an arbitrary waiting time.

Next, an embodiment corresponding to claim 5 will be described with reference to a circuit diagram 14 and a time chart diagram 15. The feature of this embodiment is that a circuit for prohibiting the switch input for a predetermined time is added immediately after the fast-forwarding operation is finished, so that the second fast-forwarding operation is started immediately after the first fast-forwarding is completed by the continuous switch input or the like. To avoid reading the wrong amount of movement. The output signal 302 in the fast-forward pulse forming circuit 5 is a signal (see FIG. 4) output when the fast-forward pulse 105 has finished outputting, and the signal 302 sets the SR latch 141 to set the signal 144 to "1". At the same time, the counter 143 is initialized.
When the signal 144 becomes "1", the switch input control circuit 1
The flip-flop in 1 is reset and inhibits the switch input, and at the same time, activates the AND gate 142 to pass φ16 to the clock input of the counter 143. When the counter 143 counts up, the predetermined bit output signal 145 becomes "1" after a predetermined time, resets the SR latch 141, and returns the signal 144 to "0". When the signal 144 becomes "0", the switch input becomes possible again. This makes it possible to reliably read the movement amount. In the switch input prohibited section, the clock frequency to the counter 143 is changed,
It is easy to change the setting by changing the number of stages of the counter.

The above-mentioned five embodiments can be realized individually, or can be realized in any combination or in all combinations. As a result, it is possible to provide a capacitor remaining amount confirmation function with very good operability.

[0018]

As described above, the structure of the present invention has the following effects. (A) With the reconfirmation function of the secondary power source remaining capacity display, the duration of the clock function can be surely recognized in a short time. Therefore, it is possible to know when the charging is necessary, which helps prevent the timepiece function from being stopped, and it is possible to provide the wearer with a sense of reliability. (B) By limiting the re-confirmation function to a predetermined number of times, it is possible to prevent the wearer from repeatedly using the re-confirmation function to display the pointer for a long time such as 10 minutes or 20 minutes. (C) By providing a predetermined time from the switch input to the start of display of the remaining capacity of the pointer during normal hand movement, it becomes easier to confirm the power supply voltage display start position of the pointer and the movement amount of the pointer can be reliably recognized. .. (D) By prohibiting the switch input of the reconfirmation function until the remaining capacity of the pointer is displayed or for a predetermined period, when the switch is continuously input, the movement of the pointer for the first time and the movement of the pointer for reconfirmation are performed. Can be continuously operated to prevent the remaining capacity display from being erroneously confirmed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a relationship diagram between a voltage value of a capacitor and a capacitance ratio.

FIG. 3 is a circuit diagram relating to a fast-forward pulse generator.

FIG. 4 is a time chart showing the operation of FIG.

FIG. 5 is a circuit diagram of a normal pulse generation unit and a motor pulse selection circuit unit.

FIG. 6 is a time chart showing the operation of FIG.

FIG. 7 is a circuit diagram of a pulse control circuit unit.

8 is a time chart showing the operation of FIG.

FIG. 9 is a circuit diagram of an embodiment corresponding to claim 2.

FIG. 10 is a time chart showing the operation of FIG.

FIG. 11 is a circuit diagram of an embodiment corresponding to claim 3;

FIG. 12 is a circuit diagram of an embodiment corresponding to claim 4.

FIG. 13 is a time chart showing the operation of FIG.

FIG. 14 is a circuit diagram of an embodiment corresponding to claim 5;

FIG. 15 is a time chart showing the operation of FIG.

[Explanation of symbols]

 1 Power Generation Mechanism 2 Charging Control Circuit 3 Capacitor 4 Power Supply Voltage Detection Circuit 5 Fast Forward Pulse Forming Circuit 6 Normal Hand Movement Pulse Forming Circuit 7 Motor Pulse Selection Circuit 8 Motor Drive Circuit 9 Display Mechanism 10 Switch 11 Switch Input Control Circuit 12 Pulse Control Circuit 13 Oscillation Circuit 14 Divider circuit

Claims (5)

[Claims] 1. A power source section comprising a secondary power source, a power generation means for storing electricity in the secondary power source, a charging control circuit for controlling charging of the secondary power source, and a display for displaying time information by a pointer. A mechanism, a motor drive circuit for driving the pointer, a switch input means by an external operation, a power supply voltage detection means for outputting a voltage display signal according to an output voltage value of the power supply section, and a voltage display signal according to the voltage display signal. A fast-forward pulse creating circuit for creating a fast-forward pulse number, and stopping the input of the normal time display signal to the drive circuit by the switch input signal by the external operation, and inputting the fast-forward pulse signal to the drive circuit A motor pulse selection means for driving the pointer by the number of the rapid-forward pulses corresponding to the output voltage value of the power supply unit and performing a voltage display operation according to the moving amount, The coincidence between the number of fast-forwarding pulses corresponding to the voltage display signal and the number of pulses of the clock signal from when the switch input signal is input is detected, and the pointer of the power source is displayed after fast-forwarding and displaying the pointer. A pulse control circuit for returning to the time, and when the pulse control circuit inputs a switch input signal by an external operation before the pointer returns to the current time, the power supply voltage detecting means performs the voltage display operation again, and The pulse control circuit for detecting the coincidence between the number of pulses of the voltage display signal and the number of pulses of the clock signal has means for adding the number of pulses of the voltage display signal according to the output voltage value of the power supply unit. A featured analog electronic watch. 2. A counter circuit that counts a switch input signal by an external operation, and a pointer is driven by the switch input signal to fast-forward and drive to display the power supply voltage, and then the counter is reset when the pointer returns to the current time by a pulse control circuit. 2. The analog electronic timepiece according to claim 1, further comprising a reset circuit for resetting and a means for inhibiting the input of the switch input signal when the counter circuit for the switch input signal reaches a predetermined number of times. 3. A means for prohibiting the input of the switch input signal for a predetermined period from the input of the switch input signal by an external operation to the fast-forwarding drive of the pointer by the power supply voltage detecting means to finish the display of the power supply voltage. The analog electronic timepiece according to claim 1 or 2, which is characterized in that. 4. Means for detecting that the switch input signal by an external operation is a switch input signal for shifting from the normal time display of the pointer to the first fast-forward drive operation, and the switch input when the detection is made. 4. The analog electronic timepiece according to claim 1, further comprising a control means for prohibiting the start of the fast forward drive of the pointer by the power supply voltage detection means from the input of the signal for a predetermined time. 5. A counter circuit that counts a predetermined time after the pointer is fast-forwarded by the input of a switch input signal by an external operation to end the power supply voltage display, and the predetermined time ends after the switch input signal is input. 5. The analog electronic timepiece according to claim 1, further comprising a control means for prohibiting the input of the switch input signal during the period up to.