JPH0580085A - Voltage detecting circuit and semiconductor storage device equipped with the said circuit - Google Patents

Abstract

PURPOSE:To detect whether the state of a low or high voltage of a prescribed potential is held for a prescribed time or not, regarding a semiconductor storage device for setting some test mode by use of the result of operation of a voltage detecting circuit (detection of a logical ultra-low or ultrahigh voltage). CONSTITUTION:Circuits 2 to 7 detecting that a voltage to be detected changes to a level having a difference of a prescribed level or above from a reference voltage, circuits 8 to 15 and C1 to C3 delaying this state of detection of the change of the level by a prescribed time, and circuits 16 to 19 determining whether the state of detection of the change of the level is held until the prescribed time passes, are provided. When the state of detection of the change of the level is held for the prescribed time or longer, a determination signal SUPZ indicating the detection of the change of the level is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detection circuit,
In particular, the present invention relates to a semiconductor memory device that sets a certain test mode using the result of the detection circuit (detection of logical ultra-low voltage or ultra-high voltage).

[0002]

In a conventional known semiconductor memory device, the test mode typically WCBR (W rite-enable,
C olumn address strobe, B efore R ow address strob
e) It will be entered by the method, but apart from that, this WC
There is also a system in which the BR system is used in combination with the detection result of the above-mentioned ultra-low voltage (or ultra-high voltage) to have a function of entering a different test mode.

This type of semiconductor memory device includes the above-mentioned voltage detection circuit, but in the conventional technique, it is a super low vo
It only had the ability to detect ltage or super high voltage. FIG. 5 shows the configuration of a low voltage detection circuit as an example of a conventional type. In the figure, 1 is an active low write enable signal (WE)
Is applied to the signal pad, Vcc indicates a high-potential power supply line, and a resistor R, p-channel transistors 2, 3, 4 and an n-channel transistor 5 are connected in series between them. The gate of each transistor is connected to the drain. The connection point (node B) of the transistors 4 and 5 is connected to the input terminal of a CMOS inverter (p-channel transistor 6 and n-channel transistor 7) connected between the power supply lines Vcc and Vss.

In this structure, when the potential of the pad 1 is lowered from the level of the voltage Vss to a level lower than the threshold level 3Vth of the three stages of the transistors 2 to 4 by 3Vth or less, the level of the node B is "H" level (Vcc-Vth = changes from V _II level) to "L" level, the potential of the inverter (output end of the 6, 7) (node C) in response to this change to the "H" level from the "L" level. In this case, the potential of the node C holds the "H" level as long as the low voltage state (<Vss-3Vth) is held.

[0005]

As described above, the conventional semiconductor memory device has only the function of detecting a logical ultra-low voltage or ultra-high voltage, and therefore spike noise is generated via an external pin, for example. Is mixed with the voltage detection circuit, a disadvantage occurs. Hereinafter, this inconvenience will be described with reference to the operation timing chart of FIG.

Now, when the semiconductor memory device is in the entry cycle of the WCBR system and spike noise is input to the voltage detection circuit (pad 1 in FIG. 5), the noise shown in FIG.
As shown in, the potential of the node A is temporarily low voltage (<
Vss-3Vth) level, and in response thereto, the levels of the node B and the node C are "L" level,
Changes to "H" level.

However, since such noise is transient, when the potential of the node A returns to the original level of Vss, the levels of the node B and the node C are correspondingly changed to the original "H" level and "H" level, respectively. Return to L "level. Thus, if spike-like noise enters the voltage detection circuit during the entry cycle of a certain test mode, the detection result (low voltage detection state) becomes abnormal, and the test mode is based on this detection result. There is a possibility that the semiconductor memory device for which the above setting is entered may enter another test mode different from the initial test mode. In this case, there is an inconvenience that the test corresponding to the initial test mode cannot be performed.

In view of the above problems in the prior art, a main object of the present invention is to provide a voltage detection circuit capable of detecting whether the low voltage or high voltage state of a predetermined potential is maintained for a certain time or longer. Especially. Another object of the present invention is to enter a semiconductor memory device having the above voltage detection circuit into a different test mode from the initial test mode even when spiked noise is mixed in during the entry cycle of the WCBR method. It is an object of the present invention to provide a semiconductor memory device which can prevent a test from being performed and can normally perform a test according to each test mode.

[0009]

In order to solve the above problems, according to one aspect of the present invention, there is provided a circuit for detecting that a detected voltage has changed from a reference voltage to a level having a difference of a certain level or more. A circuit for delaying the level change detection state for a predetermined time, and a circuit for determining whether or not the level change detection state is held until the predetermined time elapses. There is provided a voltage detection circuit characterized by outputting a determination signal instructing detection of the level change when held.

In the above structure, the determination signal may be invalidated when the level change detection state is released before the predetermined time has elapsed. According to another aspect of the present invention, there is provided a semiconductor memory device including the voltage detection circuit. This semiconductor memory device determines a circuit that determines whether a write enable signal and a column address strobe signal are input before a row address strobe signal, and determines whether to shift to a test mode based on the result of the determination. And a circuit for performing a predetermined test mode when the determination signal is output from the voltage detection circuit, and a different test mode when the determination signal is invalid. ..

[0011]

According to the above configuration, when the detected voltage changes from the reference voltage to a level having a difference of a certain level or more, it is determined whether the level change detection state is held for a predetermined time or more, and the determination is made. Based on the result, when the level change detection state is held for a predetermined time or more, a determination signal for instructing the level change detection is output.

Therefore, when the voltage to be detected changes to a certain level (low voltage or high voltage), it is possible to detect whether the state is held for a certain period of time or more by validating / invalidating this judgment signal. You can In a semiconductor memory device including such a voltage detection circuit, the WC
When spike-like noise is mixed in during the entry cycle in the BR method, the determination signal is invalidated, so that the semiconductor memory device erroneously enters another test mode different from the initial test mode. Can be prevented. As a result, it is possible to normally perform the test according to each test mode.

The details of other structural features and operations of the present invention will be described using the embodiments described below with reference to the accompanying drawings.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the circuit configuration of a low voltage detecting circuit as an embodiment of the present invention. In the figure, 1 is a signal pad to which an active-low write enable signal (WE) is applied, Vcc is a high-potential power supply line, and a resistor R and p-channel transistors 2 and 3 are connected in series between them. 4 and n-channel transistor 5 are connected. The gate of each transistor is connected to the drain. The connection point (node B) between the transistors 4 and 5 is
Connected to the input terminal of a CMOS inverter (p-channel transistor 6 and n-channel transistor 7) connected between a power supply line V _II (which is an internal power supply voltage and has a level of Vcc-Vth) and a power supply line Vss. Has been done.

The signal at the output terminal (node C) of the inverter (6, 7) is input to the gates of the p-channel transistor 16 and the n-channel transistor 17 and connected between the power supply lines V _II and Vss, respectively. 4 stage CM
It is input to the gates of the n-channel transistor 18 and the p-channel transistor 19 via the OS inverter in sequence (node G). Each CMOS inverter has a p-channel transistor 8, 1 like the inverter (6, 7).
0, 12, 14 and n-channel transistors 9, 11, 13, 1
MOS capacitors C1 to C3 for delaying the signal level are connected between the respective inverters (node D, node E, node F).

[0016] transistor 16, the transistor 17 and transistor 18 are connected in series between the power supply line V _II and Vss, each drain terminal of the transistor 16 and 17 (node H), the power supply line via a transistor 19 V
_It is connected to _II . The level of the node H becomes "H" level when at least one of the levels of the node C and the node G is "L" level, and becomes "L" level only when both levels are "H" level. That is, the transistors 16 to 19 logically form a NAND gate.

The signal at the node H is input to the CMOS inverter (p-channel transistor 20 and n-channel transistor 21) connected between the power supply lines V _II and Vss, and the inverter (20, 21) makes a decision. Signal SU
PZ is output. As will be described later, this determination signal SUPZ is a signal indicating that the potential of the pad 1 (level of the node A) is kept at a level lower than the level of the voltage Vss by a certain level or more, that is, a low voltage. This is a signal instructing detection.

FIG. 2 shows operation timing waveforms of the low voltage detection circuit of this embodiment. First, when the potential of the pad 1 (the level of the node A) drops from the level of the power supply voltage Vss to a level lower than the threshold level 3Vth of three stages of the transistors 2 to 4 by more than 3Vth, the level of the node B changes from "H" level to "L" level. The level of the output terminal (node C) of the inverters (6, 7) changes from "L" level to "H" level.

The "H" level signal of the node C is input to the gates of the transistors 16 and 17, whereby the transistor 16 is cut off and the transistor 17 is cut off.
Turns on. On the other hand, in response to the "H" level signal of the node C, the inverters (8, 9), the inverters (10, 11), the inverters (12, 13) and the output terminals of the inverters (14, 15) (node D, node D, The levels of E, node F, and node G) are sequentially delayed by a predetermined time and are changed to "L" level, "H" level, "L" level, and "H" level. The "H" level signal of the node G is input to the gates of the transistors 18 and 19, whereby the transistor 19 is cut off, the transistor 18 is turned on, and in cooperation with the on operation of the transistor 17, the node H is turned on. Lower the level to "L" level.

Upon receiving this "L" level signal, the output of the inverter (20, 21), that is, the determination signal SUPZ, becomes "H" level. As a result, it is detected that the potential of the pad 1 is kept at a constant level (<Vss-3Vth) for a predetermined time or longer. As described above, according to the configuration of this embodiment, when the level of the node A drops to a level lower than a certain level, the level of the node B drops to the “L” level, the circuit starts operating, and the level of the node G drops. Of the low voltage (<Vss-3) until the level of the node G changes to the "H" level after the change of "H" level (that is, for a predetermined time).
When the Vth) detection state is maintained, the “H” level determination signal SUPZ that indicates the detection of the low voltage is output.

In this case, when the low voltage detection state is released before a predetermined time elapses, that is, before the level of the node G changes to "H" level (for example, due to spike-like noise mixing or the like). Node C is once at "H" level
When the level is changed to the original “L” level soon after), the determination signal SUPZ becomes invalid (remains at the “L” level).

FIG. 3 shows an example of the configuration of a semiconductor memory device to which the low voltage detection circuit of this embodiment is applied. The illustrated device includes a memory cell array 30, a clock generation circuit 31 for generating a timing clock used internally in response to an active low row address strobe signal RASX and a column address strobe signal CASX, respectively, and a column. An inverter 32 responding to the address strobe signal CASX, an AND gate 33 responding to the output of the inverter and the clock from the clock generating circuit 31, and another timing clock used internally in response to the output of the AND gate are provided. A clock generation circuit 34 for generating,
A circuit 35 for generating a write signal in response to a clock from the clock generation circuit and an external active low write enable signal WEX, and an external address signal A
A circuit 36 for buffering _{0 to} A ₁₁ and predecoding the same, and decoding the row address signal and the column address signal input through the circuit 36,
A row decoder 37 and a column decoder 38 for selecting one of a plurality of word lines and a plurality of bit lines (not shown) in the cell array 30 and a data line corresponding to the selected bit line are connected to the bit line. Column gate
39, a sense amplifier (S / A) and an input / output (I / O) gate 40 for amplifying read data in response to the clock from the clock generation circuit 31 and for exchanging data with the cell array 30. And the low voltage detection circuit 41 of the present embodiment
And a circuit 42 for judging whether or not the write signal (W) is inputted prior to the row address strobe signal RASX, and a judgment for whether or not the column address strobe signal CASX is inputted before the row address strobe signal RASX. circuit
43, a circuit 44 that determines whether to shift to the test mode based on the determination signals of the circuits 41 to 43, a circuit 45 that performs data compression based on the result of the determination circuit 44, and a write signal
A data input buffer 46 that buffers the input data D _IN in response to (W), and a buffering of the data from the cell array 30 or the compressed data from the data compression circuit 45 in response to the clock from the clock generation circuit 34. And a data output buffer 47 that outputs the output data D _OUT .

FIG. 4 shows an example of the configuration of the test decision circuit 44. The circuit shown includes a p-channel transistor 51 whose source is connected to the power supply line V _II and which responds to the CBR determination signal CBRZ, and a p-channel transistor 52 whose source is connected to the drain of the transistor and which responds to the WBR determination signal WBRZ. , A p-channel transistor 53 whose source is connected to the drain of the transistor and which responds to the determination signal SUPZ, and the drain of the transistor and the power supply line Vss
N-channel transistor 54 which is connected between the drains of the transistors 53 and 54 and the power supply line Vss and which is connected to the n-channel transistor 54 and which responds to the determination signal SUPZ and which is connected to the WBR determination signal WBRZ.
Connected between the drains of the transistors 53 and 54 and the power supply line Vss, and the n-channel transistor 56 responsive to the CBR determination signal CBRZ, and the power supply lines V _II and Vss. And a CMOS inverter (p-channel transistor 57 and n-channel transistor 58) that outputs a test mode determination signal TS in response to signals at the drain ends of the transistors 53 and 54.

In this configuration, the CBR determination signal CBRZ and the WBR determination signal WBRZ are at "L" level and the determination signal SU
When PZ is at "L" level (that is, when the above-mentioned low voltage detection state is not held for a predetermined time or longer due to spike noise mixing, etc.), the signals at the drain ends of the transistors 53 and 54 are " Then, the n-channel transistor 58 of the final stage CMOS inverter is turned on, and the test mode determination signal TS is pulled down to the "L" level. In this case, control is performed so that the device does not shift to the test mode.

On the other hand, when the low voltage detection state is maintained for a predetermined time or more, that is, when the determination signal SUPZ is at the "H" level, the transistor 54 is turned on to turn on the p signal.
The channel transistor 57 is turned on, and the test mode determination signal TS becomes "H" level. This "H" level signal TS indicates that this device shifts to the test mode.

In the present embodiment, the determination signal SUPZ for instructing low voltage detection is output when the reference voltage is held at a low potential (<Vss-3Vth) below a certain level for a predetermined time or longer. The form of voltage detection is not limited to this. As is clear from the gist of the present invention, for example, when the reference voltage is held at a high potential of a certain level or higher for a predetermined time or longer, a determination signal for instructing high voltage detection may be output.

[0027]

As described above, according to the voltage detection circuit of the present invention, when the reference voltage changes to a certain level of low voltage or high voltage, it is determined whether or not the state is maintained for a certain period of time or longer. Can be detected. In a semiconductor memory device including such a voltage detection circuit, the WCB
Even if spike-like noise is mixed in during the entry cycle in the R method, there is no need to enter another test mode different from the initial test mode, and no malfunction occurs. Thereby, the test according to each test mode can be normally performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a low voltage detection circuit as an embodiment of the present invention.

FIG. 2 is an operation timing chart of the circuit of FIG.

3 is a block diagram showing a configuration of a semiconductor memory device to which the low voltage detection circuit of FIG. 1 is applied.

FIG. 4 is a circuit diagram showing a configuration example of a test determination circuit in FIG.

FIG. 5 is a circuit diagram showing a configuration of a low voltage detection circuit as an example of a conventional type.

FIG. 6 is an operation timing chart for explaining a problem of the circuit of FIG.

[Explanation of symbols]

2-4, 6, 8, 8, 10, 12, 14, 16, 18, 20 ... P-channel transistors 5, 7, 9, 11, 13, 15, 17, 19, 21 ... N-channel transistors C1-C3 ... MOS capacitors R ... Resistor SUPZ ... (Low voltage detection instruction) judgment signal Vss ... Reference voltage 41 ... Low voltage detection circuit 42 ... WBR judgment circuit 43 ... CBR judgment circuit 44 ... Test judgment circuit CASX ... Column address strobe signal RASX ... Row Address strobe signal WEX… Write enable signal

Claims (4)

[Claims] 1. A circuit (2) for detecting that the detected voltage has changed from a reference voltage to a level having a difference of a certain level or more.
~ 7, R) and a circuit (8) for delaying this level change detection state for a predetermined time.
˜15, C1 to C3) and a circuit (16 to 19) for determining whether or not the level change detection state is held until the predetermined time elapses, and the level change detection state is the predetermined time or more. A voltage detection circuit characterized by outputting a determination signal (SUPZ) for instructing detection of the level change when the voltage is held. 2. The voltage detection circuit according to claim 1, wherein the determination circuit invalidates the determination signal when the level change detection state is released before the predetermined time elapses. circuit. 3. A circuit for holding the level change detection state comprises a plurality of stages of CMOS inverters connected in series (8,
9. The voltage detection circuit according to claim 2, further comprising: 9; 10,11; 12,13; 14,15), wherein the predetermined time is set according to an operation delay time of the CMOS inverter. 4. A semiconductor memory device equipped with the voltage detection circuit according to claim 2, wherein a write enable signal (WEX) and a column address strobe signal (CAS) precede the row address strobe signal (RASX).
X) is input to determine whether the circuit (42, 43), and a circuit (44) for determining whether to shift to the test mode based on the result of the determination, the voltage detection circuit The semiconductor memory device is characterized in that it shifts to a predetermined test mode when the determination signal is output from the device and shifts to another test mode when the determination signal is invalid.