JPH0578951B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a temperature compensation circuit that compensates for changes in output sensitivity due to increases in temperature of a semiconductor converter.

[Conventional technology]

Conventionally, a pressure transducer using a semiconductor piezoresistive element is well known as a semiconductor transducer. The gauge factor of the semiconductor piezoresistive element generally exhibits a negative temperature coefficient, and the pressure-to-electrical conversion sensitivity of a converter made of a bridge circuit including the semiconductor piezoresistive element decreases as the ambient temperature rises. Conventionally, as a temperature compensation circuit at an integrated level to compensate for this decrease in sensitivity, (1) the negative temperature coefficient of the forward voltage V _BE between the base and emitter of a bipolar transistor is utilized;
A temperature compensation circuit that increases the bridge excitation voltage linearly with temperature rise by subtracting a voltage proportional to V _BE from the power supply voltage (IEICE Technical Report ED80-20); (2) Current density The difference in base-emitter voltages of different bipolar transistors, △V _BE , is proportional to absolute temperature (IEEE J.Solid-State Circuits, Vol. 6) ,
1971, pp. 2-7) to give a positive temperature coefficient to the bridge excitation voltage (Sensors and Actuators, Vol. 4, 1983)
2013, pp. 63-69). Both of the above two examples use bipolar integration technology. However, the goal of integrated converters is to make them multi-functional and intelligent, and the integrated circuit technology to achieve these goals is as follows:
MDS technology is superior to bipolar technology. In other words, future integrated converters will have not only a temperature compensation function, but also an amplification function, multiplex function, on-chip arithmetic processing function, and digital interface with a computer on the same substrate as the semiconductor sensing element. It is required to be equipped with A/D conversion and digital signal processing functions, etc., to make it possible. These requests include:
MOS integration has a proven track record in the field of analog/digital hybrid circuits, including switch capacitor circuits, analog switches, A/D conversion microprocessors, etc., and enables lower power consumption and larger scale integration than bipolar technology. Circuit technology is suitable.

However, all known integrated temperature compensation circuits are based on bipolar integration, and are fundamentally incompatible with the MOS integration process.

In order to solve the above problems, we developed a temperature compensation circuit with a configuration suitable for MOS integration (Japanese Patent Application No.
No. 187633 (Japanese Unexamined Patent Publication No. 61-66106)) was considered.
FIG. 2 shows the configuration of the temperature compensation circuit. In the figure, 100 indicates semiconductor piezoresistance elements 1, 2, 3, 4.
5 is a reference voltage generation circuit,
6 is an operational amplifier, 7 is a resistor, and 8 is a temperature-sensitive diffused resistor having a larger positive temperature coefficient than the resistor 7.
In this circuit, the resistor 7 and the temperature-sensitive diffused resistor 8 form a negative feedback loop that returns part of the output voltage of the operational amplifier 6 to the inverting input terminal. Operational amplifier 6
The circuit including the reference voltage generating circuit 5 is an inverting circuit for the output voltage of the operational amplifier 6, and the bridge circuit 100 is excited by the output voltage of the operational amplifier 6.

Therefore, assuming that the resistance values of the resistor 7 and the temperature-sensitive diffused resistor 8 are _R1 and _R2 , and the output voltage of the reference voltage generation circuit 5 is Vref, the temperature coefficient of the resistor 7 can be considered to be virtually insensitive to temperature. Assuming that Vexc is reasonably small, the output voltage of the operational amplifier 6, that is, the excitation voltage Vexc supplied to the bridge circuit 100 , is given by the following equation.

Vexc=-R ₂ R ₁・Vref=-R ₂ (O) R ₁・(1+αt)・Vref Here, R ₂ (O) and α are the resistance value of the temperature-sensitive diffused resistor 8 at a certain reference temperature and Temperature coefficient of resistance, t
is the temperature transition from the reference temperature. As is clear from the above equation, according to the circuit shown in FIG. 2, a positive temperature coefficient based on the temperature coefficient α of the temperature-sensitive diffused resistor 8 can be given to the excitation voltage Vexc of the bridge circuit 100, and the piezoresistance coefficient The negative temperature coefficient of the pressure-to-electrical conversion sensitivity of the bridge circuit 100 based on the negative temperature coefficient can be compensated for.

In the circuit shown in FIG. 2, in order to make the temperature coefficient of pressure-electrical conversion sensitivity zero, the temperature coefficient of the bridge excitation voltage, that is, the resistance temperature coefficient α of the temperature-sensitive diffused resistor 8 must be
(a positive value) should be selected to be equal to the temperature coefficient of the piezoresistance coefficient of the semiconductor piezoresistance elements 1 to 4 constituting the bridge circuit 100. Generally, this is achieved by appropriately controlling the impurity concentrations of the regions constituting the semiconductor piezoresistive elements 1 to 4 and the temperature-sensitive diffused resistor 8, respectively. In the case of a diffused resistor consisting of a p-type impurity region formed on an n-type silicon substrate, the surface impurity concentration is 3×10 ¹⁸ and 2×10 ²⁰ cm ^-3
In the vicinity of , the absolute values of the temperature coefficient of resistance (positive value) and the temperature coefficient of piezoresistance coefficient (negative value) become equal. Therefore, if the surface impurity concentration is selected to be on the upper surface, the temperature-sensitive diffused resistor 8 for temperature compensation can be manufactured in the same process as the semiconductor piezoresistive elements 1 to 4.

Reference voltage generation circuit 5 used in the circuit shown in Fig. 2
A circuit method for detecting the difference in threshold voltage between an enhancement-type MOSFET and a depletion-type MOSFET (IEEE J.Solid-State Circuits), Volume 13, 1978 Year,
(pages 767 to 774), it can be manufactured using a MOS integration process, and in conjunction with this, an operational amplifier 6, a temperature-sensitive diffused resistor 8, and a semiconductor piezoresistive element 1 to
By integrating 4 on the same semiconductor substrate
A MOS-integrated temperature compensation circuit is constructed.

[Problem that the invention seeks to solve]

The conventional example of a temperature compensation circuit suitable for MOS integration has been described above, but this circuit is not suitable for supplying large load current because the bridge circuit 100 consisting of semiconductor piezoresistive elements 1 to 4 and the temperature-sensitive diffused resistor 8 are not suitable for supplying large load current. Since this becomes a load on the operational amplifier 6, there is a drawback that the resistance values of the semiconductor piezoresistive elements 1 to 4 and the temperature-sensitive diffused resistor 8, that is, the length of the diffused resistor cannot be made small. In the case of the most widely used diaphragm pressure transducer, the pressure-to-electrical conversion sensitivity significantly decreases with the length of the semiconductor piezoresistive elements 1 to 4, so an increase in the resistance length leads to a significant deterioration of the sensitivity. Further, since the temperature-sensitive diffused resistor 8 is arranged in a narrow thick region around the diaphragm which is a pressure-insensitive part, an increase in the resistance length causes difficulty in pattern arrangement. A way to avoid these problems is to increase the size of the output stage of the operational amplifier 6 to increase its load capacity, but increasing the size of the output stage affects the previous stage and deteriorates the frequency characteristics of the entire operational amplifier. To prevent this, it is necessary to further increase the size of the front stage, and as a result, the power consumption and occupied area of the operational amplifier significantly increase.

An object of the present invention is to provide a temperature compensation circuit that is suitable for MOS integration and eliminates the drawbacks of the prior art described above.

[Means for solving problems]

In order to achieve the above object, the present invention provides a reference voltage generation circuit, an operational amplifier whose non-inverting side input terminal is grounded, an FET having a source follower configuration where the output terminal of the operational amplifier is connected to the gate, and the the inverting side input terminal of the operational amplifier, the output terminal of the reference voltage generation circuit, and the source follower configuration.
a resistor connected between the source of the FET and a temperature-sensitive diffused resistor having a larger positive temperature coefficient than the resistor;
A bridge circuit consisting of a semiconductor piezoresistance element having a negative temperature coefficient is connected to the source of the FET.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a diagram showing an embodiment of the present invention.
In the figure, 100 is a bridge circuit consisting of semiconductor piezoresistance elements 1, 2, 3, and 4 as in the configuration shown in FIG. 2, 10 is a reference voltage generation circuit, 20 is an operational amplifier whose non-inverting side input terminal is grounded, and 30 11 is a resistor connected between the output of the reference voltage generation circuit 10 and the inverting input terminal of the operational amplifier 20, and 12 is the source of the FET 30. The bridge circuit 100 as a detection circuit has a drain connected to the power supply terminal 13.
It is excited by the output of FET 30 in a source follower configuration connected to.

In this embodiment, the resistor 11 and the temperature-sensitive diffused resistor 12 respectively correspond to the resistor 7 and the temperature-sensitive diffused resistor 8 in FIG. A positive temperature coefficient based on the temperature coefficient of the temperature-sensitive diffused resistor 12 is given to the voltage. As the resistor 11, for example, a metal film, thick film, or thin film resistor with a small temperature coefficient that can be considered as a virtually temperature-insensitive resistor is used.
As the temperature-sensitive diffused resistor 12, a diffused resistor having a larger positive temperature coefficient than the resistor 11 and formed, for example, in a pressure-insensitive portion on the same substrate as the semiconductor piezoresistive elements 1 to 4 can be used.

The feature of this embodiment is that the bridge circuit 100 has a source follower configuration FET 30 rather than the operational amplifier 20.
The point is that it is excited through . That is, the conventional temperature compensation circuit shown in FIG.
However, in this embodiment, the bridge circuit 100 is not connected directly to the output of the operational amplifier 20 , but instead is connected directly to the output of the operational amplifier 20, using a FET with a source follower configuration.
Its configuration has been modified to be excited via 30.

According to the configuration of this embodiment, the bridge circuit 100
and the temperature-sensitive diffused resistor 12 has a source follower configuration.
The source follower is loaded by FET30,
The load on the operational amplifier 20 is simply the gate capacitance of the FET 30. Since there is no resistive load and there is only a capacitive load, the power consumption of the operational amplifier 20 can be significantly reduced. Furthermore, in the circuit shown in Fig. 2, one MOSFET of the output stage of the operational amplifier 6 consisting of an inverter or a source follower is connected in parallel with the bridge circuit 100 and the temperature-sensitive diffused resistor 8, which are the loads, so that the other MOSFET is connected in parallel. It was necessary to flow a current equal to the sum of the load current and the operating point current, but in this example, FET3 of the source follower configuration was used.
0 only needs to bear a current equal to the load current. Therefore, the power consumption of the entire circuit can be significantly reduced.

Therefore, according to this embodiment, without consuming a large amount of power or occupying a large area,
All the drawbacks of the above conventional technology have been completely eliminated,
An extremely useful temperature compensation circuit suitable for MOS integration is obtained.

Although the case of a pressure transducer using a semiconductor piezoresistive element has been described above, the present invention is applicable not only to a pressure transducer but also to a semiconductor transducer using a semiconductor sensing element that shows a change in resistance value in response to a change in a detection target. It can be widely applied to temperature compensation circuits.

〔Effect of the invention〕

As described above, according to the present invention, all the drawbacks of the above-mentioned conventional techniques are eliminated, and an extremely useful temperature compensation circuit suitable for MOS integration is realized. The temperature compensation circuit according to the present invention contributes to making the semiconductor converter intelligent by combining it with a microcomputer, and its effects are significant.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing a conventional example of a temperature compensation circuit for a semiconductor converter. 100... Bridge circuit, 1, 2, 3, 4...
Semiconductor piezoresistive element, 10... Reference voltage generation circuit, 20... Operational amplifier, 11... Resistor, 12...
…Temperature-sensitive diffusion resistance, 30…Source-follower configuration
FET.

Claims (1)

[Claims] 1 A source follower configuration including a reference voltage generation circuit, an operational amplifier whose non-inverting input terminal is grounded, and an output terminal of the operational amplifier connected to a gate.
an FET, a resistor connected between the inverting input terminal of the operational amplifier, the output terminal of the reference voltage generating circuit, and the source of the FET in the source follower configuration, and a resistor having a positive temperature coefficient larger than the resistor; 1. A temperature compensation circuit comprising: a thermal diffusion resistor; and a bridge circuit comprising a semiconductor piezoresistance element having a negative temperature coefficient and connected to the source of the FET having the source follower configuration.