JPH0578042B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a signal processing device for engine control such as fuel supply amount.

BACKGROUND ART Conventionally, in automobiles and the like, a signal processing device as shown in FIG. 1 has been used to control the amount of fuel supplied so that the engine always performs proper combustion.

In FIG. 1, an A/D (analog/digital) converter 1 is supplied with an analog signal as shown in FIG. 2a. This analog signal is an output signal of a sensor when an engine parameter such as intake negative pressure or cooling water temperature is detected by the sensor. The output signal of the A/D converter 1, that is, the digital signal, is generated by a microprocessor, etc.
The CPU 2 normally responds to timing pulses such as TDC (top dead center) pulses synchronized with the rotation of the engine crankshaft or ignition pulses as shown in Figure 2b. For example, the fuel supply device 4 is controlled by digitally processing the sensor signal.
Note that the timing pulse is supplied to the CPU 2 via the waveform shaping circuit 3.

However, as the number of engine parameters to CPU 2 increases and the number of A/D converters connected to CPU 2 increases, there is a limit to the time that CPU 2 can read the output signal of a single A/D converter. The reading speed of the CPU 2 for the output signals of each A/D converter becomes slower. Therefore, the sampling rate of analog signals that represent engine parameters decreases, and CPU2
There was a problem that the accuracy of the read data decreased.

Therefore, after combining multiple input signals, the CPU
It is considered to be supplied to For example, in Japanese Patent Application Laid-Open No. 110326/1983, on/off signals emitted from multiple switches are combined and the combined signal is
It is disclosed that it is supplied to the CPU.

However, although it is easy to synthesize binary signals of the same type such as on/off signals, it is easy to synthesize binary signals such as on/off signals, but it is difficult to synthesize analog signals for engine control whose level changes continuously as described above and timing signals that occur at predetermined timing. Since these are completely different types of signals, it has been difficult to synthesize these signals.

OBJECT OF THE INVENTION An object of the present invention is to obtain the level of the analog signal and the generation time of the timing signal without deteriorating the reading accuracy of the analog signal data for engine control. An object of the present invention is to provide a signal processing device capable of synthesizing generated timing signals.

Configuration of the Invention The signal processing device of the present invention receives and synthesizes an analog signal that indicates the operating state of an engine and is used as a parameter for controlling the engine, and a timing signal that is generated at a predetermined timing, and then supplies the synthesized signal to a central processing means. a signal processing device that outputs the analog signal as it is when no timing signal is generated, and outputs the analog signal at a level sufficiently far from the level variation range of the analog signal when the timing signal is generated; converting means converting the output signal level of the waveform synthesizing means into a digital signal and supplying the digital signal to the central processing means, the central processing means detecting that the value of the digital signal is sufficiently far from the level fluctuation range of the analog signal; The present invention is characterized by having a determining means for determining the time of detection as the time of generation of a timing signal.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 and 4.

As shown in FIG. 3, in the device of the present invention, the waveform synthesis circuit 5 receives an analog signal indicating the operating state of the engine and used as a parameter for controlling the engine, and a timing pulse as a timing signal via the waveform shaping circuit 3. and are supplied.
A CPU 2 is connected to the output end of the waveform synthesis circuit 5 via an A/D converter 1.

In such a configuration, when an analog signal as shown in FIG. 4a and a timing pulse as shown in FIG. 4b are supplied to the waveform synthesis circuit 5, the waveform synthesis circuit 5 outputs the analog signal when no timing pulse is input. When a timing pulse is input, a pulse signal having a peak potential Va sufficiently far from the level fluctuation range of the analog signal is output.
Therefore, the output signal of the waveform synthesis circuit 5 has a waveform as shown in FIG. The CPU 2 determines whether the output data of the A/D converter 1 is data representing the analog level of an analog signal or data representing the generation timing of a timing pulse.

Next, the determination operation of the CPU 2 will be explained with reference to the operation flow diagram of FIG.

The CPU 2 first converts the A/D converter 1 at each predetermined period.
Read the output data Dx (step 11). Next, it is determined whether the output data Dx is equal to the digital value Da corresponding to the potential Ca (step
12). If Dx≠Da, the data Dx is processed as analog signal data (step 13). on the other hand,
If Dx=Da, that point in time is treated as a timing pulse generation timing (step 14).

Note that it is desirable that the CPU 2 performs interpolation calculations from previous and subsequent data in order to compensate for missing data due to pulse signals in the analog signal.

FIG. 6 shows a specific circuit example of the waveform synthesis circuit 5. In Figure 6, the analog signal input terminal
An analog switch 6 is connected to IN ₁ , and the output signal of the waveform synthesis circuit 3, that is, the timing pulse input terminal IN ₂ , is connected to the drive end of the analog switch 6 and the drive end of the analog switch 8 via an inverter 7. has been done. A potential Va is supplied to the analog switch 8, a voltage follower circuit 9 is connected to the output terminals of the analog switches 6 and 8, and the output signal of the voltage follower circuit 9 becomes the output signal of the waveform synthesis circuit 5.

In the waveform synthesis circuit 5 having such a configuration, the analog switch 6 is turned on when no timing pulse is input.
is turned on, analog switch 8 is turned off, and an analog signal is output from voltage follower circuit 9. When the timing pulse is input, analog switch 6 is turned off, analog switch 8 is turned on, and potential Va is output from voltage follower circuit 9.

Effects of the Invention As described above, according to the signal processing device of the present invention,
When a timing signal is not generated, the analog signal is digitized and supplied to the central processing means, and when a timing signal is generated, the analog signal level for engine control is not output as is, but is set to a level sufficiently far from the level fluctuation range of the analog signal. Thereafter, the signal is digitized and supplied to the central processing means, and the central processing means determines that the timing signal is generated when the value of the digital signal is sufficiently far from the level fluctuation range of the analog signal. Therefore, since the generation period of the timing signal is short, the sampling rate of the analog signal does not decrease significantly, so the level of the analog signal can be obtained without deteriorating the accuracy of reading the level of the analog signal, and the timing It is possible to reliably obtain the time when the signal is generated. Furthermore, since the level of the analog signal for engine control and the time of generation of the timing signal can be supplied to the central processing means such as the CPU on the same line, the number of input terminals of the central processing means can be reduced by at least one terminal. can. That is, considering that the number of terminals determines the chip size of an integrated circuit, being able to reduce the number of terminals by even one terminal is a great advantage in terms of miniaturization of the central processing means.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example of a signal processing device, Fig. 2a is an analog signal waveform diagram, Fig. 2b is a timing pulse waveform diagram, and Fig. 3 shows an embodiment of the signal processing device of the present invention. Block diagrams, Figures 4a to 4c are operational waveform diagrams of the circuit in Figure 3, Figure 5 is an operational flow diagram of the CPU in Figure 3, and Figure 6 is a specific circuit example of the waveform synthesis circuit in Figure 3. FIG. Explanation of symbols of main parts, 1...A/D converter,
2...CPU, 3...Waveform shaping circuit, 5...Waveform synthesis circuit.

Claims (1)

[Claims] 1 A signal processing device that receives and synthesizes an analog signal that indicates the operating state of an engine and is used as a parameter for controlling the engine, and a timing signal that is generated at a predetermined timing, and then supplies the synthesized signal to a central processing means, Waveform synthesis means for outputting the analog signal as it is when the signal is not generated, and outputting the analog signal at a level sufficiently away from the level fluctuation range of the analog signal when the timing signal is generated; converting means converting the output signal level into a digital signal and supplying it to the central processing means, the central processing means detecting that the value of the digital signal is sufficiently far from the level fluctuation range of the analog signal; A signal processing device characterized by comprising a determining means for determining the time of detection as the time of generation of the timing signal.