JPH0575135A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make it possible to attain a low voltage program by installing a drill-shape pointed tip to a substrate which faces a tunnel window. CONSTITUTION:When a drain diffusion layer region 5 (DD) is grounded on a data write-side and positive high voltage is applied to a control gate (CC), the electrons are injected into a floating gate (FG) 2 from a projected part of an Si semiconductor substrate (SB) 10 by way of a tunnel oxide film 4. On an erase side, when the CG 1 is grounded with high voltage, the electrons are extracted from the FG 2. The projected part 9 can be formed with an Si anisotropic etching solution, such as KOH, for example. When writing or erasing, a potential difference is generated between the projected part and the FG 2 capacitance coupled with the CG 1. During the generation of the potential difference, the electric lines of force extended from the FG 2 are concentrated into the projected part 9 of an injector where the electric field is locally intensified so that the electrons may be tunneled at a low voltage, which makes it possible to attain a low voltage program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device as an EEP type or EP type ROM having a floating gate, in which writing and erasing can be performed at a lower voltage than before.

[0002]

2. Description of the Related Art In the most basic floating gate type EEP type ROM, a tunnel window is provided between a diffusion region on the data line side and a floating gate to take in and out electrons. Since the tunnel oxide film of the tunnel window is uniform, the electrons flow uniformly in the plane of the tunnel window. Further, as a method of improving the transfer of electrons into and out of the floating gate, a method of increasing the injection electric field by utilizing the unevenness of the polycrystalline Si surface has been conventionally proposed, but in this method, the unevenness of the surface of the floating gate is uneven. Is used to extract charges to another Poly-Si wiring, or a wiring for injection having unevenness is formed under the floating gate and the wiring is injected from the wiring, which causes various problems. Was left practically.

That is, in the conventional device, it is usually necessary to apply a high voltage of 20 V or more to the control gate in order to inject electrons into the floating gate. Therefore, the device structure is complicated and the device area is reduced. It needs to be large, and
The example using the unevenness of Poly-Si also has drawbacks such as increase in wiring and complexity of the circuit and increase in element area.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides an EEP type ROM of this type,
By achieving a low-voltage program, the memory cell, which had become large because it required a high voltage for programming,
To reduce the size of memory cells and simplify the peripheral circuits,
Another object is to increase the reliability of the device by low voltage programming.

[0005]

[Means for Solving the Problems] To achieve the above object,
In order to achieve low voltage programming, the present invention provides at least one or more pyramidal or trapezoidal protrusions on the surface of the Si semiconductor substrate corresponding to the tunnel window region to form protrusions and recesses, and The conventional defect is eliminated by concentrating the electric field in the tunnel oxide film at the time of programming at the convex portion.

[0006]

As described above, when the conical or trapezoidal convex portion is formed so as to project on the surface of the tunnel window of the Si semiconductor substrate, the width of the oxide film to be tunneled at the tip of the convex portion becomes narrower. The electric field at that portion is concentrated and the effect of facilitating tunneling at the tip portion is derived, and writing / erasing can be performed at a lower voltage than before. On the other hand, even if the tunnel oxide film is thickened, the same writing and
Since the erasing efficiency can be obtained, a good manufacturing margin can be obtained and a highly reliable oxide film can be formed with this type of device.
Further, since the capacity of the tunnel window portion can be reduced, the effect that the voltage applied to the tunnel oxide film can be increased can be obtained.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor memory device according to the present invention will be described in detail below with reference to the drawings. In FIG. 1, 1
0 is a Si semiconductor substrate of an EEP type ROM having a floating gate, 1 is a control gate, 2
Is a floating gate, 3 is a tunnel window,
4 is a tunnel oxide film, 5 is a drain diffusion layer, 6 is a source diffusion layer, and 9 is at least one or more pyramids or trapezoids formed by etching on a portion of the upper surface of the semiconductor substrate 10 facing the tunnel window 3. A convex portion of the shape, the tip of the convex portion being located closest to the floating gate.

When the EEP type ROM having the above-mentioned structure is used, the drain diffusion layer region 5 is grounded on the data write side, and when a positive high voltage is applied to the control gate, it is formed in the tunnel window region. S
Electrons are injected from the convex portion of the i semiconductor substrate into the floating gate 2 through the tunnel oxide film 4. On the erase side, contrary to the write side, when the control gate 1 is grounded by a high voltage in the drain diffusion layer region 5, electrons are extracted from the floating gate 2. In the present embodiment, S facing the tunnel window area
The convex portion formed on the surface of the i semiconductor substrate may be, for example, KOH.
It can be formed with a Si anisotropic etching solution such as.
When writing or erasing, control the Si convex portion 9 and
Floating gate 2 capacitively coupled to gate 1
And a potential difference is generated. At this time, the lines of electric force extending from the floating gate are concentrated on the convex portion of the injector, and the electric field is locally increased, so that electrons are tunneled at a lower voltage and a low voltage program is achieved.

That is, according to the present invention, in order to achieve low voltage programming, a convex portion is provided on the surface of the Si semiconductor substrate in the tunnel window region, and the electric field in the tunnel oxide film during programming is concentrated on the tip portion of the convex portion. Therefore, if unevenness is formed on the surface of the tunnel window Si, the electric field at the convex portion is increased, and tunneling becomes easier at that portion.

Therefore, the EEP type RO according to the present invention
M achieves a low voltage program for a memory cell that has become large because it requires a high voltage for programming, thereby reducing the size of the memory cell and simplifying the peripheral circuit, and improving the reliability of the device. This has the advantage that the performance can be enhanced by a low voltage program.

As described above, the present invention has a simple structure in which the semiconductor substrate facing the tunnel window is provided with a convex portion having a sharp tip such as a pyramid, and when writing to or erasing from the floating gate. By the convex portion, the electric field of the tunnel oxide film generated when a voltage is applied is locally enhanced, and tunneling can be performed at a voltage lower than usual,
The intended purpose can be achieved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of an EEP type ROM according to the present invention.

FIG. 2 is an enlarged view of a part of FIG.

FIG. 3 is a top view of FIG.

[Explanation of symbols]

 1 Control Gate 2 Floating Gate 3 Tunnel Window 4 Tunnel Oxide Film 5 Drain Diffusion Layer 6 Source Diffusion Layer 7 Interlayer Film 8 Electric Force Line 9 Si Convex 10 Semiconductor Board

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication G11C 16/04

Claims (1)

[Claims] 1. An EEP-ROM memory cell in which a floating gate is provided on a semiconductor substrate, wherein at least one pyramid or platform protruding from the surface of the semiconductor substrate facing a tunnel window portion of the floating gate. A semiconductor memory device having a conical convex portion.