JPH0575039A - Semiconductor mos integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate a malfunction resulting from power supply noises at a time when a semiconductor MOS integrated circuit is interfaced with a TTL, and to enable even operation at high speed. CONSTITUTION:A plurality of exclusive power terminals 4, 5, 7, 8 connected only to a power supply system driving the input buffer of a semiconductor MOS integrated circuit are arranged, and the diffraction of the internal power supply system noises of the integrated circuit to the input buffer is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an input terminal, an output terminal,
Semiconductor MOS having either a bidirectional terminal or a power supply terminal
Related to integrated circuits.

[0002]

2. Description of the Related Art In a conventional semiconductor MOS integrated circuit having any one of an input terminal, an output terminal, a bidirectional terminal, and a power supply terminal, a power supply system such as an input buffer directly connected to the input terminal or the bidirectional terminal is It was connected to the same power supply system as the internal logic circuit in order to reduce the area of the integrated circuit. For this reason, high integration and high speed have been realized today, so noise from the power supply system spills into the input buffer, and TTL
When a level input signal is applied to the input terminal, a malfunction may occur. Also, the high speed operation of the integrated circuit increases the sensitivity of the input buffer,
At the same time, the sensitivity to noise has increased. For this reason, the input signal of the integrated circuit is set to a signal swinging from VDD to VSS, or the sensitivity of the input buffer is reduced to cope with the speedup of the integrated circuit.

[0003]

[Problems to be Solved by the Invention] However, TTL
The necessity of operating at high speed while interfacing with the MOS integrated circuit is increasing more and more. In the present circumstances,
The delay in the input buffer is compensated by the high-speed operation of the internal logic circuit, but if either one is sacrificed, M
In some cases, there is no choice but to give up the system construction using the OS integrated circuit. An object of the present invention is to eliminate the malfunction of the semiconductor MOS integrated circuit due to the power supply noise at the time of the interface with the TTL, and also to enable the high speed operation.

[0004]

[Means for Solving the Problems] a) Semiconductor M having any of an input terminal, an output terminal, a bidirectional terminal, and a power supply terminal
In the OS integrated circuit, b) a dedicated power supply terminal (VDD terminal) connected to only the power supply system of the P-channel MOS transistor group connected to the input terminal or the bidirectional terminal and the gate through the resistance for static electricity protection, and N A dedicated power supply terminal (VSS terminal) connected only to the power supply system of the channel MOS transistor group is provided, and the VDD terminal and the VSS terminal are provided.
It is characterized in that a plurality of terminals are arranged for each terminal.

[0005]

With the above-described structure of the present invention, noise of the power supply system inside the integrated circuit does not flow into the input buffer.
No malfunction occurs even if a TL level input signal is applied to the input terminal. Also, in response to the demand for high-speed operation of the integrated circuit, other power supply system noises are cut, so the sensitivity of the input buffer can be increased and the input buffer can be operated at high speed, resulting in high-speed operation of the entire integrated circuit. Contribute to.

[0006]

EXAMPLE FIG. 1 shows an example of the present invention. In this embodiment, the input terminals (pads) of the integrated circuit correspond to 1, 2 and 3.
Focusing on 1, the signal input here reaches the input buffer through 50 anti-static resistors and 20, 21 anti-static diodes. Here, P channel MO
S transistor 30 and N channel MOS transistor
It is an input inverter composed of 31. Separate the power supply system of MOS transistors (connected to the power supply pads 4 and 7 with power supply wirings 10 and 11) and the power supply system of the internal circuit (shown by power supply pads 6 and 9) that compose this input inverter. Power pads are located. The power supply noise generated by the internal circuit during operation is
It stops at 6 and 9 and does not affect the input inverter. A conventional example is shown in FIG. 2. In this example, power supply noise generated in the internal circuit propagates through the power supply system of the internal circuit and affects the input inverter. As a result, the input level is TT
In the case of the L level, the input inverter makes a mistake in distinguishing whether the signal is HIGH or LOW due to power supply noise and causes a malfunction. In particular, today, as integrated circuits become larger and faster, power supply noise generated in internal circuits is large, and there is a limit to how much effort can be made to reduce the power supply impedance. As a result, input signals to a large-scale integrated circuit that operates at high speed cannot handle signals other than those that swing VDD and VSS fully. In the present invention, the power supply wiring 10, 11, 12,
Although it is necessary to build 13 and power supply pads 4, 5, 7, and 8, the above problems will be eliminated, and the optimum design of the input inverter can be easily done without considering the influence of power supply noise. Further, it is not necessary to reduce the sensitivity of the input inverter and reduce the operating speed of the input inverter in order to reduce the influence of power supply noise as in the conventional case. Up to now, the method of separating the power supply system of the output buffer from the internal circuit (including the power supply system of the input buffer) in response to the increase in the driving capability of the output buffer has been adopted, but the power supply pad dedicated to the input buffer is used. It has not been designed to be provided. Even with such a design, there has been no problem since the large scale and high speed of the integrated circuit have not been remarkable so far. Although FIG. 1 is limited to the case of three input pads, the present invention can be applied to an integrated circuit having an arbitrary number of input pads. Further, in the present invention, by disposing a plurality of VDD and VSS for driving the input buffer,
A power pad can be placed near the input buffer. As a result, the impedance of the power supply system that drives the input buffer can be reduced, the influence of the power supply noise of other input buffers can be reduced, and the power supply wiring can be simply arranged.

[0007]

As described above, according to the present invention, since the power supply noise generated inside the semiconductor integrated circuit does not sneak into the input buffer, the malfunction due to the power supply noise does not occur even if input at the TTL level. Further, it is not necessary to lower the sensitivity of the input buffer and reduce the operating speed of the integrated circuit in order to reduce the influence of power supply noise as in the conventional case. This enables high speed operation of the integrated circuit. The present invention will become more effective in the future because the higher integration and higher speed of semiconductor integrated circuits are becoming more and more remarkable today.

[Brief description of drawings]

FIG. 1 is a semiconductor MOS integrated circuit diagram showing an embodiment of the present invention in which a power supply system of an input inverter and a power supply system of an internal circuit are separated.

FIG. 2 is a semiconductor MOS integrated circuit diagram of a conventional example.

[Explanation of symbols]

1, 2, 3, 101, 102, 103 ・ ・ ・ Input terminal (input pad) 4, 5, 6, 106 ・ ・ ・ Power supply terminal (V
DD power supply pad 7, 8, 9, 109 ・ ・ ・ Power supply terminal (V
Power supply pad for SS) 10, 11, 12, 13, 14, 15, 114, 115 ・ ・ ・ Power supply wiring 20, 21, 22, 23, 24, 25, 120 ・ ・ ・ Protection diodes 121, 122, 122 for static electricity countermeasures 123,124,125 ・ ・ ・ Protective diodes for static electricity protection 30,32,34,130,132,134 ・ ・ ・ P-channel MOS transistors 31, 33,35,131,133,135 ・ ・ ・ N-channel M
OS transistors 40, 140 ・ ・ ・ Internal circuits 50, 51, 52, 150, 151, 152 ・ ・ ・ Protection resistors for static electricity protection 60, 160 ・ ・ ・ Semiconductor MOS
Integrated circuit

Claims (1)

[Claims] 1. A semiconductor MOS integrated circuit having a) any one of an input terminal, an output terminal, a bidirectional terminal, and a power supply terminal, and b) a gate via the input terminal or the bidirectional terminal and an electrostatic protection resistor. P-channel MO connected to
A dedicated power supply terminal (VDD terminal) connected only to the power supply system of the S transistor group and a dedicated power supply terminal (VSS terminal) connected only to the power supply system of the N-channel MOS transistor group
A semiconductor MOS integrated circuit is provided, in which a plurality of VDD terminals and VSS terminals are provided.