JPH0575025A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the electrostatic breakdown strength of a semiconductor integrated circuit device which has a plurality of power sources or earth terminals. CONSTITUTION:The source and drain terminals of a MOS transistor 107 are connected to a plurality of power sources or earth potential wirings 103 and 104, and the gate terminal is fixed to the potential at which the MOS transistor is cutoff.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a plurality of fixed potential input terminals having the same potential.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device, an increase in current consumption due to an increase in scale, a power supply potential when an output potential changes due to an increase in the number of bits of output terminals, and a noise on a ground potential wiring Various measures have been taken to cope with the increase and the like.

The most effective of these is to provide a power supply terminal, a ground potential supply terminal, or both, to reduce the current load, and to supply the power supply potential wiring or ground generated by some circuits. Noise on the potential wiring has been prevented from affecting other lines.

For example, in the case of the ground potential supply wiring for supplying the ground potential to the data output circuit, when the data output is switched from the high level to the low level, a current flows from the output terminal to the ground potential supply wiring through the data output circuit, and the ground potential is supplied. The ground potential changes due to the parasitic impedance of the supply wiring. At this time, if the ground potential is supplied to another internal circuit through the same ground potential wiring, the potential fluctuation causes noise, and in the worst case, the other internal circuit malfunctions. In order to prevent this malfunction, separate the wiring that supplies the potential to the data output circuit and the wiring that supplies the potential to other internal circuits from the input terminals so that noise in the data output circuit is not transmitted to other circuits. It is effective to do.

[0005]

In such a conventional semiconductor device having a plurality of fixed potential input terminals having the same potential, when the surge voltage of, for example, about 2000 V is applied to the input / output terminals, the normal semiconductor device is provided. There is a problem that the breakdown voltage is inferior as compared with a semiconductor device that does not have a plurality of fixed potential input terminals for the potential.

For example, as shown in FIG. 5, when an electrostatic withstand voltage test is performed on the output terminal, if a surge voltage is applied between the output terminal 501 and the ground terminal 502, only a single ground terminal is applied. In the semiconductor device having the semiconductor device, as shown in FIG. 5, the punch-through current of the output driving MOS transistor 503 connected between the output terminal 501 and the ground potential terminal 502 causes electric charge due to the surge to flow out, and an internal element of the semiconductor device is provided. Is prevented from being destroyed.

However, when a semiconductor device having a plurality of ground potential terminals 401 and 402 as shown in FIG. 4 is subjected to the same electrostatic withstand voltage test as described above, the output terminal 408 and its output terminal 408 are provided as shown in FIG. M driving the output terminal 408
The ground terminal 40 to which the OS transistor 409 is connected
When applied between the ground terminal 402 different from 1, the charge due to the surge is generated by the MOS transistor 4 as in the above example.
Since there is no conductive path due to punch-through of 09, 1
MOS transistor 409 due to surge of about 500V
However, there is a drawback that the gate oxide film or the PN junction of the drain is destroyed.

The ground potential terminal 402 is the ground potential wiring 4
It is connected to the internal circuit 406 via 04. The ground potential terminal 401 is connected to the internal circuit 4 via the ground potential wiring 403.
05 is connected.

An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned drawbacks and prevents internal elements from being destroyed.

[0010]

According to the structure of the present invention, in a semiconductor integrated circuit device having a plurality of fixed potential input terminals of the same potential, the first fixed potential input terminal of the fixed potential input terminals of the same potential is The first fixed potential wiring for supplying a potential to the element of the internal circuit is a source or drain electrode, and the second fixed potential wiring for supplying a potential from the second fixed potential input terminal to the element of the internal circuit is a drain or source electrode. In addition, a transistor in which the gate electrode is connected to a fixed potential that turns off is provided.

[0011]

1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

In FIG. 1, this embodiment is applied to a ground potential wiring. The ground potential is supplied from the first ground potential terminal 101 to the first internal circuit 105 through the first ground potential wiring 103. Similarly, the second ground potential is supplied from the second ground potential terminal 102 to the second internal circuit 106 through the second ground potential wiring 104. Here, the N-type MOS transistor 107 has its source and drain connected to the first ground potential wiring 103 and the second ground potential wiring 104, respectively.

Here, the gate terminal of the N-type MOS transistor 107 is connected to the second ground potential wiring 104 and is normally in the cutoff state, but this gate terminal is connected to the first ground potential wiring 103. However, the same effect can be obtained.

Further, an output terminal driving MOS transistor 1
A source 09 is connected to the first ground potential wiring 103, a drain is connected to the output terminal 103, and a gate is connected to a drive signal 110 generated by an internal circuit, and has a role of driving the output terminal 108 to a low level. .

In the present embodiment, when a surge voltage is applied between the output terminal 108 and the ground potential terminal 102, a punch-through current of the two MOS transistors 109 and 107 has a current conduction path, and the internal It is possible to prevent the device from being destroyed by the surge voltage.

Further, in a normal operation state, the MOS transistor 107 is in a cutoff state, and, for example, the output terminal 108.
Ground potential wiring 103 generated when driving a low level
It is possible to satisfy the original function of preventing the noise of (1) from being transmitted to the other ground potential wiring 104.

FIG. 2 is a circuit diagram of a second embodiment of the present invention, in which an N-type MOS transistor 207 inserted between a first ground potential wiring 203 and a second ground potential wiring 204 is shown. The gate terminal is connected to the substrate potential 211 generated inside the semiconductor device. Other parts are the same as in FIG.

In the case of the present embodiment, one ground potential wiring is M
Even when noise exceeding the threshold voltage of the OS transistor 207 occurs, the original purpose of separating the two ground potential wirings 203 and 204 can be satisfied.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. Here, the fixed potential wirings 303 and 304 both have a power source potential and the two power source potential wirings 303 and 304
By making the MOS transistor 307 inserted between the P type, the input / output terminal 308 and the power supply terminals 301, 3
It is possible to prevent destruction of internal elements due to a surge voltage applied between cells 02.

[0020]

As described above, according to the present invention, in a semiconductor device having a plurality of fixed input terminals of the same potential, the punch-through current under high voltage of the MOS transistor inserted between the fixed input terminals of the same potential causes It has an effect that an excessive voltage is prevented from being applied to the internal elements in the semiconductor device, and the electrostatic withstand voltage which has been conventionally about 1500V can be improved to 2000V or more.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example having a plurality of conventional ground potential terminals.

FIG. 5 is a circuit diagram showing an example having a conventional single ground potential terminal.

[Explanation of symbols]

101, 102, 201, 202, 401, 402, 5
02 ground potential terminals 102, 104, 203, 204, 403, 404
Ground potential wiring 107,207 N-type MOS transistor 307 P-type MOS transistor 108,208,308,408,501 Output terminal 110,210,310,410,503 Output terminal driving MOS transistor 105,106,205,206,305 , 306, 4
05,406 Internal circuit 110, 210, 310, 410 Output MOS transistor drive signal

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a plurality of fixed potential input terminals of the same potential, wherein a potential is supplied to an element of an internal circuit from a first fixed potential input terminal of the fixed potential input terminals of the same potential. The first fixed potential wiring is the source or drain electrode, the second fixed potential wiring for supplying the potential from the second fixed potential input terminal to the element of the internal circuit is the drain or source electrode, and the gate electrode is in the cutoff state. A semiconductor integrated circuit device comprising transistors connected to a potential, respectively.