JPH0574258B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a termination device for a data transmission line. Specifically, local area networks (hereinafter referred to as
This is a terminating device used in a LAN transmission path, and the aim is to provide a new data terminating device for connecting various data terminals to a LAN transmission path.

[Prior Art] A conventional technique is disclosed in, for example, Japanese Patent Laid-Open No. 118032/1983, and will be explained using FIGS. 33 to 39.

Figure 33 shows a terminal with a speed of 19.2Kbps.
It is a principle diagram for accommodating a 64Kbps transmission line in an electronic exchange. The flag synchronization bit (F bit) located at bit 0 of frame 0 is used to cause the receiving side to take the frame position by repeating the flag pattern of "1010". The receiving side is
By detecting this, the frame position can be easily recognized. Accommodating a 19.2 Kbps terminal on a 64 Kbps transmission path can be achieved by accommodating 24-bit data D0 to D23 in designated bit positions every 10 multiframes, as shown in FIG. Please do not use blank spaces.

FIG. 34 shows the principle of accommodating a 9.6 Kbps terminal.

12 which is 1/2 the number of bits of 19.2Kbps in Figure 33
Speed conversion is possible if bit data D0 to D11 can be accommodated, but in this case, in order to accommodate data of different speeds in the same circuit, the same data is embedded twice as shown in Fig. 34.
Accommodates different speeds as 19.2Kbps. Similarly, for 4.8Kbps data, repeat the same data four times,
2.4Kbps data is achieved by embedding eight times each.

The principle of the synchronization establishment bit (SY bit) located at bit 0 of frame 1 will be explained with reference to FIG.
In Fig. 35, L ₁ and L ₂ are the transmission line and reception line, respectively, when viewed from the device A side, and the device B
From a closer perspective, the relationship is the opposite. However, in the following explanation, the state viewed from the A side will be explained.

The line termination device DCE _a on the A side detects the F bit sent from the rotary termination device DCE _b on the B side of the reception line L ₂ and, when synchronization is established, turns on the SY bit and switches the transmission line L ₁ on. Send to. When the line terminating device DCE _b on the B side establishes synchronization with the transmission line _L1 by receiving the F bit, it similarly
Sends the on state of the SY bit to receive line _L2 . With the above, the line terminating device DCE _a on the A side is connected to the receiving line.
By monitoring the SY bit of _L2 , the synchronization state of the transmission line _L1 can be known. Line termination device on B side
The same applies to DCE _b . JIS-C6361 and EIA RS-232
-C and various control line information specified by CCITT V.24/V.28 are accommodated in bit 7 of frames 0 to 3 in FIGS. 33 and 34.
The alphabetic character to the left of the diagonal line in bit number 7 is A
The signal sent by the side terminating device DCE _a to the transmission line L ₁ ,
The English letters on the right are signals sent from the B-side line termination device DCE _b via the receiving line _L2 .

Here, RS is a request to send signal (Request to Send), CD is a received carrier detection signal (Carrier Detect), CS and CS′ are clear to send signals (Clear to Send), and ER is a data terminal ready signal. The signal (Equipment Ready) and DR are data set ready signals (Data Set Ready), and CI and CI' are called indicator signals (Call Indicator). FIG. 36 shows a method of accommodating control signals between the terminal device A and the terminal device B, and FIG. 37 shows a method of accommodating control signals between the terminal device and the modem.

In FIG. 36, since terminal devices A and B are interfaces having the same input/output relationship, transmission data SD transmitted from terminal device A is received by terminal device B as reception data RD. Similarly, other lines are connected as shown in the figure. The transmission lines are connected one-to _- one to make the explanation easier to understand, but since the data formats shown in _Figs . A collection of books. As is clear from the principle explained in FIGS. 33 and 34, each control signal is sampled only once every 10 frames. There is a maximum delay of 1.25ms before the reception carrier detection signal CD of device B turns on, and if the data from terminal device A reaches the reception data RD before the reception carrier detection signal CD turns on,
Terminal device B cannot receive because it is not ready for reception.

Therefore, in order to keep the reception carrier detection signal CD in the on state during data reception, the value of the transmission request signal RS is determined by the logical sum of the previous and current sample values, and the transmission path is set as shown in the table below. This is achieved by determining the state to be sent to.

Value of RS Previous state Current state Transmission state Off Off Off Off On On On Off On On Off On Figure 38 shows the relationship between the transmission request signal RS and the transmission data SD. The relationship between the transmission request signal RS and the transmission data SD is that while the transmission request signal RS is on, the data D
has become effective. If we sample it in units of 10 multiframes (1.25ms) as mentioned above, RS
This becomes the sample pulse (RSP). However, if data D is delayed by 1.25 ms and sent out to the transmission path as transmission data SD, and the state judgment in the previous table is performed to determine transmission RS, the relationship between transmission RS and data D will be as shown in Figure 38. becomes the send request signal
The relationship that data D is valid while RS is on is guaranteed.

To delay data by 1.25ms, a 24-stage shift register is provided as shown in Figure 39, and the register
This is achieved by setting the load pulse to 1.25ms at the timing of transferring from REG _a to register REG _b .
The reason for providing 24 stages is that 24 stages are added to the 10 multi-frames mentioned above.
This is because bits must be embedded.

FIG. 37 shows a connection between a terminal and a modem, and unlike FIG. 36, transmission data SD is connected one-to-one to transmission data SD of a modem (modem). Other control signals are also connected one-to-one as shown in the figure. Also, the output signal from the modem is
CS and CI are realized by connecting to CS′ and CI′.

[Problems to be Solved by the Invention] The termination devices shown in FIGS. 35, 36, and 37 have a multi-frame configuration on a channel transmission line fixed at 64 kbps, for example, 2.4 kbps, It accommodated and transmitted terminal data and various control line information at data (communication) speeds such as 4.8 kbps, 9.6 kbps, and 19.2 kbps.
However, recently, such data has been used in various ways.
There is an increasing demand for sending and receiving data over LAN transmission lines,
If these traditional data rates e.g.
Set the end device fixed at 64kbps to a faster speed than the end device, for example, 128kbps, 192kbps,
There was a problem in that it was not possible to connect to a LAN transmission line with a speed of one of 256kbps, 384kbps, 1.536Mbps, 3.072Mbps, etc.

[Means for solving the problem] A PLL circuit for obtaining a basic clock from a LAN transmission line with a predetermined transmission speed, and a forced terminal device control based on the basic clock that is the output of this PLL circuit. A timing generation circuit that generates timing signals for synchronizing with the LAN transmission path and various timing signals necessary for the operation of each circuit in this terminal device, and a timing generation circuit that generates timing signals for synchronizing with the LAN transmission path and the various timing signals necessary for the operation of each circuit in this terminal device. A mapping circuit that performs mapping to match the data speed, and a demapping circuit that receives data signals from a LAN transmission line sent at a predetermined speed and sends the demapped data to a terminal device are provided.

[Operation] With this configuration, the operations of terminal devices of various speeds can be synchronized with the LAN transmission path, data signals of the terminal devices can be mapped and speed converted, and sent to the LAN transmission path at a predetermined transmission speed. Now I can do it. It was also sent at the specified speed.
It receives data signals from the LAN transmission line, demaps them, and transmits them to the terminal device at the speed of the terminal device.

By doing this, you can set different data speeds, for example, 2.4kbps, 4.8kbps, 9.6kbps,
various terminal devices operating at one data rate, such as 19.2kbps, having a given transmission rate;
It made it possible to communicate via a LAN transmission line.

[Embodiment] The present invention is a LAN transmission line termination device that operates according to the regulations of JIS-C6361 and the like and can handle data at a predetermined speed. Fig. 1 is a system configuration diagram for explaining the operational concept. The waveforms of each part are shown in FIG. 2 and will be explained.

In FIG. 1, between the terminal device 5A on the terminal device A side and the terminal device 5B on the terminal device B side
There is a LAN transmission line in between. The signal speed of this LAN transmission line is, for example, 128kbit, 192kbit,
One of 256 kbit, 384 kbit, 1.536 Mbit, 3.072 Mbit ps, etc. is used, and a LAN control device 8 is provided for exchanging signals on this LAN transmission path. This LAN control device 8 sends a timing signal TIMP to the LAN transmission path.

The timing signal TIMP sent from the LAN timing circuit 9 to the termination devices 5A and 5B via the LAN transmission line and the timing of data transferred by the LAN control device 8 are shown in FIG.

TIMP in FIG. 2a is a signal that defines the timing of transmission and reception on this LAN transmission line. When the terminating device 5A receives the timing signal TIMP shown in a, the terminating device 5A outputs the data signals D0 to D7 received from the terminal A as DOUT shown in b.
It is sent to the LAN transmission line during the period of the timing signal TIMP. The transmission of DOUT shown in b is performed at intervals of 125 μs, for example. In the terminal device 5B,
During the TIMP period of a, the data signals D0 to D7 from the terminal device A are set as DIN shown in c, for example.
Receive at 125μs intervals.

Communication between the terminal devices 5A, 5B and the terminal devices A, B is carried out using the timing of ST2 and RT, which are clocks generated from TMP, in the terminal devices 5A, 5B as described above as the prior art. SD, RD in Figures 36 and 37,
This is done using the RS, CS, CS′, CD, ER, DR, and CI′CI signals.

Of the operational concept explained in FIG. 1, the part related to the present invention, that is, the specific structure of the terminal devices 5A and 5B, is shown in FIG. 3, and the waveforms of each part are shown in FIG. 4 and will be explained. Here, the terminal devices 5A and 5B
Both have the same configuration.

In FIG. 3, 100 is a PLL (Phase Lock Loop) circuit, which creates a basic clock 121 for obtaining various timing signals within the apparatus based on the timing signal TIMP of the LAN transmission line. The relationship between TIMP and basic clock 121 is such that the leading edge of basic clock 121 is synchronized with the trailing edge of TIMP, as shown in FIGS. 4b and 4c.

In the timing generation circuit 200 receiving the basic clock 121, based on TIMP, the signals 274 and 275 shown in FIG.
bus signal 259, bus signal 286, and clocks ST2 and RT.

300 is a mapping circuit which receives transmission data SD sent from the terminal device, transmission request signal RS,
The clear-to-send signal CS', the data terminal ready signal ER, and the called indication signal CI' are sent to the bus signal 259 and the signal 27 as shown in FIG. 33 or 34.
4 and outputs the mapped signal 386 of FIG. 4a as DOUT.

Reference numeral 400 denotes a demapping circuit, which receives the demapped signal 90 DIN and outputs received data RD (D0 to 5, D6 to 11, . . . in FIG. 4d) contained therein.
...) at the timing of signals 262 and 275,
In addition, the send ready signal CS, data set ready signal DR, and called indication signal CI are sent at the timing of bus signal 286, and the received carrier detection signal CD is sent to signal 2.
At timing 64, contrary to the mapping shown in FIG. 33 or FIG. 34, the data is demapped and sent to the terminal device.

Furthermore, in the demapping circuit 400, FIG.
The frame numbers shown in (frame 0, frame 1
.

In the demapping circuit 400, the frame 1
The mapping circuit 3 detects the SY bit (Fig. 4 d) and sends a signal 551 indicating that synchronization has been established.
00, and the mapping circuit 300 that receives this signal 551 outputs the SY of frame 1 in FIG. 4a.
It is called bit (first bit). When the mapping circuit 300 receives the transmission request signal RS, it sends out a signal 367. Upon receiving this, the demapping circuit 400 performs an AND operation with CS of frame 1 in FIG. 4d and outputs a transmission enable signal CS.

FIG. 5 explains the operation of clocks ST2 and RT generated by the timing generation circuit 200.
The clock ST2 shown in b is sent to the terminal device, and at its rising edge, the data D0, D1, . . . are sent out from the terminal device as transmission data SD as shown in a, and applied to the mapping circuit 300. The clock RT shown in Figure 5d is the received data shown in c.
It is sent along with RD to the terminal device, and the terminal device captures the received data RD by sampling the received data RD at the trailing edge of the clock RT.

FIG. 6 shows, for example, a data terminal device.
Transmitted data SDa when operating at a speed of 9.6kbps,
Clock ST2b, timing signal 274c
It shows the relationship of sampled SDd. When the data terminal device receives the clock ST2 shown in d from the timing generation circuit 200, it sends out the transmission data SD shown in a to the mapping circuit 300.

Upon receiving this, the mapping circuit 300 maps each sampled SD shown in d by sampling one data twice using the timing signal 274 shown in c.

FIG. 7 shows the circuit configuration of the timing generation circuit 200. Here, 240 is a clock timing circuit, and the basic clock 121
and TIMP, the bus signal 276, the signal 274 to the mapping circuit 300, and the bus signal 259
It generates a signal 275 to the demapping circuit 400 and clocks ST2 and RT to the terminal device. Here, signal 262 included in bus signal 259
and 264 are also applied to the demapping circuit 400.

280 is a reception timing circuit which receives the basic clock 121 and bus signals 526 and 276 and outputs the bus signal 286 to the synchronous reception circuit 400.
is being sent.

FIGS. 8 and 9 are circuit diagrams and timing charts of clock timing circuit 240.

In FIG. 8, 241 is an eight-stage serial/parallel (S/P) register, and TIMP, which is applied at 125 μs intervals as shown in FIG. S/P register 2 with 8 stages of basic clock as shown in
41 clock terminal. Its output Q7
A signal 278 shown in c is obtained. This signal 2
The rising edge of 78 is 1/2 cycle of the basic clock in b earlier than the rising edge of TIMP in a, and the rising edge of TIMP in b is faster than the falling edge of TIMP shown in a.
An output not shown in Figure 9 that falls with a delay of 1/2 cycle of the basic clock 121 shown in Figure 9.
The AND gate 149 performs an AND operation with QO, and the signal shown in d rises 1/2 cycle of the basic clock 121 and falls 1/2 cycle after the falling edge of TIMP shown in a. I got 279.

This signal 279 is applied to the reset terminal R of the 24-ary counter 242. On the other hand, the basic clock 121 shown in b is applied to the clock input terminal of the 24-decimal frame counter 242, and when the signal 279 is applied to the reset terminal R at d, this basic clock 121 is upped from 0. When the count reaches 23, a signal 258 shown at f is outputted from the carry out terminal CRY, and the count value during this counting up is outputted by a bus signal 276 shown at e.

The signal 258 shown at f from the carry-out terminal CRY of the 24-decimal frame counter is connected to the decimal multi-frame counter applied to the enable terminal ENB.
The counter 243 has the basic clock 121 of b applied to its clock terminal via the inverter 252, counts up from 0 every signal 258, and indicates the count value at the bus signal 277 g.
When the count value reaches 9, by applying the signal 258 shown in f and the basic clock 121 via the inverter 252, the bus signal 27 shown in g is applied.
Set the count value of 7 to 0 as shown in Figure 9g,
Count up again.

Bus signal 276, which is the output of 24-decimal frame counter 242, is applied via decoder 244 to flip-flop group 245, which includes one D flip-flop for each signal decoded. Each of the decoded signals is applied to the data terminal of each flip-flop, and the clock terminal of each flip-flop has a basic clock signal.
21 (CK1) or the basic clock 121 (CK2) via an inverter 252 is applied.

In this way, from the flip-flop group 245, the signal 260 shown at h is transferred to the bus signal 276 shown at e.
16, and is delayed by 1/2 cycle of the basic clock 121 of b.
62 is obtained as shown in i.

Signal 2, which is the output of flip-flop group 245
61, when the value of the bus signal 277 shown in g indicates 0 and the value of the bus signal 276 shown in e indicates 17 to 22, one pulse, ie, a group of six pulses, is generated for each value of the bus signal 276. In addition to when the value of the bus signal 277 of g is 0,
It is also output in the case of 1, 2, 3 (Fig. 17B d)
reference).

Signal 2, which is the output of flip-flop group 245
64 is output as a pulse with a pulse width of one cycle of the basic clock 121 of b when the value of the bus signal 277 shown in g indicates 0 and the bus signal 276 shown in e indicates a value of 17. .

Similarly, the signal 265 is the bus signal 2 shown in g.
The value of 77 indicates 1, and the bus signal 276 shown at e
When the value of 17 is shown, the basic clock of b is 1 of 121.
It is output as a pulse with a pulse width equal to a cycle.

Similarly, the signal 267 is the bus signal 277 shown in g.
When the value of 3 indicates 3 and the bus signal 276 shown at e indicates a value of 23, a pulse having a pulse width of one cycle of the basic clock 121 at b is output.

Similarly, the signal 270 shown at K shows that the value of the bus signal 277 shown at g is 0, and the bus signal 277 shown at e shows the bus signal 277 shown at g.
When 6 shows the value of 23, the basic clock of b is 121
It is output as a pulse with a pulse width of one cycle.

Similarly, the signal 271 is the bus signal 277 shown in g.
When the value of 1 indicates 1 and the bus signal 276 shown at e indicates 16, a pulse having a pulse width of one cycle of the basic clock 121 at b is output.

Similarly, the signal 272 is the pulse signal 27 shown in g.
The value of 7 indicates 2, and the bus signal 276 shown in e is 23
When , the pulse with a pulse width of one cycle of the basic clock 121 is output at b.

These signals 260, 261, 262, 26
3,264,265,267,270,271,
272 forms a bus signal 259.

The signal 263 shown in j is output while the value of the bus signal 276 of g is 17 to 22, and is further output in the same way when the value of the bus signal 277 of g is 1, 2, or 3. .

The signal 276 shown at e is also applied to the decoder 246 and the same signal 262 shown at i is applied to one terminal of the AND gate 250.

The bus signal 277 shown in g is also applied to the decoder 247 and decoded to produce the bus signal 277 in g.
While the value of 7 is 0, “1” is output to the other terminal of the AND gate 250. Therefore, the output of this AND gate 250 becomes the same signal as the i signal 262 and is applied to the reset terminal R of the decimal counter 248 to reset it. On the other hand, this
The basic clock 121 shown in b is applied to the clock terminal of the decimal counter 248, and the clock ST2 shown in m starts at the rising edge of the basic clock 121 applied at the same time as the rising of the signal 262 shown in i. Rise up, this basic clock 12
It falls when it counts 5 1's, and rises again when it counts 5 more 1's. Clock RT and clock 275 are the same as clock ST2, and are inverted by inverter 253 to obtain clock 274.

A specific circuit of the reception timing circuit 280 and its timing chart are shown in FIGS. 10A and 10B.

In FIG. 10A, decoder 281 decodes bus signals 276 and 256 and applies them to flip-flop group 282. Here, the decoder 281, flip-flop group 282 and inverter 283 are connected to the decoder 24 shown in FIG.
4, flip-flop group 245, and inverter 252, respectively.

The signal 288 shown in c is the bus signal 25 shown in d.
This signal is output every time the value of 6 changes, has a pulse width of one cycle of the basic clock 121 of a, and indicates "1" from the second half of 6 to the first half of 7 of the value of bus signal 276 of b. .

The signal 287 shown in e is the bus signal 52 shown in d.
Each time the value of 6 changes, the bus signal 276 shown in b
When the value of shows 16, the basic clock of a is 121
It is output with a pulse width of one cycle.

The signal 289 shown in h is the bus signal 52 shown in d.
When the value of 6 indicates 1, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 16 to the first half when it shows 17.

The signal 293 shown in g is the bus signal 52 shown in d.
When the value of 6 is 0, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 23 to the first half when it shows 24.

The signal 294 shown in i is the bus signal 52 shown in d.
When the value of 6 indicates 1, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 23 to the first half when it shows 24.

The signal 296 shown in j is the bus signal 52 shown in d.
When the value of 6 indicates 2, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 23 to the first half when it shows 24.

The signal 297 shown in k is the bus signal 52 shown in d.
When the value of 6 indicates 3, and the bus signal 2 of b
The value of 76 indicates "1" from the second half when it shows 23 to the first half when it shows 24.

The signal 290 shown in f is the bus signal 52 shown in d.
When the value of 6 indicates 0, 1, 2, 3, b
From the second half when the value of bus signal 276 shown in shows 17
By the time it finishes showing 22, six pulses are output.

FIG. 11a shows the circuit configuration of the PLL circuit 100, and 101 is an oscillator that oscillates a clock 105 of, for example, 3.072 MHz. 110 is a frequency dividing circuit, which receives this clock 105 and
The frequency is divided by 15, 16, or 17 under the control of signals 161, 162, and 163 shown in the table. signal 16
3, 162, 161 are “0”, “1”, respectively
When it shows "1", it is judged that there is a phase lag, that is, the frequency of the basic clock 121 is low, the frequency division ratio is set to 15, the frequency of the basic clock 121 is increased, and the clock is set to "1", "0", "0". ”, it is assumed that there is no phase delay or lead, and the frequency division ratio is set to 16.
When "1", "0", and "1" are shown, it is judged that the phase is leading, that is, the frequency of the basic clock 121 is high, and the frequency division ratio is set to 17.
By lowering the frequency of the basic clock 121, the basic clock 1 of 192KHz synchronized with TIMP
I got 21. This frequency dividing circuit 110 further divides the frequency of the 3.072 MHz clock 105 by 3, 4 or 5, as shown in FIG. 11b, to obtain a signal 128 with a frequency of 768 kHz. Also, frequency dividing circuit 1
10, the basic clock 121 is divided by 24 to create 8K.
A signal 126 with a frequency of Hz is obtained, and a signal 127 whose timing is different from that of the signal 128 but whose frequency is the same is output.

130 is a phase comparator circuit, which connects TIMP and signal 1.
26 and 127, the phases of TIMP and signal 126 are compared. This comparison is performed every 125 μs, and when the phase of the signal 126 is ahead, the signal 141 is output, and when the phase is behind, the signal 142 is output. During the period when no comparison is performed, both signals 141 and 142 are output. Both indicate "0".

In the frequency division ratio control circuit 150, the clock 105 and
Upon receiving a signal 141 representing a phase lead, a signal 142 representing a phase lag, and a signal 128, it is determined that the phase is leading when the signal 141 is "1", and the signals 163, 162, and 161 are set to "1",
“0” and “1”, and when the signal 142 is “1”, it is determined that there is a phase delay and the signals 163, 162, 16
1 as “0”, “1”, “1”, and the signals 141, 14
When both 2 are “0”, “1”, “0”,
“1” is output.

FIG. 12A shows a specific circuit example of the frequency dividing circuit 110, and FIG. 12B shows its timing chart.

111 in FIG. 12A is a hexadecimal counter, and its clock terminal is connected to the clock 1 in FIG. 12B a.
05 is applied, and the output of the carry terminal CRY is applied to the load terminal LD via the inverter 117.

Furthermore, the data terminal D of this hexadecimal counter 111
0, D1, D2, and D3 are signals 161 and 161, respectively.
162, 163 and +5V “H” are applied, and the outputs Q1 and Q2 are connected to the AND gate 11.
2 to obtain a signal 129 shown in e.

When the phase is delayed, that is, the signals 163, 16
When the carry CRY is output when 2,161 is "0", "1", "1", the signal 128 shown in FIG.
The hexadecimal counter 111 applied to LD
Load the count value 11 in figure B c, count up the clock 105 in a, and check the count value.
11, 14, and 15, the output Q1 becomes “1” respectively.
and the output Q2 has a count number of 12 to 15.
Since it indicates "1", the AND is performed to obtain the signal 129 shown at e. Therefore, the signal 129 shown at e will indicate "1" when the values of Q0 to Q3 of the counter 111 at d indicate 14 and 15.

When the phase is advanced, that is, the signals 163, 162,
Carry when 161 is “1”, “0”, “1”
When CRY is output, the hexadecimal counter 111
Loaded with 13 of Figure 12B c, clock 105
count up and the count number is 14,
15, the output Q1 indicates "1", and the output Q2 indicates "1" when the count number is 13 to 15, so the AND is performed to obtain the signal 129 shown at e.

Similarly, when there is no phase lead or lag, that is, signals 163, 162, 161 are "1", "0",
If carry CRY is output when “0”, 16
The decimal counter 111 has the count value 12 in Figure 12B c.
is loaded, and when the count number becomes 13, 14, or 15, the output Q1 indicates "1", and the output Q2 indicates "1" when the count number is 12 or 15.
Therefore, by taking the AND, we get the signal 1 shown in e.
Get 29.

113 and 114 are D flip-flops, a signal 129 of e is applied to the data terminal D of the flip-flop 113, a clock 105 is applied to its clock terminal via an inverter 116, and an output Q is applied to the data terminal of the flip-flop 114. applied. A clock 105 is applied to the data terminal of the flip-flop 114, and its output Q provides a signal 127 shown at f which is delayed by one cycle of the clock 105 of the signal 129 a. This signal 127 is applied to the 96-decimal counter 115, and the signal 121 whose frequency is divided into 1/4 and 1/96
A signal 126 is obtained.

FIG. 13A shows a specific circuit example of the phase comparison circuit 130, and FIG. 13B shows its timing chart.

131 to 133 are D flip-flops, and when the signal 126 shown in FIG. And 143 of c and 144 of d are output to the knot output Q. Here, when the signal 126 of b is behind the TIMP of a, the signal 143 of c indicates "0", and when it is ahead, it indicates "1".

The signal 127 of e is connected to the flip-flop 132,1
TIMP is applied to the clock terminal of flip-flop 133, and TIMP is applied to the data terminal D of flip-flop 132 via inverter 137. Its output, a signal 145 shown at f, is applied to one input terminal of the NAND gate 134, this signal 145 is applied to the data terminal D of the flip-flop 133, and at its output Q, a signal 146 shown at g is applied. is applied to the other input terminal of NAND gate 134 via inverter 138. signal 14
A signal 147 of h is obtained by taking the AND of 5,146 and inverting it.

Signal 143 of c and signal 147 of h are input to NOR gate 135 to obtain signal 141 shown at i. Also, the signal 144 of d and the signal 147 of h
is applied to NOR gate 136 to obtain signal 142 shown at j. This i and j signal 14
1 and 142 both enable only data obtained from signal 126 immediately after the falling edge of TIMP.

FIG. 14A shows a specific circuit example of the frequency division ratio control circuit 150, and FIG. 14B shows its timing chart.

Reference numerals 151 to 155 are D flip-flops, and a signal 1 indicating the phase lead in FIG.
41 is applied, a signal 165 shown in b is obtained, which is applied to the clock 10 of e via an inverter 157.
A signal 128 indicated by f is applied to the data terminal D of the flip-flop 153 to which 5 is applied.
Its output Q is the D flip-flop 154, 155
applied to the clock terminal of

On the other hand, since the c signal 142 representing the phase delay is "0" at this point, the d signal 164, which is the output Q of the flip-flop 151, is "0". Therefore, the h and g signals 162 and 163 indicate "0" and "1", respectively, before time _t1 , and the not Q output of the D flip-flop 155 and the NAND gate 1 to which the g signal 163 is applied.
56 outputs the signal 161 shown at i and sets it to "1". This signal 161 indicates "0" before time _t1 .

After time t ₁ in FIG. 14B, signal 1 of f
28 indicates "0", and at the trailing edge of the e signal 105 applied next to the rise of this signal 128, that is, at time _t2 , the i signal 161 changes from "1" to "0".

Similarly, at time _t3 , i's signal 161
changes from “0” to “1”, h signal 162 changes to “0”
The signal 163 of g changes from “1” to “0”. Comparing this state with the signal in FIG. 11b, before time _t1 , the signal 14B
Signals 163, 162, 161 in figures g, h, and i are
Since they indicate "1", "0", and "0", respectively,
This shows the state without phase control. At time _t1 to _t2 , the same signals 163, 162, 161 are
Since they respectively indicate "1", "0", and "1", they indicate a state of phase advance. Similarly, at times _t3 to _t4 , the signals indicate "0", "1", and "1", respectively, indicating a phase lag. After time _t4 , a state without phase control is shown.

FIG. 15A shows the data rate of the LAN transmission path, for example, 128 kbps, 192 kbps,
The circuit configuration of the mapping circuit 300 for adjusting to one data rate among 256 kbps, 384 kbps, 1.536 Mbps, 3.072 Mbps, etc. is shown, and its timing chart is shown in FIG. 15B.

This is Figure 33 showing mapping, or Figure 3.
The F bit at bit number 0 in Figure 4, the SY bit, and the various control signals at bit number 7
CS', CI', RS, ER and bit numbers 1 to 6
This shows a circuit for concentrating data D0 to D23. The F bit sending circuit 310
In response to the signal 260 in Figure B, it outputs a signal 316 "1" indicating the F bit of c. Since the F bit is "0" after 1.25 ms, that is, after one multiframe, the signal 316 of c at that time indicates "0".

The SD sending circuit 320 is shown in FIG. 15B d, e, f.
In response to the signals 261 and 263 shown in
SD is sampled by clock 274 and signal 3
26 is output.

The CS' sending circuit 330 samples the transmittable signal CS' with the signal 264, and outputs the signal 336 at the timing of the signal 265 shown in FIG. 15B, j.

The CI' sending circuit 340 samples the called indication signal CI' with the signal 264 and outputs the signal 346 at the timing of the signal 267 shown in FIG. 15B (n). Here, the configuration of this CI' sending circuit 340 is as follows:
The configuration is the same as that of the CS' sending circuit 330.

The SY bit sending circuit 350 receives the signal 551 and outputs the signal 356 at the timing of the signal 271 shown in FIG. 15B k.

The RS sending circuit 360 receives the sending request signal RS, samples it with a signal 264, and outputs the signal shown in FIG. 15B.
The signal 366 is sent out at the timing of the signal 270. Here, the signal 367 constantly outputs the sampled signal RS.

The ER sending circuit 370 outputs a data terminal ready signal.
ER is sampled with signal 264, and at the timing of signal 272 shown in Figure 15B, signal 376 is sampled.
is outputting. Here, this ER sending circuit 37
The configuration of CS′ sending circuit 330 is the same as that of CS′ sending circuit 330.

Concentrator circuit 380 receives signals 316, 326 of FIG. 15B, c and g, and signals 336, 346, 35.
6,366,376 are condensed and OR'ed, and a map signal 386 shown in FIG. 15B (p) is output.

FIG. 16A shows an example of a specific circuit of the F bit sending circuit 310, and FIG. 16B is a timing chart showing waveforms of each part thereof.

Reference numeral 311 denotes a D flip-flop, and the signal 317 shown in FIG. be done. This c signal 316
and a signal 260 are ANDed by an AND gate 312 to output a c signal 316. The signal 312 of c is output every 10 frames at the start of the frame.

FIG. 17A shows an example of a specific circuit of the SD sending circuit 320, and FIG. 17B is a timing chart of signals in each part of the circuit.

S/ for 24-bit serial/parallel conversion
In the P register 321, the transmission data SD shown in FIG. 17B (b) is sampled by the clock 274 (a), loaded into the register, and outputted in parallel.
Here, the clock 274 of a has a period of 10 frames.
This is a signal that divides 1.25ms into 25 equal parts, which is
It has a frequency of 19.2kbps. Transmission data of b
SD indicates data from 0 to 23 sent from the terminal side.

A P/P that receives data in parallel from the S/P register 321 and performs 24-bit parallel-to-serial conversion.
The S register 322 loads the data received at the timing of the signal 262 shown in c, and loads the data received at the timing of the signal 262 shown in c.
At timing 61, a signal 326 of i among f, g, h, and i shown on an enlarged time axis is outputted via an AND gate 323 during a period of signal 263 of e.

Here, the repetition period of signal 263 of h is 125μs
The repetition frequency of the signal 261 of g during the period of one signal 263 of h is equivalent to 192 kbps,
Six pieces of data are sent four times in 1.25ms at 125μs intervals.

FIG. 18A shows an example of a specific circuit of the CS' sending circuit 330, and FIG. 18B is a timing chart of signals in each part of the circuit.

The send enable signal CS' of FIG. 18B b is applied to the data terminal D of the D flip-flop 331.
The signal a is applied to the clock terminal at an interval of 1.25 ms, and the output signal Q and the signal c 265
is applied to AND gate 332, and a signal 336 shown at d is output. This signal 336 indicates the timing at which the send ready signal CS' is sent to the LAN transmission line.

The operation of this CS' sending circuit 330 is the same as that of the CI' sending circuit 340 and the ER sending circuit 370, and the ready-to-send signal CS' is called the called indication signal CI' or the data terminal ready signal ER. signal 2
65 is called signal 267 or signal 272,
Output signal 336 as signal 346 or signal 3
It can be called 76 instead.

FIG. 19A shows an example of a specific circuit of the SY bit sending circuit 350, and FIG. 19B shows a timing chart of signals in each part of the circuit.
Here, the AND gate 351 has a
The signal 551 shown in and b and the signal 271 at an interval of 1.25 ms are applied, and by taking the AND, c
A signal 356 is output. This signal 356
Indicates the timing of sending the SY bit to the LAN transmission line.

FIG. 20A shows an example of a specific circuit of the RS sending circuit 360, and FIG. 20B shows a timing chart of signals in each part of the circuit.

The transmission request signal RS shown in FIG. 20B is applied to the data terminal D of the D flip-flop 361.
A signal 264 shown at a is applied to its clock terminal, and a signal 368 shown at c is outputted to its output Q. c signal 368 and b transmission request signal RS
is applied to the OR gate 363 and ORed,
Applied to data terminal D of D flip-flop 362. The a signal 264 is applied to the clock of this D flip-flop 362, and the d signal 367 is outputted to its output Q. This d signal 3
67 is the same as the transmission RS in FIG.

The signal 368 indicates the value of the previous transmission request signal RS, that is, 1.25ms ago. If the previous RS (signal 368) is "0" and the current RS is "0", the signal 367 of d is "0". 0” and the previous RS
is “0” and the current RS is “1”, signal 3
67 is "1", and if the previous RS is "1" and the current RS is "0", the signal 367 is "1", and the previous RS is "1" and the current RS is "0". If so, the signal 367 is "1". To summarize, if either the previous RS or the current RS is "1", the signal 367 indicates "1".

This signal 367 and the signal 270 of FIG. 20B are applied to an AND gate 364 to output a signal 366 shown at f. This signal 36
6 indicates the timing for sending the transmission request signal RS to the LAN transmission path.

FIG. 21A shows a specific example of the concentrator circuit 380, and FIG. 21B is a timing chart of signals in each part of the circuit.

Signal 316 in Figure 21B a, signal 326 in Figure 21B d,
e signal 336, g signal 346, c signal 35
6, b signal 366, and f signal 376 are applied to OR gate 381 to output a map signal 386 shown at h. Therefore, the F bit is sent out at the beginning of a multi-frame consisting of 10 frames, the data D0-5 are sent out at the next 6 bits, and the transmission request signal RS is sent out at the last bit of the first frame.

In the first bit of the second frame, the SY bit is
Data D6 to D11 are sent to the next 6 bits, and a send enable signal CS' is sent to the last bit.

The first bit of the third frame is "0", the next 6 bits are data D12-17, and the last bit is the data terminal ready signal of signal 376 shown at f.
ER is sent.

The first bit of the fourth frame is "0", the next 6 bits are data D18-23, and the last bit is the called indicating signal CI' of signal 346 shown in g.

This h between the 5th frame and the 10th frame
All signals 386 indicate "0". In this way, the mapping shown in FIG. 33 is executed.

FIG. 22A shows, for example, 128 kbps, 192 kbps,
It receives the demapped signal 90, which is data input DIN, from a LAN transmission line with a data speed of one of 256 kbps, 384 kbps, 1.536 Mbps, 3.072 Mbps, etc., and demaps the received data RD according to the speed of the terminal device. A configuration diagram of a demapping circuit 400 for transmitting data to a terminal device is shown, and FIG. 22B shows a timing chart of waveforms of each part thereof.

The F-bit receiving circuit 410 detects the F-bit signal from the demapped signal 90 shown in FIG. It outputs a signal 501 indicating whether or not it is in a synchronized state. Here, in order to detect the F bit, the basic clock 121 and the bus signal 2
Signals 287 and 288 included in 86 are used,
The signal 287 is applied at the timing of the first bit position of each frame as shown in FIG. 22B (c). The signal 288 is applied every frame to indicate the timing at which the bus signal 526 is output.

The RD receiving circuit 560 samples the demapped signal 90 shown in FIG. It is outputting to the terminal side. The received data RD of g has a speed of, for example, 19.2 kbps, which is suitable for the operation of the terminal equipment.

In the CS receiving circuit 580, the demapped signal 90 of FIG. 22B (b) is sampled with the l signal 294, and the m transmittable signal CS is extracted. Here, the send enable signal CS is sent only when both the signals 367 and 551 are "1".

In the CI receiving circuit 595, the demapped signal 90 of FIG. 22B b is sampled with the q signal 297, and the r called call indication signal CI is extracted and sent.

In the SY bit receiving circuit 530, FIG.
The demapped signal 90 of ``h'' is sampled with the signal 289 of ``h'', and the signal 501 is
It is sent as a signal 551 only when .

The CD receiving circuit 570 samples the demapped signal 90 shown in FIG. 22B with the signal 293 of i, and outputs the result as a received carrier detection signal CD shown at k at the timing of the signal 264 of j.

The DR receiving circuit 590 operates in the same manner as the CI receiving circuit 595, and converts the signal 297 into the n signal 296 and the called indication signal CI into the p data set ready signal DR.
It can be called instead.

FIG. 23A is a diagram showing the internal configuration of the F-bit receiving circuit 410, and FIG. 23B is a timing chart of waveforms of each part thereof. Here, in FIG. 23B, only the F bit of the demapped signal 90 is displayed, and all other data signals and control signals are displayed as "0".

In the frame counter 420, the basic clock 1
21 and the signal 287 of FIG. 23B a, and outputs the bus signal 440 of c. This c bus signal 440 indicates frame numbers 0 to 9,
When this frame number is 0, the signal 441 of d is output at the timing of the signal 287 of a. g
When the signal 501 of is “0”, the signal 47 shown in f
1, it is not possible to count up the bus signal 440 which is the frame count output, but when it receives the signal 470 of e, it becomes possible to count up, and the signal 28 of a
Each time 7 is applied, the contents of the c bus signal 440 are counted up from 0 to 9 and then 0 again.
Return to Here, when the f signal 471 is applied, the count is not increased, and when the e signal 470 is applied, it is possible to count up.

When the g signal 501 is "1", the frame counter 420 counts up the a signal 287 and c The operation of counting the contents of the bus signal 440 from 0 to 9, then back to 0, and counting back to 9 is continued.

In the comparator circuit 450, the g signal 501 is “0”
In this case, the demapped signal 90 representing only the F bit of b is compared with the circuit state of the flip-flop in the comparison circuit 450 at the timing of the signal 441 of d, and if a match is obtained, it is determined that the F bit has been detected. Therefore, output signal 470 of e, invert the state of the internal flip-flop, and if there is a mismatch,
Since the F bit is not detected, f
The state of the internal flip-flop is not inverted.

When the signal 501 of g is "1", each time the signal 441 of d is applied, regardless of whether the demapped signal 90 representing only the F bit of b matches or does not match the state of the internal flip-flop,
The state of the flip-flop is reversed.

In the protection circuit 480, the basic clock 121 is applied, and when the signal 471 indicating a mismatch of f is applied twice, it is assumed that synchronization has been lost and the signal 501 of g is set to "0", indicating a match. When the e signal 470 is repeatedly applied four times, the g signal 501 becomes "1", assuming that frame synchronization has been achieved. By doing so, protection is provided by preventing the signal 501 representing the synchronization state from immediately changing even if it receives noise.

The latch circuit 520 receiving the bus signal 440
The contents (frame number) of bus signal 440 of c latched at the timing of signal 288 are transferred to bus signal 52.
Send as 6.

FIG. 24A shows a specific circuit example of the frame counter 420, and FIG. 24B shows a timing chart of the waveforms of each part of the circuit.

The basic clock 121 of FIG. 24B a is applied to the clock terminal of the D flip-flop 421 via an inverter 430, the signal 287 of b is applied to its data terminal D, and the signal 442 of c is applied to its output Q. is obtained.

On the other hand, a signal 470 representing the coincidence of h is applied to the clock terminal of the D flip-flop 422 via an inverter 431, and its data terminal D is +
It is connected to 5V and becomes "1", and a signal 471 indicating a mismatch is applied to its reset terminal. When a signal 470 representing a coincidence of h is applied, a signal 445 of d of the output Q of the D flip-flop 422 becomes "1", and this state continues until a signal 471 representing a mismatch is applied. d
The g signal 445, the g signal 501, and the g signal 444 are ORed by two OR gates 428 and 429, and the output thereof is applied to the enable terminal of the decimal counter 424. When this enable terminal is "1", each time the signal 442 of c is applied to the decimal counter 424, it counts up.

Output Q0, Q1, Q2, Q3 of this counter 424
The signal 441 in FIG. 24B is obtained through the OR gate 425 and the NOR gate 426. This signal 441 indicates "1" when the frame number that is the content of the bus signal e is 0 and the signal 287 representing the beginning of the frame b is applied.
This indicates the presence of an F bit signal.

The basic clock 121 of FIG. 24Bb is applied to the clock terminal of the D flip-flop 423, and the OR gate 425 is applied to its data terminal D.
is applied, and the g signal 444 indicates "1" when the value of the e bus signal 440 is 1 to 9.
is output.

The enable terminal ENB of the counter 424 to which the output of the OR gate 429 is applied becomes "1" when the signal 501 representing the establishment of frame synchronization is "1" and the signal 470 representing the coincidence of h.
is applied, and when the value of the e bus signal 440, which is the output of the counter 424, is between 1 and 9, that is, when the g signal 444 is "1".

In this way, the enable terminal ENB becomes “1”
When , the counter 424 counts up and when the content of the bus signal 440 of e reaches 9, the outputs Q _B and Q _C are applied via the respective outputs Q _A and Q _D of the counter 424 and the inverters 432 and 433. The NAND gate 427 changes the f signal 443 from "1" to "0" and applies it to the load terminal LD to load 0, and the count is counted up again.

FIG. 25A shows an example of a specific circuit of the comparison circuit 450, and FIG. 25B shows a timing chart of waveforms of each part of the circuit. Here, in FIG. 25B, only the F bit of the demapped signal 90 is displayed, and all other data signals and control signals are displayed as "0".

Since the data terminal of the D flip-flop 453 is connected to its not Q output, each time the signal 475 of FIG. 25B j applied to the clock terminal is applied, the d signal 472 of its output Q is inverted. . The d signal 472 of the output Q of this D flip-flop 453 and the demapped signal 90 representing only the F bit of c are exclusively ORed by an exclusive OR gate 458, and the output thereof is sent to an inverter 460. through NAND Gate 454 and directly to NAND Gate 45
5. These Nando Gates 454
The b signal 441 is applied to the NAND gates 454 and 455, and the e signal 473 and the f signal 474, which are the outputs of the NAND gates 454 and 455, are applied to the data terminals D of the D flip-flops 451 and 452, respectively. is being applied.

These D flip-flops 451 and 45
Both clock terminals are connected to an inverter 459.
The basic clock 121 of a is applied to the output Q of the D flip-flop 451, and the signal 470 of h is applied to the output Q of the D flip-flop 452.
1 is output. Here, the h signal 470 is outputted as "0" when the c demapped signal 90 and the d signal 472 match, and when they do not match, the i signal 471 is outputted as "0".

Nott Q output of D flip-flop 452 and g
The signal 501 of j is ANDed by an AND gate 456, and its output is applied to a NOR gate 457, which is NORed with the not Q output of the D flip-flop 451 to obtain a signal 475 of j, which is
It is applied to the clock terminal of flip-flop 453. The signal 501 of g is a signal that indicates "1" when frame synchronization is established, and "0"
, and when 471 is "0", the D flip-flop 453 is not inverted. signal 50
1 is "1" and the signal 471 is "0" (when they do not match), the D flip-flop 453 is caused to be inverted. Regardless of the value of signal 501, when signal 470 is "0" (when there is a match), D flip-flop 453 is inverted.

FIG. 26A shows a specific embodiment of the protection circuit 480, and FIG. 26B shows a timing chart of waveforms at various parts thereof.

The not-Q output of D flip-flop 482 is connected to its data terminal D, its clock terminal is applied with the match signal 470 of FIG. 26B, and the b signal 502 is available at its Q output.

The b signal 502 and the a signal 470 are applied to an OR gate 488 and ORed together to obtain a c signal 503, which is applied to the up count terminal UC of the up down counter 481. Terminal A of this up-down counter 481 is set to "1" (+5V), terminals B, C, and D are set to "0", and when "0" is applied to the load terminal LD, the output terminal Q0 becomes “1”, Q1, Q2,
Q3 is set to "0". Up, down,
The down count terminal DC of the counter 481 has
d signal 471 is applied.

When the output terminal Q0 of e is "1" and the signal 503 of c is applied to the up count terminal UC when all Q1 to Q3 are "0", the output terminals Q0 to Q of e are applied to the up count terminal UC.
The count value of Q3 becomes 2, so the output terminal Q1 becomes "1". Next, when the signal 503 of c changes from “1” to “0”, the inverter 49
The output of the NAND gate 489 to which the signal 503 is applied through 1 goes from "1" to "0" like the signal 504 of f. A D flip-flop 483 receives this f signal 504 at its data terminal D.
Now, the basic clock 121 of g is received at the clock terminal, and the signal 505 shown in h is changed from "1" to "0".
Make it. This h signal 505 is connected to the preset terminal.
The D flip-flop 485 receiving PR changes the output Q from "0" to "1" as shown by the signal 501 of i.

The not-Q output of flip-flop 483 is D
It is applied to the data terminal of flip-flop 486, and the basic clock 121 is applied to its clock terminal via inverter 492, and its output Q
A signal having the opposite polarity to the first “0” signal of the j signal 506 is obtained, and this becomes the j signal 506 via the NOR gate 490.

This j signal 506 is applied to the load terminal LD of the up-down counter 481, and in order to load the value of the terminals A to D, that is, 1, the value of the outputs Q0 to Q3 of e becomes 1 again.

A signal 47 indicating a mismatch of d is sent to the down count terminal DC of the up/down counter 481.
When 1 is applied, the outputs Q0 to Q3 of e indicate 0, and when the second signal 471 of d indicating "0" is applied, the up/down counter 48
Since the count value of 1 becomes negative, a signal 509 of k indicating "0" is output from the borrow terminal BRW.

This signal 509 is applied to the data terminal of flip-flop 484, whose clock terminal has g
A basic clock 121 of 1 is applied, and a signal 507 of 1 is obtained at its not-Q output.

This l signal 507 is applied to the D flip-flop 4.
The signal 501 shown at i of the output Q changes from "1" to "0".
The l signal 507 is also applied to the data terminal D of the D flip-flop 487, whose output Q is as shown in the m signal 508. This m signal 508 is applied to a NOR gate 490 and the j signal 506
Obtain a signal indicating the second “0” of
06 is applied to the load terminal LD of the up-down counter 481 to load the value 1 set to the terminals A to D, so the values of the outputs Q0 to Q3 of e indicate 1 again.

In this way, the operation of counting up by the signal 470 of a and counting down by the signal 471 of d continues, and when the signal 470 indicating the match of a is applied four times in a row, i
The signal 501 of i changes from "0" to "1", and when the signal 471 indicating the mismatch of d is applied twice in succession, the signal 501 of i changes from "1" to "0".

FIG. 27 shows a specific example of the latch circuit 520. Here, the latch 521 has
A bus signal 440 representing a frame number is received at data terminals D0 to D3, and a signal 288 (FIG. 10B c)
(see FIG. 10B) is applied, the outputs Q0 to Q3 are outputted as a bus signal 526 (see FIG. 10B d).

FIG. 28A shows a specific embodiment of the SY bit receiving circuit 530, and FIG. 28B shows a timing chart of the waveforms of each part thereof. Here, the demapped signal 9 of FIG.
0 represents only the SY bit, and other data signals and control signals are shown as "0".

The signal 501 is applied to the reset terminals R of the D flip-flops 531, 532, 533 via two inverters 542, 543, and the signal 50
1 is “1”, the D flip-flop 531
The demapped signal 90 of FIG. 28Bb is applied to the data terminal D of
A signal 289 of c is applied, and a signal 552 of c is obtained at its output Q. This signal 552 is applied to the data terminal D of the D flip-flop 532;
At its output terminal Q, a signal 553 of d is obtained. This signal 553 is connected to the D flip-flop 53.
3, and its output Q has e
A signal 554 is obtained.

The not-Q output of each D flip-flop 531, 532, and 533 is applied to a NOR gate 537 whose output is applied to the data terminal of a D flip-flop 534. The clock terminal of this D flip-flop 534 has a signal 289 of a.
is applied via an inverter 541, and a signal 555 shown at f is obtained at its output Q.

The Q outputs of D flip-flops 531, 532, and 533 are applied to a NOR gate 538 whose output is applied to the data terminal of D flip-flop 536. This D flip-flop 53
A signal 289 of a is applied to the clock terminal of 6 through an inverter 541, and a signal 556 of h is obtained at its output Q.

The data terminal D of the D flip-flop 535 is set to "1" (+5V), and the h signal 556 and the signal 501 via the inverter 542 are applied to the reset terminal R via the NOR gate 539. There is. Also, flip-flop 535
The signal 555 of f is applied to the clock terminal of , and when the signal 501 is "1" and the signal 556 is "0", the reset terminal R is "1", so the signal 555 of f is applied. Then, the output Q becomes "1" as shown in the signal 551 of g, and then the signals 552, 553 of c, d, e,
When all 554 become "0", the data terminal D of the flip-flop 536 becomes "1", so the a signal 289 applied to the clock terminal via the inverter 541 causes the h signal 556 to become "1". goes from "0" to "1", and this signal 556 is reset through the NOR gate 539 to set the reset terminal R of the D flip-flop to "0", so that the output Q of the D flip-flop 535 becomes the signal of g. As shown in 551, it changes from "1" to "0".

When the signal 501 representing the synchronization state is "0", the reset terminal R of the D flip-flop 535
is reset to “0”, and the signal 55
1 always becomes "0".

The SY bit receiving circuit 5 shown in FIG. 28A
30, it is possible to sample 90 samples of the demapped signal representing only the SY bit in b using the signal 289 for sampling the SY bit in FIG. When the terminating device on the communication partner side
It is determined that the synchronization state has been reached with respect to the F bit, and the signal 551 of g is changed from "0" to "1".
Conversely, "0" of the demapped signal 90 representing only the SY bit of b three times in a row is changed to the signal 289 of a.
When sampled with , it is judged that the terminal device on the other side is no longer in synchronization with the F bit, and the signal 551 of g is changed from “1” to “0”.
Make it.

FIG. 29A shows an example of a specific circuit of the RD receiving circuit 560, and FIG. 29B shows a timing chart of waveforms of each part thereof. Here, the demapped signal 90 of FIG.
represents only data signals, and all other control signals are shown as "0".

In the S/P register 561 that converts 24-bit serial input data to parallel data, the second
The demapped signal 90 representing only the data in Figure 9B (b) is received at the data input terminal DI, sampled by the signal 290 (a) applied to the clock terminal, loaded, and output in parallel as 24-bit data. This 24-bit data output in parallel is
Applied to P/S register 562 which converts parallel data to serial data.

In the P/S register 562, this parallel data is loaded with “1” of the signal 262 of c, and the data is changed to “0”.
During the interval d, the received data RD of e is sequentially outputted by the clock 275.

FIG. 30A shows an example of a specific circuit of the CD receiving circuit 570, and FIG. 30B shows a timing chart of waveforms of each part thereof. Here, the demapped signal 90 in FIG. 30B represents only the received carrier detection signal CD, and all other control signals and data signals are shown as "0".

The demapped signal 90 of FIG. 30Bb is applied to the data terminal D of the D flip-flop 571, the signal 293 of FIG. . Then signal 264 of c
is applied to the clock terminal of the D flip-flop 572, the output Q signal 576 shown at d, which was previously at "0", becomes "1". If the demapped signal 90 representing only the received carrier detection signal CD of b is “0”, then the signal 26 of c
4 is applied, the received carrier detection signal of d
Signal 576, which is CD, indicates "0". 30th B
The arrow in the figure indicates that the demapped signal 90 in b is output by the signal 576 indicated by the arrow in d.

FIG. 31 shows an example of a specific circuit of the CS receiving circuit 580. D flip-flop 581
The data terminal D of the demapped terminal 9 of FIG.
0 is applied and a signal 294 of l having a period of 1.25 ms is applied to its clock terminal, the output Q is obtained, and this output Q is applied to the AND gate 5.
82. This AND gate 582 has signals 367 (see FIG. 20B, d) and 55
1 (see Figure 28B, g) is applied, and the clear-to-send signal CS of Figure 22B, m, is obtained at its output.
The terminal that receives this starts transmission.

FIG. 32 shows an example of a specific circuit of the DR receiving circuit 590. D flip flop 591
The demapped signal 90 of FIG. 22Bb is applied to the data terminal D of
signal 296 is applied to output the p data set ready signal DR.

The specific circuit of the CI receiving circuit 595 is the 32nd
The circuit is the same as the one shown in the figure, and instead of the signal 296, the signal 297 in Figure 22B g is applied, and the called indication signal CI (its value is indicated as "0") shown at r is the data. - Output in place of the set/ready signal DR.

In this way, various signals RD, CS, CD, DR, and CI are sent out in parallel from the demapping circuit 400 to the terminal device.

[Effect of the invention] As is clear from the above explanation, JIS-C6361
Various speeds based on regulations such as
128kbps, 192kbps, 256kbps, 384kbps,
If the device of the present invention is used as a terminating device for one LAN transmission line capable of transmitting data at one data rate of 1.536 Mbsp, 3.072 Mbps, etc., the operation of terminal devices of various speeds can be controlled more easily than this terminal device. Since it is now possible to synchronize with a LAN transmission line that has a high speed and a predetermined transmission speed, terminal devices can be freely connected to the LAN transmission line and synchronized to the timing of the LAN transmission line without the need for any operations. It became possible to transmit and receive data at the speed required by the terminal by converting the speed. Therefore, the effects of the present invention are extremely large.

[Brief explanation of the drawing]

Fig. 1 is a conceptual configuration diagram for explaining the operational concept of the present invention, Fig. 2 is a timing chart showing waveforms of each part in Fig. 1, and Fig. 3 is an embodiment of the termination device of the present invention. The configuration diagram, Fig. 4, represents the 3rd
5 and 6 are waveform timing charts for each part of the figure, and FIG. 7 is a timing chart showing the relationship between the timing signal generated by the timing generation circuit to the data terminal device and the data sampled by the data terminal device. is the timing generation circuit 2
FIGS. 8 and 9 are circuit configuration diagrams showing one embodiment of the clock timing circuit 240 included in the timing generation circuit 200 of FIG. Timing charts showing waveforms, Figures 10A and 10
Figure B is a circuit configuration diagram showing one embodiment of the reception timing circuit 280 included in the timing generation circuit 200 in Figure 7, and a timing chart showing the waveforms of each part thereof. The circuit configuration diagram and its state diagram, FIGS. 12A and 12B, showing one embodiment of the PLL circuit 100 are as shown in FIG.
A circuit configuration diagram showing one embodiment of the frequency dividing circuit 110 included in the PLL circuit 100 and a timing chart showing the waveforms of each part thereof, FIGS. 13A and 13
Figure B is a circuit configuration diagram showing one embodiment of the phase comparator circuit 130 included in the PLL circuit 100 of FIG. 11, a timing chart showing waveforms of each part, and a first
4A and 14B are a circuit configuration diagram showing one embodiment of the frequency division ratio control circuit 150 included in the PLL circuit 100 of FIG. 11, a timing chart showing waveforms of each part, and FIGS. 15A and 15B. 3 is a circuit configuration diagram showing an embodiment of the mapping circuit 300 in FIG. 3, and a timing diagram showing waveforms of each part.
Chart, Figures 16A and 16B are
A circuit configuration diagram showing an embodiment of the F bit sending circuit 310 in FIG. 5A and a timing chart showing waveforms of each part, FIGS. 17A and 17B are
A circuit configuration diagram showing an embodiment of the SD sending circuit 320 in Fig. A and a timing chart showing waveforms of each part, and Figs. 18A and 18B show an example of the CS' sending circuit 330 in Fig. 15A. The circuit configuration diagram and timing charts showing the waveforms of each part, Figures 19A and 19B, are the SY of Figure 15A.
A circuit configuration diagram showing an embodiment of the bit sending circuit 350, a timing chart showing waveforms of each part, and FIGS. 20A and 20B are similar to those shown in FIG. 15A.
A circuit configuration diagram showing an embodiment of the sending circuit 360 and a timing chart showing waveforms of each part, No. 21A
The diagram and FIG. 21B show the concentrator circuit 3 of FIG. 15A.
FIGS. 22A and 22B are a circuit diagram showing an embodiment of the demapping circuit 400 in FIG. 3 and a timing chart showing the waveforms of each part. Timing charts shown in Figures 23A and 23B.
22A is a block diagram showing an embodiment of the F-bit receiving circuit 410, and a timing chart showing the waveforms of each part. FIGS. 24A and 24B are
A circuit configuration diagram showing an embodiment of the frame counter 420 in FIG. 23A, a timing chart showing waveforms of each part, and FIGS. 25A and 25B are as follows:
FIG. 23A is a circuit configuration diagram showing an embodiment of the comparison circuit 450 and a timing chart showing waveforms of each part. FIGS. 26A and 26B are circuit configurations showing an embodiment of the protection circuit 480 in FIG. 23A. Timing chart showing diagrams and waveforms of each part, No. 27
23A is a circuit diagram showing an embodiment of the latch circuit 520 in FIG. 23A, and FIGS. 28A and 28B are circuit diagrams showing an embodiment of the SY bit receiving circuit 530 in FIG. 22A. Timing charts showing waveforms, FIGS. 29A and 29B are a circuit configuration diagram showing an embodiment of the RD receiving circuit 560 in FIG. 22A, and timing charts showing waveforms of each part, FIGS. 30A and 30B. teeth,
FIG. 22A is a circuit configuration diagram showing an embodiment of the CD reception circuit 570 and a timing chart showing waveforms of each part; FIG. 31 is a circuit configuration diagram showing an embodiment of the CS reception circuit 580 of FIG. 22A; FIG. 32 is a circuit configuration diagram showing an embodiment of the DR receiving circuit 590 of FIG. 22A, and FIGS. 33 and 34 are
A timing chart showing mapping time slots that accommodate conventional control signals and data; FIGS. 35, 36, and 37 are conceptual configuration diagrams of a conventional transmission system; FIG. FIG. 37 is a timing chart for explaining the operation, and FIG. 39 is a circuit configuration diagram for delaying the signal used in FIGS. 36 and 37. 5A, 5B...Terminal device, 8...LAN control device, 90...Demapped signal, 100...PLL
Circuit, 101... Oscillator, 105, 274, 27
5... Clock, 110... Frequency dividing circuit, 111...
...Hex counter, 112,249,250,31
2,323,332,351,364,456,
582...and gate, 113,114,1
31-133, 151-155, 311, 33
1,361,362,421~423,451~
453,482-487,531-536,57
1,572,581,591...D flip-flop, 115...96 base counter, 116,11
7,137,138,157,251~253,
283,313,430-433,459,46
0,491,492,541-543...Inverter, 121...Basic clock, 126-12
9,141-147,161-165,258,
260-267, 270-272, 278, 27
9,287~290,293,294,296~
298, 316, 317, 326, 336, 34
6,356,366~368,376,441~
445,470-475,501-509,55
1 to 556,576...Signal, 130...Phase comparison circuit, 134,156,427,454,45
5,489...Nand Gate, 135,13
6,426,457,490,537-539...
...Noah gate, 150...Division ratio control circuit, 2
00...Timing generation circuit, 240...Clock timing circuit, 241...8 stage S/P register, 242...24 base frame counter, 24
3... Decimal multi-frame counter, 24
4,246,247,281...Decoder, 24
5,282...flip-flop group, 248...
Decimal counter, 259, 276, 277, 28
6,440,526... bus signal, 280... timing circuit for reception, 300... mapping circuit, 310... F bit sending circuit, 320...
SD sending circuit, 321,561...S/P register, 322,562...P/S register, 330
...CS' sending circuit, 340...CI' sending circuit, 35
0...SY bit, 360...RS sending circuit, 36
3,381,425,428,429,488...
...OR gate, 370...ER sending circuit, 38
0...Concentrator circuit, 386...Map signal, 400
... Demapping circuit, 410 ... F bit receiving circuit, 420 ... Frame counter, 424 ...
... Counter, 450 ... Comparison circuit, 458 ... Exclusive OR gate, 480 ... Protection circuit, 481 ... Up-down counter, 5
20... Latch circuit, 521... Latch, 530
...SY bit receiving circuit, 560...RD receiving circuit, 570...CD receiving circuit, 580...CS receiving circuit, 590...DR receiving circuit, 595...CI receiving circuit, CD...receiving carrier detection signal, CI,
CI′...Called indication signal, CS, CS′...Send ready signal,
DIN...Data input, DOUT...Data output,
DR...Data set ready signal, ER...Data terminal ready signal, _L1 , _L2 ...Transmission/reception line, RD
... Reception data, REG _a , REG _b ... 24-stage shift register, RS ... Transmission request signal, RT ... Clock, SD ... Transmission data, ST2 ... Clock,
TIMP……Timing signal.

Claims (1)

[Claims] 1. A termination device for connecting a data terminal device to a LAN transmission path that accommodates data and control signals in a multi-frame configuration and can transmit at a predetermined transmission speed using a LAN timing signal TIMP. 5, the terminal device maps the data SD and control signals RS, CS'ER, and CI' from the data terminal device in a predetermined procedure to configure a multiframe and generates a map signal 38.
Bit 3 represents the frame for outputting 6.
F bit sending means 310 for sending out 16
and the data sent from the data terminal device.
SD sending means 320 for sending SD, CS' sending means 330 for sending 336 a send clear signal sent from the data terminal device, and a called indication signal sent from the data terminal device. CI' sending means 340 for sending 346 and sending SY bit 346 indicating that synchronization has been established.
SY bit sending means 350 for transmitting 56 data, and a transmission request signal sent from the data terminal device.
RS sending means 360 for sending out RS, and ER sending means 37 for sending out 376 a data terminal ready signal sent from the data terminal device.
0, the output 316 of the F bit sending means, the output 326 of the SD sending means, the output 336 of the CS' sending means, and the output 346 of the CI' sending means.
, the output 356 of the SY bit sending means, the output 366 of the RS sending means, and the output 376 of the ER sending means are condensed to generate the map signal 38.
a mapping means 300 including a concentrating means 380 for sending out the data RD and the control signals CS, CD,
F bit receiving means 410 for receiving F bits representing a frame in the demapped signal for sending DR and CI to the data terminal device at a predetermined timing; and for receiving data in the demapped signal. RD receiving means 560 for receiving the transmittable signal in the demapped signal.
CS receiving means 580 and CI receiving means 59 for receiving the called indication signal in the demapped signal.
5, SY bit receiving means 530 for receiving the SY bit indicating that synchronization has been established in the demapped signal, and CD receiving means 570 for receiving the received carrier detection signal in the demapped signal. , DR receiving means 590 for receiving a data set ready signal in the demapped signal; PLL clock 1 with repetition frequency
oscillation means 101 for generating 05;
Frequency dividing means 110 for obtaining the basic clock by dividing the PLL clock by a frequency division ratio instructed by phase control signals 161 to 163, and the phase of the frequency dividing operation in the frequency dividing means and the LAN timing. Comparison results 141, 14 by comparing the phase of the signal
2, and a frequency division ratio control means 150 for outputting the phase control signal in response to the comparison result from the phase comparison means.
PLL means 100 including: the basic clock generated by the PLL means;
A termination device comprising timing generating means 200 for transmitting a required timing signal from the LAN timing signal to the mapping means, the demapping means, and the data terminal device. 2. The timing generation means 200 receives the basic clock 121 and the LAN timing signal TIMP, and applies the mapping clock 2 to the mapping means 300.
74, a timing signal 259 for instructing a mapping position, a demapping clock 275 to be applied to the demapping means 400, and a timing signal 2 for instructing a demapping position.
86, a signal 276 indicating the position of each bit in the frame in the mapping means, and timing signals ST2, RT for the data terminal device.
Clock timing means 2 for outputting
40, the basic clock 121, a signal 276 indicating the position of each bit in the frame in the mapping means, and a signal 526 indicating the position of the frame in the signal to be demapped, 2. The terminal device according to claim 1, further comprising a reception timing means 280 for outputting a signal 286 indicating the position of each bit of the terminal. 3. The F-bit receiving means 410 receives the basic clock 121 and a signal 287 indicating the interval between frames in the demapped signal 90;
A frame for receiving a signal 470 representing a match, a signal 471 representing a mismatch, and a signal 501 representing a synchronization state, and outputting a frame number and a signal 440 representing a time point at which a specific number of the frame is output. - Counter means 420, the demapped signal 90, the basic clock 121, and the signal 501 representing the synchronization state.
and a signal 441 indicating that the specific number of the frame has been output, and a flip-flop 45 that changes its state each time it receives a signal indicating that the specific number of the frame has been output.
1,452, compares the state of the flip-flop with the demapped signal, and outputs a signal 470 representing the match when they match, and outputs a signal 470 representing the mismatch when they do not match.
a comparison means 450 for outputting 1; the basic clock 121; a signal 470 representing the match; and a signal 47 representing the mismatch.
1, outputs a signal 501 representing the synchronized state when a predetermined number of consecutive signals representing coincidence are received, and outputs a signal 501 representing the synchronized state when a predetermined number of consecutive signals representing mismatch are received. By not outputting a signal representing
2. The terminal device according to claim 1, further comprising protection means 480 for protecting the synchronization state. 4. The CS receiving means 580 receives the SY bit in the demapped signal 90;
2. The terminal device according to claim 1, wherein the input clear-to-send signal 551 and the request-to-send signal 367 sampled by the mapping means are ANDed and the clear-to-send signal CS is output.