JPH0574156A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To enable the defining of a data read accurately free from any very fine potential difference between a bit line and an inversion line in the reading of the data. CONSTITUTION:A common connection part of transistors Q3 and Q4 ina series circuit of the transistors Q3 and Q4 which compose a sense amplifier interposed between a bit line BL and an inversion bit line #BL is grounded through a transister Q6. A bit line potential amplification circuit comprising transistors Q7, Q8 and Q9 having different conductances is connected in parallel with the transistor Q6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit having a bit line potential amplifier circuit.

[0002]

2. Description of the Related Art A DRAM, which is a semiconductor memory circuit, includes a sense amplifier for reading data. This sense amplifier is basically composed of a flip-flop differential amplifier circuit, and compares the voltage of the data read from the memory cell with a reference voltage and amplifies the difference voltage to determine the data. I have to. A DRAM for reading data using a sense amplifier in this way is disclosed in, for example, Japanese Patent Laid-Open No. 2-306492.

FIG. 1 is a block diagram showing the main part of a conventional semiconductor memory circuit of this type. Bit line BL and inverted bit line
Between #BL, a series circuit of N-channel transistors Q ₁₀ and Q ₁₁ , a series circuit of N-channel transistor Q ₁₂ and P-channel transistors Q ₁ and Q ₂ forming a sense amplifier, and an N-channel transistor A series circuit of transistors Q ₃ and Q ₄ is interposed respectively. Transistor Q ₁₀ and Q ₁₁
The common connection portion with and is connected to the precharge power supply V _P, and the gates of the transistors Q ₁₀ , Q ₁₁ and Q ₁₂ are both connected to the equalize line EQL.

Gates of the transistors Q ₁ and Q ₃ are both connected to the inverted bit line #BL, and gates of the transistors Q ₂ and Q ₄ are both connected to the bit line BL. Bit line BL is N
A power supply V _CC , which will be described later, is supplied via a memory cell M _{0 formed} of a series circuit of a channel transistor Q ₁₃ and a capacitor C _0.
It is connected to the plate voltage power supply V _D which is a voltage of 1/2. The gate of the transistor Q ₁₃ is connected to the word line WL ₀ .

The inverted bit line #BL is connected to the plate voltage power supply V _D via a memory cell M ₁ which is a series circuit of an N-channel transistor Q ₁₄ and a capacitor C ₁ . The gate of transistor Q ₁₄ is connected to word line WL ₁ .
For example, the power source V _{CC of} 5 V is grounded through a series circuit of a P-channel transistor Q ₅ and N-channel transistors Q ₁₆ , Q ₁₇ , and Q ₆ . Transistors Q ₅ and Q ₁₆
Common connection portion between, the connected to the common connection serving node N2 between the transistor Q _1, Q _2, the common connection of the transistors Q ₁₇ and Q _6, the common connection of the transistors Q ₃ and Q ₄ It is connected to the barrel node N1.

An N-channel transistor Q ₁₅ is interposed between the nodes N1 and N2. Transistors Q ₁₅ , Q ₁₆ ,
The gate of Q ₁₇ is both connected to the equalize line EQL, and the common connection between the transistors Q ₁₆ and Q ₁₇ is connected to the precharge power supply V _P. Wherein the transistor Q ₆ is the conductance of the transistor Q ₇ greater than the conductance of the transistor Q ₆ is connected in parallel. These transistors Q ₆ and Q _{7 form a} bit line potential amplifier circuit. The sense amplifier activation signal φ ₀ is input to the gate of the transistor Q _5, the sense amplifier activation signal φ ₁ is input to the gate of the transistor Q ₆ , and the sense amplifier activation signal φ ₂ is input to the gate of the transistor Q _7. To be done.

Next, the data read operation of this semiconductor memory circuit
Figure 2 shows the timing chart of the signals of each part.
I will explain together. First, as shown in Fig. 2 (a),
Start up the line EQL and turn on the transistor Q_Ten, Q₁₁, Q₁₂as well as
Transistor Q₁₅, Q₁₆, Q ₁₇Turn on. By that
Bit line BL, inverted bit line #BL to precharge power supply V
_PTo precharge, and the nodes N1 and N2 have the same potential.
To

Due to this precharge, the potentials of the bit line BL and the inversion bit line #BL are normally set to 1/2 the potential of the power source V _CC . Next, as shown in Fig. 2 (a), the equalize line EQL
The after turning off the transistors Q _10, Q _11, Q ₁₂ and the transistor Q _15, Q _16, Q ₁₇ and to fall, for example in order to read data from the memory cells M _0, the word line WL ₀ connected thereto , As shown in FIG. 2 (b), the transistor Q ₁₃ is turned on and turned on.

Then, the potential of the memory cell M ₀ is applied to the bit line BL, and the potential of the bit line BL changes from the precharged potential. If data "1" is written in the memory cell M ₀ , the bit line BL
Is slightly higher than the potential of the precharge power supply V _P. Next, when the sense activation signal φ ₁ is raised as shown in FIG. 2D, the transistor Q ₆ having a conductance smaller than that of the transistor Q ₇ is turned on. The gate voltage at this time the transistor Q ₄ is is higher than the gate voltage of the transistor Q _3, the transistor Q ₄ is turned on first, the potential of the inverted bit line #BL begins to decrease.

Next, as shown in FIGS. 2 (c) and 2 (e), when the sense amplifier activation signal φ _{0 is set} to “0” and φ _{2 is set} to “1”,
Both the transistor Q ₅ and the transistor Q ₇ having a conductance larger than that of the transistor Q ₆ are turned on. When the transistor Q ₇ turns on, the inverted bit line #BL approaches the ground potential.

[0011] The gate voltage of the transistor Q ₁ is, is lower than the gate voltage of the transistor Q _2, and on the transistor Q ₁ is earlier, whereby the bit line BL is connected to a power supply V _CC, the bit lines BL The potential rises rapidly and is amplified rapidly. In this way, the memory cell M ₀
The read data is determined immediately before the change in the potential of the bit line BL from which the data is read is amplified and rapidly amplified.

FIG. 3 is a characteristic diagram showing the relationship between the potential of the bit line BL and the potential of the inverted bit line #BL measured by simulation, with the horizontal axis representing time and the vertical axis representing bit line and inverted bit line potentials. is there. As shown in this figure, the bit line BL and the inverted bit line #BL are precharged to have substantially the same potential at 0 ns (nanoseconds) when the equalize line EQL is raised. Then, when the word line WL ₀ is activated, the precharge potential of the bit line BL is slightly increased by the data read at 120 ns.

Next, when the sense amplifier activation signal φ ₀ falls and the sense amplifier activation signal φ ₂ rises 180 ns
Then, the power supply V _CC is connected to the bit line BL and the potential suddenly rises,
On the other hand, the inverted bit line #BL is grounded and suddenly drops and is amplified rapidly.

FIG. 4 is an enlarged view around the time point 180 ns in FIG. As shown in this figure, when the sense amplifier activation signal φ ₀ falls and the sense amplifier activation signal φ ₂ rises 180 ns, that is, immediately before the rapid amplification, the potential of the bit line BL and the inverted bit line # The potential difference from the BL potential is 0.35
It becomes V and the read data is confirmed.

[0015]

By the way, recent DRMA
Is highly integrated, the potential difference that the bit line potential changes from the precharge potential during data reading is extremely small as described above. Therefore, immediately after the bit line potential is changed from the precharge potential, the read data cannot be definitely determined, and there is a problem that the data read may become unstable.

In view of the above problems, the present invention is a semiconductor memory circuit in which data can be reliably determined even when the potential difference when the bit line potential changes from the precharge potential due to the data read is extremely small and the data can be read stably. The purpose is to provide.

[0017]

A semiconductor memory circuit according to the present invention includes a memory cell, a sense amplifier provided between a bit line and an inverted bit line, and a bit line potential amplification for amplifying the potential of the bit line. In the semiconductor memory circuit including a circuit, the bit line potential amplifier circuit is configured by connecting four transistors having different conductances in parallel.

[0018]

When reading the data, when the transistor having the smallest conductance among the third transistors is turned on, the potential of the common connection portion between the first transistor and the second transistor changes gently. Then, when the remaining three transistors are turned on in order from the one with the smallest conductance, the potential of the common connection portion is rapidly decreased stepwise.
When the second transistor is turned on, the potential of the common connection portion reaches a predetermined potential. This causes a large potential difference between the bit line and the inverted bit line immediately before the sense amplifier rapidly amplifies. Therefore, the read data can be reliably determined by this large potential difference.

[0019]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. First, the principle of the present invention will be described. Generally, the sensitivity ΔV _{SA of a} sense amplifier is

[0020]

[Equation 1]

It is represented by Here, α is the ratio of the falling speed of the bit line potential to the falling speed of the node potential on the side that lowers the potential of the sense amplifier, K is the lowering speed of the node potential, and β ₀ is the conductance of the transistor that lowers the potential. A constant, Δβ ₀ is a variation in the conductance constant of the transistor, ΔC _B is a variation in the bit line capacitance, and ΔV _th
Is the variation in the threshold voltage of the transistor that lowers the potential.

As shown in the equation (1), it is understood that the sensitivity of the sense amplifier increases as the decreasing rate K of the node potential decreases. Therefore, when operating the sense amplifier, when the change in the bit line potential is small, the node potential is gradually lowered using a transistor with a small conductance constant, and when the change reaches a predetermined value, the conductance constant changes. By sequentially operating a plurality of larger transistors and rapidly lowering them in multiple stages, and by confirming the read data at the time when they are lowered in multiple stages, the read data can be reliably and stably determined. ..

The present invention will be described in detail below with reference to the drawings showing its embodiments. FIG. 5 is a configuration diagram showing a configuration of a main part of a semiconductor memory circuit according to the present invention. Bit line BL and inverted bit line
Between #BL, a series circuit of N-channel transistors Q ₁₀ and Q ₁₁ , a series circuit of N-channel transistor Q ₁₂ and P-channel transistors Q ₁ and Q ₂ forming a sense amplifier, and an N-channel transistor A series circuit of transistors Q ₃ and Q ₄ is interposed. The common connection between the transistors Q ₁₀ and Q ₁₁ is connected to the precharge power supply V _P, and the gates of the transistors Q ₁₀ , Q ₁₁ and Q ₁₂ are both connected to the equalize line EQL.

The gates of the transistors Q ₁ and Q ₃ are both connected to the inverted bit line #BL, and the gates of the transistors Q ₂ and Q ₄ are both connected to the bit line BL. Bit line BL is N
A power supply V, which will be described later, is supplied via a memory cell M _{0 formed} of a series circuit of a channel transistor Q ₁₃ and a capacitor C _0.
It is connected to a plate voltage power supply V _D which is a voltage of 1/2 of _CC . The gate of the transistor Q ₁₃ is connected to the word line WL ₀ .

The inverted bit line #BL is connected to the plate voltage power supply V _D via the memory cell M ₁ which is a series circuit of an N-channel transistor Q ₁₄ and a capacitor C ₁ .
The gate of transistor Q ₁₄ is connected to word line WL ₁ . For example, the power source V _{CC of} 5 V is a P-channel transistor Q ₅ and N-channel transistors Q ₁₆ , Q ₁₇ , and Q _6.
It is grounded through a series circuit with. A common connection portion between the transistors Q ₅ and Q ₁₆ is connected to a node N _{2 which} is a common connection portion between the transistors Q ₁ and Q ₂ and
The common connection portion between ₁₇ and Q ₆ is connected to the common connection serving node N1 of the transistor Q ₃ and Q _4.

An N-channel transistor Q ₁₅ is interposed between the nodes N1 and N2. Transistors Q ₁₅ , Q ₁₆ ,
The gate of Q ₁₇ is both connected to the equalize line EQL, and the common connection between the transistors Q ₁₆ and Q ₁₇ is connected to the precharge power supply V _P. Transistors Q ₇ , Q ₈ , and Q ₉ are connected in parallel to the transistor Q ₆ . These transistors _{Q 6, Q 7, Q 8} , Q 9 constitute a bit line potential amplifying circuit by.

The conductances of the transistors Q ₆ , Q ₇ , Q ₈ , and Q ₉ are selected to have larger values in that order.
These transistors Q ₆ , Q ₇ , Q ₈ and Q ₉ have a channel length L and a channel width W, respectively.
Since the conductance is proportional to W / L, the transistors Q ₆ , Q ₇ , Q ₈ and Q ₉ have the same channel length L,
The channel width W is changed.

The gate of the transistor Q ₅ receives the sense amplifier activation signal φ ₀ , the gate of the transistor Q ₆ receives the sense amplifier activation signal φ ₁ , the transistors Q ₇ ,
The sense amplifier activation signal phi ₂ to the gate of Q _8, Q _9,
phi _3, phi ₄ is input to each another.

Next, the data read operation of this semiconductor memory circuit will be described with reference to FIG. 6 which shows a timing chart of signals at respective parts. First, turn on the transistor Q _10, Q _11, Q ₁₂ and the transistor Q _15, Q _16, Q ₁₇ and the equalizing line EQL raised as shown in Figure 6 (a). As a result, the bit line BL and the inverted bit line #BL are set to the precharge power source V
_{It is} precharged by _P, and the nodes N1 and N2 are set to the same potential.

Due to this precharge, the potentials of the bit line BL and the inverted bit line #BL are normally set to a half of the voltage of the power source V _CC . Next, as shown in Fig. 6 (a), the equalize line EQL
The after turning off the transistors Q _10, Q _11, Q ₁₂ and the transistor Q _15, Q _16, Q ₁₇ and to fall, for example in order to read data from the memory cells M _0, the word line WL ₀ connected thereto , As shown in FIG. 6B, the transistor Q ₁₃ is turned on to turn on the transistor Q ₁₃ .

Then, the potential of the memory cell M ₀ is applied to the bit line BL, and the potential of the bit line BL changes from the precharged potential. If data "1" is written in the memory cell M ₀ , the bit line BL
Is slightly higher than the potential of the precharge power supply V _P. Next, as shown in FIG. 6D, when the sense amplifier activation signal φ ₁ is raised, the transistor Q ₆ having a conductance smaller than the conductance of any of the transistors Q ₇ , Q ₈ , and Q ₉ is turned on. The gate voltage at this time the transistor Q ₄ is is higher than the gate voltage of the transistor Q _3, and on the transistor Q ₄ is previously inverted bit line #B
The potential of L begins to fall gradually.

Subsequently, as shown in FIGS. 6E and 6F, when the sense amplifier activation signals φ ₂ and φ ₃ are sequentially set to “1”, the transistor Q ₇ having a conductance larger than that of the transistor Q ₆ is turned on. Then transistor Q ₇
The transistor Q ₈ having a conductance larger than the conductance of turns on. As a result, the potential of the bit line BL drops rapidly. Next, as shown in FIGS. 6C and 6G, when the sense amplifier activation signal φ ₀ is lowered and the sense amplifier activation signal φ ₄ is simultaneously raised, the conductances of the transistor Q ₅ and the transistor Q ₈ The large conductance transistor Q ₉ is turned on.

When the transistor Q ₉ is turned on, the inverted bit line #BL becomes the ground potential. Since this time the gate voltage of the transistor Q ₁ is lower than the gate voltage of the transistor Q _2, the transistor Q ₁ is turned on earlier, thereby the potential of the bit line BL is the bit line BL is connected to a power supply V _CC soared rapidly It will be amplified to. In this way, the read data is determined immediately before the change in the potential of the bit line BL that has read the data from the memory cell M ₀ is amplified and rapidly amplified.

That is, the bit line is formed by the transistor Q _6.
After amplifying the potential of BL, transistors Q ₇ , Q ₈ ,
The signal is amplified in multiple stages by Q _{9, and} after a predetermined time has passed since the transistor Q ₆ was turned on, the inverted bit line becomes the ground potential, and when the potential difference between the bit line and the inverted bit line becomes large, the read operation is performed. Data will be finalized,
Even if the bit line potential is extremely small, the read data can be definitely determined and can be stably determined.

FIG. 7 is a characteristic diagram showing the relationship between the potential of the bit line BL and the potential of the inverted bit line #BL, with the horizontal axis representing time and the vertical axis representing the bit line and inverted bit line potentials. As is clear from this figure, the bit line BL and the inverted bit line #BL are precharged to have substantially the same potential at 0 ns (nanosecond) when the equalize line EQL is raised. And word line WL ₀
The bit line is read by reading the data at 120ns when the
The precharge potential of BL rises slightly.

Then, the potential of the inversion bit #BL starts to drop from 165 ns when the sense amplifier activation signal φ ₁ rises, and the inversion bit line #BL of the inversion bit line #BL starts every time the sense amplifier activation signals φ ₂ and φ ₃ rise. The potential drops sharply, the sense amplifier activation signal φ ₀ falls, and the sense amplifier activation signal φ ₄
The inverted bit line #BL becomes the ground potential 180ns after the start-up.

FIG. 8 is an enlarged view around 180 ns in FIG. As is clear from this figure, the potential difference between the bit line BL and the potential of the inverted bit line #BL is 180 ns when the sense amplifier activation signal φ ₀ falls and φ ₄ rises, that is, immediately before the rapid amplification. Becomes 2.4 V, and the read data is confirmed by this.

Therefore, when the two transistors Q ₆ and Q ₇ are used as in the conventional case, the potential difference immediately before the rapid amplification is 0.35 V as shown in FIG. using transistors _{Q 6, Q 7, Q 8} , Q 9, if you let them sequentially turned on, the potential difference just prior to the more rapid amplification to 2.4 V, can without significantly large. Thus, four transistors having different conductances are suitable, and when two or three transistors are used, the potential of the inverted bit line #BL before the rapid amplification does not reach 0V.

When five or more transistors are used, the inversion bit line #BL is already 0 before the final stage transistor is turned on.
Since it has reached V, the transistor at the final stage does not serve to reduce the potential of the inverted bit line #BL.

The transistors Q ₆ , Q ₇ , Q ₈ , Q
The channel width of ₉ is 2.0 μm for the transistor Q ₆ and 1.0 μm for the transistor Q ₇ when the channel length L is 1.0 μm.
4.0 μm, transistor Q ₈ 6.0 μm, transistor Q ₈ 8.0 μm. That is, the minimum channel length is L _min
Assuming that the minimum channel width is W _min , as a result of simulation, the channel lengths of the transistors Q ₆ , Q ₇ , Q ₈ , Q ₉ are always L _min , and the channel width is W _min , 2
W _min, 3W _min, that may be set to 4W _min was confirmed.

[0041]

As described in detail above, according to the present invention, four transistors having different conductances are connected in parallel to a transistor for connecting a common connection portion of transistors connected in series in a sense amplifier to a predetermined potential. Since the common connection portion is made to reach a predetermined potential when the fourth transistor is operated by sequentially operating those transistors, the bit line and the inversion bit are set immediately before the sense amplifier amplifies rapidly. A large potential difference can be obtained with the line.

Therefore, the read data can be surely and stably determined even when the change in the bit line potential is small. Therefore, according to the present invention, it is possible to provide an excellent effect that a highly reliable semiconductor memory circuit in which a data read error does not occur even if circuits are integrated is provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a main part of a conventional semiconductor memory circuit.

FIG. 2 is a timing chart of signals of respective parts in FIG.

FIG. 3 is a characteristic diagram showing a relationship between a bit line potential and an inverted bit line potential.

FIG. 4 is an enlarged view in which a part of FIG. 3 is enlarged.

FIG. 5 is a configuration diagram showing a main part configuration of a semiconductor memory circuit according to the present invention.

FIG. 6 is a timing chart of signals of respective parts in FIG.

FIG. 7 is a characteristic diagram showing a relationship between a bit line potential and an inverted bit line potential.

FIG. 8 is an enlarged view in which a part of FIG. 7 is enlarged.

[Explanation of symbols]

Q _1, Q ₂ ... Q ₁₇ transistors BL bit lines #BL inverted bit line WL _0, WL ₁ word line EQL equalizing line M _0, M ₁ memory cell V _CC supply V _P precharge power source V _D plate voltage supply

Claims (1)

[Claims] 1. A semiconductor memory circuit comprising a memory cell, a sense amplifier provided between a bit line and an inverted bit line, and a bit line potential amplifier circuit for amplifying the potential of the bit line. The semiconductor memory circuit is characterized in that the potential amplifier circuit is configured by connecting four transistors having different conductances in parallel.