JPH0574151A - Emulation circuit for dynamic memory - Google Patents

Abstract

PURPOSE:To achieve higher efficiency of a memory access preventing emulation between a refreshing cycle and a CPU cycle and a DMA cycle. CONSTITUTION:When emulation occurs between a refreshing demand signal 6 to be outputted from a refreshing demand signal generating section 3, a DMA demand signal 5 to be outputted from a DMA controller 2 and a CPU access demand signal 4 to be outputted from a CPU1, a memory status generation part 7 starts a processing with a demand high in preference. In the emulation with the DMA demand signal 5, when the refreshing cycle is preferred, a weight is set on the DMA controller 2 with a DMA weight generation part 8. In the emulation with the CPU access demand signal 4, when the refreshing cycle is preferred, the CPU1 is under a weight until a RDY signal 20 is outputted from a RDY signal generation part 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competition circuit for an access cycle and a refresh cycle of a dynamic memory (hereinafter abbreviated as DRAM). The present invention relates to a dynamic memory contention circuit suitable for preventing a decrease in memory access speed due to contention.

[0002]

2. Description of the Related Art As a conventional technique for coping with competition between a DRAM access cycle and a refresh cycle, there is one disclosed in Japanese Patent Laid-Open No. 1-276488. In this conventional technique, when the direct memory access request signal from the device other than the CPU and the refresh cycle request signal compete with each other, the direct memory request is preferentially executed, and the refresh request signal is held during the direct memory access. A refresh cycle is performed after the direct memory access is completed.

[0003]

In the above prior art, when the refresh request signal and the direct memory access request signal from a device other than the CPU conflict with each other, the DMA cycle is always prioritized and executed, and the refresh cycle is prioritized. Never do. Also, when the refresh request signal is output earlier and a direct memory access request is issued by a device other than the CPU during execution of this refresh cycle, there is no consideration of wait insertion for the DMA cycle, and the memory access speed is not considered. However, there is a problem that

An object of the present invention is to prevent a decrease in memory access speed when a refresh request signal and a direct memory access request signal from a device other than a CPU compete with each other in a memory system using a DRAM which requires a data holding operation. It is to provide a competing circuit capable of doing so.

[0005]

SUMMARY OF THE INVENTION In a memory system using a DRAM having a data holding function, the above object is to be satisfied when a DRAM refresh request signal and a DMA memory access request signal with a device other than a CPU as a bus master compete with each other. In addition, the contention timing can be achieved by deciding which of the refresh cycle and the DMA cycle is preferentially performed before or after the DMA command is output. The above object is also to execute the CPU cycle with priority when the refresh request signal and the CPU access request signal compete during an idle period in which both the CPU and a device other than the CPU are not bus masters. This is achieved by giving priority to the refresh cycle during the suspension of the fast page mode. The above object is also achieved by inserting a DMA wait according to the time required until the end of the refresh cycle when a memory access request by a device other than the CPU occurs during execution of the refresh cycle.

[0006]

Since the conflict between the refresh cycle and the DMA cycle by the device other than the CPU and the conflict between the refresh cycle and the memory cycle in which the CPU is the bus master are avoided, the refresh cycle for holding the stored data is executed in the control of the DRAM. It is possible to prevent the memory access speed from being lowered due to the above, and to prevent the malfunction of the memory system due to the competition between the refresh cycle and the memory access cycle.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a dynamic memory contention circuit according to an embodiment of the present invention. The request signal 4 output from the CPU 1, the request signal 5 output from the DMA controller 2, and the refresh request signal generator 3
The request signal 6 output from is input to the memory status generation unit 7 and the DMA weight generation unit 8. When the request signals 4, 5, and 6 do not conflict with each other, the DMA weight generation unit 8 outputs a weight setting signal 9 for setting 0 weight to the DMA controller 2. Further, the memory status generation unit 7 outputs the CPU status signal 10, the DMA status signal 11 or the refresh status signal 12 to the memory control signal generation unit 13 according to the single access request signal 4, 5 or 6. The memory control signal generation unit 13 uses the status signals 10, 11 or 1
According to the input signal of 2, the row address strobe signal 14
(RAS-N signal), column address strobe signal 1
5 (CAS-N signal), memory write enable signal 1
6 (MWEN signal) and output enable signal 1
7 (OE-N signal) is output to control the memory chip 18.

When the DMA request signal 5 and the refresh request signal 6 compete with each other, the DM from the DMA controller 2
If the A command signal 19 has already been output to the DMA weight generation unit 8 and the memory status generation unit 7, the DMA weight generation unit 8 outputs a 0 weight setting signal to the DMA controller 2, and the memory status generation unit 7 causes the DMA,
The status signals 11 and 12 are output to the memory control signal generation unit 13 in the order of refresh, and the cycle is executed in the order of DMA and refresh. Also, the DMA controller 2
If the request signals 5 and 6 compete with each other before outputting the DMA command 19, the memory status generator 7 outputs status signals 11 and 12 in the order of refresh and DMA, and the cycle is executed in the order of refresh and DMA. It At this time, the DMA weight generation unit 8 outputs to the DMA controller 2 a wait setting signal 9 that allows execution of the DMA cycle after execution of the refresh cycle.

When the CPU access request signal 4 and the refresh request signal 6 compete with each other, the state of the memory control signal at this time is that the high speed page mode is being executed (RAS-N signal 14).
(Asserted state), the memory status generation unit 7 outputs status signals 10, 12 in the order of CPU and refresh.
Is output, and the cycle is executed in the order of CPU and refresh. If the state of the memory control signal is the high-speed page mode suspended state (RAS-N signal 14 negated state), the memory status generation unit 7 outputs the status signals 10 and 12 in the order of refresh, CPU, refresh,
The cycle is executed in the order of CPU. At this time, CPU1
The RDY signal 20 for recognizing the end of the cycle is C
It is generated by the RDY signal generation unit 21 by the PU status signal 10. Therefore, in the competition between the CPU and the refresh cycle, even if the refresh cycle is preferentially executed, the CPU 1 is in the wait state until the CPU cycle is executed.

When the DMA request signal 5 is output from the DMA controller 2 during execution of the refresh cycle, the refresh status signal 12 output from the memory status generator 7 recognizes the execution state of the refresh cycle, and the subsequent DMA is executed. The DMA weight generation unit 8 generates the DMA weight necessary for executing the cycle,
Output to the DMA controller 2. FIG. 2 shows state transitions in each cycle of the competitive circuit shown in FIG. In the figure, two stages of C0 and C1 indicate a CPU cycle, three stages of D0, D1 and D2 indicate a DMA cycle, three stages of R0, R1 and R2 indicate a refresh cycle, and two stages of I0 and I1 are the above. Indicates an idle period when neither cycle is performed.
However, the I0 stage is in the high-speed page mode suspended state (RA
S-N signal negated state) indicates an idle period, I
The two stages show the idle periods in the fast page mode continuation state (RAS-N signal asserted state).

FIG. 3 is a time chart when the DMA request signal 5 and the refresh request signal 6 compete with each other before the DMA command 19 is output. When the DMA request signal 5 is output during the idle period of the I0 stage, the process proceeds to the DMA stage D0. Since the DMA command 19 is output in the DMA stage D1, when the refresh request signal 6 is output in the DMA stage D0, the DMA stage D0 shifts to the refresh stage R0 and the refresh cycle is preferentially executed. Since the DMA controller 2 continues the DMA cycle during this period, R
The DMA wait generator 8 outputs the 3 wait setting signal 9 corresponding to the refresh cycle period of 0, R1, R2 from the DMA wait generator 8.
Output to the MA controller 2. Transition from the refresh stage R2 to the DMA stage D1 and wait for DMA
Run the cycle. FIG. 4 is a time chart when the DMA request signal 5 and the refresh request signal 6 compete with each other after the DMA command 19 is output. In this case, the previously requested DMA cycle is executed in the order of D0, D1, and D2, and then the process moves to the refresh stage R0 to execute the refresh cycle. At this time, since the DMA cycle is not interrupted by the refresh request signal 6, the DMA wait generator 8 outputs the 0 wait setting signal 9 to the DMA controller 2. in this way,
When the DMA request signal 5 and the refresh request signal 6 compete with each other, DM is output according to the output status of the DMA command 19.
The refresh cycle necessary for holding the internal data of the memory chip 18 can be surely performed without lowering the access speed of the A cycle.

In FIG. 5, when the CPU access request signal 4 and the refresh request signal 6 are in the high speed page mode interruption (RA
9 is a time chart in the case where the CPU and the device other than the CPU compete with each other during the idle period in which the S-N signal 14 is negated). When both the CPU access request signal 4 and the refresh request signal 6 are output during the idle period of the I0 stage, the process proceeds to the refresh stage R0 and the refresh cycle is executed. After execution of the refresh cycle, the stage moves from the refresh stage R2 to the CPU stage C0 to execute the CPU cycle according to the CPU access request signal 4. C
The PU cycle is ended by recognizing the RDY signal 20 generated from the CPU status signal 10. Therefore, the CPU cycle is inevitably in the wait state during the execution of the refresh cycle. Further, in this race condition, the DMA wait setting signal 9 is not set and the 0 wait remains.

In FIG. 6, when the CPU access request signal 4 and the refresh request signal 6 are in the high speed page mode (RA
FIG. 6 is a time chart in the case where the CPU and the device other than the CPU compete with each other during the idle period in which the S-N signal 14 is asserted). When both the CPU access request signal 4 and the refresh request signal 6 are output during the idle period of the I1 stage, it is possible to shift to the CPU stage C1 and execute the CPU cycle in the fast page mode. After executing the 0-wait high-speed page mode by I1 and C1, the process shifts to the R0 stage to execute the refresh cycle by the refresh request signal 4. As described above, when the CPU access request signal 4 and the refresh request signal 6 compete during the idle period, the CPU cycle is preferentially executed while the high-speed page mode continues, so that the memory access accompanying the execution of the refresh cycle is executed. It is possible to prevent a decrease in speed.

FIG. 7 shows R during the refresh cycle.
It is a time chart when the DMA request signal 5 is output in the 0 stage. In this case, in the DMA cycle by the DMA request signal 5, since the R1 stage corresponds to the D0 stage, the DMA wait generator 8 outputs the 1 wait setting signal 9 so that the DMA wait is set during the next R2 stage. It is output to the DMA controller 2. When the refresh cycle is completed, the R2 stage shifts to the D1 stage and the waiting DMA cycle is executed.

FIG. 8 shows R during the refresh cycle.
6 is a time chart when the DMA request signal 5 is output in one stage. In this case, in the DMA cycle by the DMA request signal 5, since the R2 stage corresponds to the D0 stage, DM is executed during the refresh cycle.
Since it is not necessary to insert the A weight, the DMA weight generator 8 outputs the 0 weight setting signal 9 to the DMA controller 2. When the refresh cycle ends, the R2 state shifts to the D1 state and the DMA cycle is executed.

FIG. 9 shows R during the refresh cycle.
6 is a time chart when the DMA request signal 5 is output in the two stages. In this case, since the DMA cycle by the DMA request signal 5 is activated after the refresh cycle is completed, the R2 stage shifts to the D0 stage and is executed. In this case, since it is not necessary to set the DMA wait associated with the execution of the refresh cycle, the DMA wait generator 8 outputs the 0 wait setting signal 9 to the DMA controller 2. in this way,
When the DMA request signal 5 is output during execution of the refresh cycle, D is output according to the execution state of the refresh cycle.
It is possible to determine the value of the MA weight setting signal 9.

In the present embodiment, for simplicity, the number of statuses in each memory cycle is reduced, and the transition of each status is basic. However, the memory status generator 7 depends on the environment of the memory system. It can be arbitrarily set by changing the configuration method of.

[0018]

According to the present invention, in the control of the dynamic memory, it is possible to prevent the refresh cycle necessary for holding the memory data and the DMA cycle contention in which a device other than the CPU is used as the bus master. In addition, it is possible to prevent contention between the refresh cycle and the memory access cycle in which the CPU is the bus master.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a competitive circuit according to an embodiment of the present invention.

FIG. 2 is a state transition diagram of a memory status generated by a memory status generation unit shown in FIG.

FIG. 3 is a time chart of refresh priority when a refresh request signal and a DMA request signal compete with each other.

FIG. 4 is a time chart of DMA priority when a refresh request signal and a DMA request signal compete with each other.

FIG. 5 is a time chart of refresh priority when a refresh request signal and a CPU cycle request signal compete with each other.

FIG. 6 is a time chart of CPU priority when a refresh request signal and a CPU cycle request signal compete with each other.

FIG. 7 is a 1-wait time chart when a DMA request signal is output to the R0 stage during execution of a refresh cycle.

FIG. 8 is a time chart of 0 wait when a DMA request signal is output to the R1 stage during execution of a refresh cycle.

FIG. 9 is a time chart of 0 wait when a DMA request signal is output to the R2 stage during execution of a refresh cycle.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... DMA controller, 3 ... Refresh request signal generation part, 4, 5, 6, 9-12, 14-1
7, 19, 20 ... Signal line, 7 ... Memory status generation unit, 8 ... DMA wait generation unit, 13 ... Memory control signal generation unit, 18 ... Memory chip, 21 ... RDY signal generation unit, I0, I1 ... During idle period Status, C0,
C1 ... CPU cycle status, D0, D1, D2
... DMA cycle status, R0, R1, R2 ... Refresh cycle status.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Shiobara 292 No. Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company Hitachi Imaging Information Systems (72) Inventor Masahiko Otaki 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Ceremony Company Hitachi Image Information System (72) Inventor Masato Hiroi 7-1-1 Higashi Narashino, Narashino, Chiba Prefecture Hitachi Systems Design and Development Center

Claims (1)

[Claims] 1. In a memory system using a dynamic memory as a compact and high-density storage device, a direct memory using a refresh cycle request signal necessary for holding data stored in the dynamic memory and a device other than a CPU as a bus master. When conflicting access request signals occur before the memory read / write command output from the direct memory access controller (hereinafter abbreviated as DMA controller), the refresh cycle is prioritized and executed. A means for inserting a wait cycle, a means for executing a refresh cycle after the execution of a DMA cycle without inserting the DMA wait if there is a conflict during the output of the command signal, and a means for immediately following a conflict after clearing the command signal Refresh service A dynamic memory competing circuit comprising means for executing an icle.