JPH0574140A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To enable preparation of a design having an increased stability for a range of fluctuation of voltage and to realize a test of reliability of a large- capacity semiconductor memory with ease. CONSTITUTION:A regulator circuit 1 receives an externally supplied source voltage VCC as an input and generates an internal voltage on the occasion of supplying the voltage to a memory element and memory peripheral circuit 3. This regulator circuit 1 functions as an internal step-down circuit. Besides, a low-impedance switch 2 is provided separately from this regulator circuit 1 and it supplies the memory element and memory peripheral circuit 3 with a voltage being different from the output of the regulator 1. These different voltages are supplied selectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a large capacity semiconductor memory circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor memory circuit, it is common to use an external voltage directly as a driving power source. However, as the capacity of the memory circuit increases, the miniaturization of the transistors constituting the memory element and the peripheral circuit becomes smaller. At the same time, the breakdown voltage of the transistor is lowered and the power consumption is increased. For this reason, conventionally, a regulator circuit using an externally supplied power supply voltage as an input voltage is provided inside the semiconductor memory, and it is generally used as an internal step-down circuit for lowering the externally supplied power supply voltage as a normal means for a large-capacity memory circuit. is there. That is, by using the internal step-down circuit, both low power consumption and high integration can be realized. For example, the power supply voltage of a normal large-capacity memory circuit is 5V ± 1 which is common to the TTL circuit.
A power supply voltage of 0% is used.

On the other hand, as a large capacity memory circuit of 16 MDRAM and 4 MSRAM or more, an external voltage of 3 V ± 10%
Alternatively, the power supply voltage of 3.3V ± 10% is being standardized. At the same time, a semiconductor memory circuit is also used in which a step-down circuit is formed inside a semiconductor memory circuit by using an external TTL power source and an internal step-down circuit, and the voltage is lowered to a voltage equal to or lower than a required TTL power source inside the memory circuit.

[0004]

The semiconductor memory circuit having the conventional internal voltage step-down circuit described above is newly standardized from the normally used external voltage of 5V ± 10% to 3V.
Alternatively, in order to switch to a voltage of 3.3V ± 10%, it is necessary to maintain the internal voltage down converter having a large current capacity and stable including a temperature change. This circuit configuration has a drawback in that it is difficult to stabilize the generated voltage of internal step-down, especially when the external voltage drops. Further, in the conventional semiconductor memory circuit, even if the external voltage is changed in the reliability test of the semiconductor memory, the voltage applied to the internal memory element is reduced by the voltage generated by the internal step-down. There is a drawback that the reliability test of cannot be performed sufficiently.
Further, in the conventional semiconductor memory circuit, since there are two kinds of power supply required for the memory device, that is, a 5V power supply and a 3V or 3.3V power supply, it is difficult to simultaneously meet two kinds of power supply requests. There is.

An object of the present invention is to realize a stable design against such voltage fluctuations, to facilitate a reliability test of a large capacity semiconductor memory, and to make it possible to cope with various power sources. To provide.

[0006]

A semiconductor memory circuit according to the present invention comprises a memory element and a memory peripheral circuit, a regulator circuit for inputting an external power supply voltage to generate an internal voltage, and the external power supply voltage directly. A low impedance switch supplied as an internal power supply voltage, and the output voltage of the regulator circuit or the voltage via the low impedance switch is used as the internal power supply voltage.

Also, the semiconductor memory circuit of the present invention receives a memory element and a memory peripheral circuit, a first power supply pad for supplying a first external power supply voltage, and the first external power supply voltage. A regulator circuit for generating an internal voltage, and a second power supply pad for directly supplying a second external power supply voltage different from the first external power supply voltage to the memory element and the memory peripheral circuit as an internal voltage. Configured.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory circuit showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, a memory element and a memory peripheral circuit 3, a regulator or an internal step-down circuit 1 that supplies the memory element and the memory peripheral circuit 3 by stepping down a power supply voltage VCC, and an external power supply VCC. And a switch 2 such as a low-impedance fuse connected to bypass the regulator circuit or the internal step-down circuit 1. In such a semiconductor memory circuit, when the low impedance switch 2 is not opened, the external power supply voltage VCC is directly supplied to the memory element and the memory peripheral circuit 3. When the switch is opened, the output voltage of the regulator circuit or the internal step-down circuit 1 is supplied as the power source of the memory element and the memory peripheral circuit 3. In this way, either the external power supply VCC or the voltage obtained by stepping down the external power supply VCC can be selectively supplied, so that a more stable design can be performed with respect to the voltage fluctuation range. Further, since the external voltage can be directly supplied, the reliability test of the large-capacity semiconductor memory can be easily realized, and any power source can be supported.

FIG. 2 is a block diagram of a semiconductor memory circuit showing a second embodiment of the present invention. As shown in FIG. 2, this embodiment is constructed by providing two or more power supply pads 4 and 5 inside a semiconductor memory circuit. That is, the first
When wire bonding is performed only on the power supply pad 4 of FIG. 1, the external power supply VCC is applied to the first VCC pad 4, and the output voltage of the regulator circuit or the internal step-down circuit 1 which has been stepped down is supplied to the memory element and the memory peripheral circuit 3. Supplied as an internal voltage. At this time, since the second power supply pad 5 is not bonded, it is in an open state. Conversely, bonding to the second power supply pad 5
When the power supply pad 4 is opened or the first power supply pad 4 is also bonded, the external power supply voltage VCC is directly applied as the internal voltage of the memory element and the memory peripheral circuit 3. Therefore, in this embodiment, the power supply used for the semiconductor memory circuit is selected by preparing two or more bonding pads 4 or 5 for the external power supply and the internal step-down power supply. With this configuration, this embodiment can also obtain the same result as that of the first embodiment described above.

[0011]

As described above, the semiconductor memory circuit of the present invention has means for directly supplying the external power supply as the power supply and means for supplying the output power supply voltage of the internal regulator circuit or the internal step-down circuit. , The regulator circuit or the internal step-down circuit uses an external power source 5 common to TTL.
It is necessary to design only to generate the internal voltage required for the device from the V ± 10% power source, and the power source such as 3V or 3.3V ± 10% directly uses the external voltage, so that it is much better than the voltage fluctuation range. The effect is that a stable design can be realized. Further, according to the present invention, since the test voltage can be directly supplied to the internal memory circuit or the memory element by the external voltage without using the internal step-down circuit in the reliability test, the reliability test of the large capacity semiconductor memory is facilitated. The effect is that it can be implemented. Furthermore, the present invention has an effect that it is possible to meet the demands of the apparatus for the 5V power supply and the low voltage power supply.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory circuit showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a semiconductor memory circuit showing a second embodiment of the present invention.

[Explanation of symbols]

 1 Regulator Circuit 2 Low Impedance Switch 3 Memory Element and Memory Peripheral Circuit 4 First Power Supply (VCC) Pad 5 Second Power Supply (VCC) Pad

Claims (2)

[Claims] 1. A memory device and a memory peripheral circuit, a regulator circuit for inputting an external power supply voltage to generate an internal voltage, and a low impedance switch for directly supplying the external power supply voltage as the internal power supply voltage. Then
A semiconductor memory circuit, wherein an output voltage of the regulator circuit or a voltage via the low impedance switch is used as an internal power supply voltage. 2. A memory device and a memory peripheral circuit;
A first power supply pad for supplying an externally supplied power supply voltage, a regulator circuit for receiving the first externally supplied power supply voltage to generate an internal voltage, and a second power supply pad different from the first externally supplied power supply voltage. And a second power supply pad for directly supplying an externally supplied power supply voltage as an internal voltage to the memory element and the memory peripheral circuit.