JPH0573626B2 - - Google Patents
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- Publication number
- JPH0573626B2 JPH0573626B2 JP608987A JP608987A JPH0573626B2 JP H0573626 B2 JPH0573626 B2 JP H0573626B2 JP 608987 A JP608987 A JP 608987A JP 608987 A JP608987 A JP 608987A JP H0573626 B2 JPH0573626 B2 JP H0573626B2
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- JP
- Japan
- Prior art keywords
- train
- point
- alarm
- warning
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000001514 detection method Methods 0.000 claims description 36
- 238000012544 monitoring process Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 6
- 238000013459 approach Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
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- Train Traffic Observation, Control, And Security (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、踏切警報制御の開始点と終止点の列
車検知による警報制御区間内の列車数の記憶によ
り踏切警報制御を行いうる列車追跡可能な点制御
式踏切制御装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is capable of tracking trains that can perform level crossing warning control by storing the number of trains in a warning control section by detecting trains at the start and end points of the railway crossing warning control. This invention relates to a point-controlled level crossing control device.
従来の点制御式踏切制御装置は、踏切制御子や
軌道リレーに代表される列車検知リレーの動作に
基づき単純なリレー論理回路で踏切制御を行うた
め踏切制御子や軌道回路の不安定動作に耐する対
策が不十分であり、これらの条件が不安定動作し
たときは、警報持続や無警報などの誤制御に陥り
やすい回路となつている。また続行列車に対する
無警報対策用としての踏切制御子が別途必要であ
り、警報開始点から踏切までの間の閉そく信号機
の位置や数の違いにより踏切制御子の設置位置や
数が違うなど、制御回路が複雑であり踏切ごとに
個別設計になつている、などの欠点があつた。
Conventional point-controlled level crossing control devices perform level crossing control using simple relay logic circuits based on the operation of train detection relays such as level crossing controllers and track relays, so they are resistant to unstable operation of level crossing controllers and track circuits. If these conditions lead to unstable operation, the circuit is prone to erroneous control such as sustained alarms or no alarms. In addition, a separate level crossing controller is required as a countermeasure against no-warning for continuing trains. The disadvantages were that the circuit was complex and each level crossing was individually designed.
〔問題点を解決するための手段〕
本発明は、上記欠点を一掃し高信頼化と標準化
を可能とするもので、列車検知入力条件の不安定
動作による誤制御を防止し、続行対策用の踏切制
御子を不要として制御回路の標準化を可能とする
点制御式踏切制御装置を提供するもので、踏切警
報制御区間の警報開始点と警報終止点における列
車検知地点を列車が通過中に発生する列車検知条
件を入力し、列車検知地点への列車の進入から進
出までを記憶し、該入力条件が不正に動作した場
合でも正常へ補正することができる列車検知回路
と、列車の走行に伴つて動作する警報開始点の列
車検知回路と警報終止点の列車検知回路の動作順
序を列車単位に記憶する回路と、該回路の記憶を
条件に列車が前記警報開始点に進入したときに加
算し、警報終止点を進出したときに減算し、警報
終止点の列車検知回路動作時にあらかじめ定めた
動作順序を満足しないときと列車が警報開始点に
進入してから一定時間経過後も警報終止点の動作
がないときは加算と減算を停止する制御手段を施
された踏切警報制御区間内の列車数の計数回路と
を備え、該計数回路の出力により警報制御区間内
に列車が存線中は踏切警報制御を行うことができ
ることを特徴とするものである。[Means for Solving the Problems] The present invention eliminates the above-mentioned drawbacks and enables high reliability and standardization. It prevents erroneous control due to unstable operation of train detection input conditions, and provides a continuation countermeasure. This provides a point-controlled level crossing control device that eliminates the need for a level crossing controller and enables standardization of control circuits.This device provides a point-controlled level crossing control device that eliminates the need for level crossing controllers and enables standardization of control circuits. A train detection circuit that inputs train detection conditions, memorizes the train from its entry to the train detection point to its exit, and can correct the input conditions to normal even if they operate incorrectly; a circuit that stores the operating order of the train detection circuit at the alarm starting point and the train detection circuit at the alarm ending point for each train; It is subtracted when the train advances from the alarm end point, and when the predetermined operation order is not satisfied when the train detection circuit at the alarm end point operates, and even after a certain period of time has passed after the train enters the alarm start point, the alarm end point operates. A counting circuit for counting the number of trains in the level crossing warning control section is equipped with a control means that stops addition and subtraction when there is no train in the warning control section. The feature is that it can be controlled.
以下本発明の実施例を図面によつて説明する。
第1図は複線の場合の線路図で、踏切警報の開始
点がAに対して終止点Bが、開始点がCに対して
終止点がDとして警報制御を行う装置の実施例が
第3図に示す回路図である。第2図は単線の場合
の線路図で、踏切警報の開始点がEに対して終止
点がG、開始点がFに対して終止点がGとして警
報制御を行う実施例が第4図に示す回路である。
Embodiments of the present invention will be described below with reference to the drawings.
Figure 1 is a track diagram for a double-track system, and shows a third embodiment of the device that performs alarm control with the starting point of the level crossing warning being A and the ending point B, and the starting point being C and the ending point being D. It is a circuit diagram shown in a figure. Figure 2 is a track diagram for a single track, and Figure 4 shows an example in which the alarm control is performed with the starting point of the level crossing alarm being E and the ending point being G, and the starting point being F and the ending point being G. This is the circuit shown.
第1図および第2図において警報開始点および
警報終止点A,B,C,D,E,F,Gに設置さ
れる例えば踏切制御子や軌道回路などの列車検知
器から出力される列車検知条件は第3図および第
4図においてTa,Tb,Tc,Td,Te,Tf,Tg
として入力される。第3図の回路ブロツク図にお
いてTIは第5図および第6図に示す如く列車検
知条件が不正に動作した場合でも補正が可能な列
車検知回路、DCは第7図および第9図に示す如
き動作をする複線用の列車追跡および制御回路、
TCは最終の制御出力回路である。また第4図に
おいてTI,TCは第3図の場合と同様であり、SC
は第8図および第10図に示す如き動作をする単
線用の列車追跡および制御回路である。 Train detection output from train detectors such as level crossing controllers and track circuits installed at alarm start points and alarm end points A, B, C, D, E, F, and G in Figures 1 and 2. The conditions are Ta, Tb, Tc, Td, Te, Tf, Tg in Figures 3 and 4.
is entered as . In the circuit block diagram of Figure 3, TI is a train detection circuit that can correct even if the train detection conditions operate incorrectly, as shown in Figures 5 and 6, and DC is a train detection circuit as shown in Figures 7 and 9. Train tracking and control circuit for double track operating;
TC is the final control output circuit. Also, in Figure 4, TI and TC are the same as in Figure 3, and SC
is a single track train tracking and control circuit which operates as shown in FIGS. 8 and 10.
複線における実施例を第3図に基づいて説明す
る。列車検知入力条件のうち、例えば上り方向を
Ta,Tb、下り方向をTc,Tdとする入力条件は
それぞれTIへ入力される。TIは具体例を第5図
に、動作を第6図に示しているが、第5図におい
てTIAは列車検知条件の記憶回路、TIBとTIDは
タイマ回路、TICは列車検知入力条件の補正回路
である。列車検知入力条件iが入力されると図6
aのタイムチヤートに示される如くTIAに記憶
されるが、同時に入力条件が安定して動作し確実
な情報として確定させるための監視時間mがTIB
によつて設定される。TICはm経過後のTIAが同
一内容を維持するとき安定した列車検知データと
して判定しdに示す如きデータをoへ出力する。
同時に続行列車が進入してくるまでの間に発生す
る不正な入力iを補正するための監視時間nが
TIDによつて設定される。このnの値は列車の速
度や閉そく区間の距離によつて算出することにな
るが、列車検知点を列車が通過後、続行列車が続
いて進入してくるまでの時間を監視すればよく、
TICはn設定中の不正な列車検知入力は補正し不
採用とする。第6aの2はn設定中に不正入力し
た例であり、該データは不採用となり出力dへは
出力されない。第3図のDCはTIからの出力を受
け、警報区間の列車追跡と警報制御を行うが、第
7図はDCの具体例であり第9図はDCの動作を示
している。第7図のSCAは警報開始点上へ列車
が在線中である状態の記憶回路、SCBは警報終
止点上へ列車が在線中である状態の記憶回路、
SCCは列車が警報開始点と終止点の間に在線中で
ある状態の記憶回路である。いま、列車が警報開
始点に進入するとsから条件が入力され、SCA
からの出力eによりSCDでは列車数を加算する。
このとき列車数が初めて1になつたときhをセツ
トし警報制御をtへ出力する。このとき既に列車
数が計数されていたときは続行列車による列車検
知を示しており、既に警報制御中の状態にある。
列車が警報開始点を進出するとSCAはeをリセ
ツトしfがSCCによつてセツトされる。列車が警
報終止点に進入するとrから条件が入力され
SCBからの出力gによりfはリセツトする。列
車が警報終止点を進出すると、SCBは出力gを
リセツトし、SCDは列車数を減算し列車数が0
となつたときhをリセツトし警報制御を解除す
る。SCDは列車走行にしたがつてe,f,gの
動作順序を監視しており、動作順序が正規でない
場合は故障と判断し、警報制御を保持することも
可能である。また、例えばeからgまでの時間を
監視することにより、警報終止点の列車検知器の
故障により列車通過にもかからず列車検知が行わ
れなつかた場合の故障判定なども可能である。第
3図においてDCは上り方向と下り方向単位に設
け、TCはそれぞれの警報制御のORにより最終
的な警報制御出力Tを提供する。 An embodiment for a double track will be described based on FIG. 3. Among the train detection input conditions, for example, the up direction
Input conditions such as Ta, Tb, and down direction as Tc, Td are input to TI, respectively. A specific example of TI is shown in Figure 5, and its operation is shown in Figure 6. In Figure 5, TIA is a storage circuit for train detection conditions, TIB and TID are timer circuits, and TIC is a correction circuit for train detection input conditions. It is. When train detection input condition i is input, Figure 6
As shown in the time chart in a, it is stored in TIA, but at the same time, the monitoring time m to ensure that the input conditions operate stably and is confirmed as reliable information is TIB.
Set by. When TIA maintains the same content after m elapses, TIC determines it as stable train detection data and outputs data as shown in d to o.
At the same time, the monitoring time n to correct the incorrect input i that occurs until the continuing train approaches is
Set by TID. The value of n is calculated based on the speed of the train and the distance of the block section, but it is sufficient to monitor the time from the time the train passes the train detection point until the next train enters.
TIC will correct any invalid train detection input during n setting and reject it. No. 6a-2 is an example in which an illegal input was made during the n setting, and the data is not adopted and is not output to the output d. The DC in Fig. 3 receives the output from the TI and performs train tracking and alarm control in the warning section. Fig. 7 shows a specific example of the DC, and Fig. 9 shows the operation of the DC. In Figure 7, SCA is a memory circuit for the state where the train is on the line above the alarm starting point, and SCB is a memory circuit for the state where the train is on the line above the alarm end point.
The SCC is a memory circuit for the state in which the train is on the line between the warning start point and the warning end point. Now, when the train enters the warning starting point, the conditions are input from s, and the SCA
The SCD adds the number of trains based on the output e from the .
At this time, when the number of trains reaches 1 for the first time, h is set and an alarm control is output to t. If the number of trains has already been counted at this time, this indicates that a train is being detected due to a continuing train, and the system is already under alarm control.
When the train advances beyond the warning starting point, the SCA resets e and f is set by the SCC. When the train approaches the warning end point, conditions are input from r.
f is reset by the output g from SCB. When the train advances past the alarm end point, the SCB resets the output g, and the SCD subtracts the number of trains until the number of trains becomes 0.
When this happens, h is reset and the alarm control is canceled. The SCD monitors the order of operations of e, f, and g as the train runs, and if the order of operations is not normal, it is possible to determine a failure and maintain alarm control. Furthermore, by monitoring the time from e to g, for example, it is possible to determine a failure in the case where a train cannot be detected even though the train has passed due to a failure of the train detector at the warning end point. In FIG. 3, DC is provided for each upstream and downstream direction, and TC provides the final alarm control output T by ORing each alarm control.
つづいて単線における実施例を第4図に基づい
て説明する。第8図は単線用のSCの具体例であ
り第10図は動作例である。警報終止点の列車検
知条件Tgは上り方向と下り方向に対して共通で
あり、例えば下り方向の警報開始点をTeとする
と上り方向の警報開始点はTfとなる。いま、下
り方向へ列車が走行した場合を例にとつて説明す
ると、列車が警報開始点へ進入するとTIより出
力される安定した列車検知データはSCのsへ入
力される。SCEの出力iによりSCJでは列車数を
加算し列車数が初めて1になつたときnをセット
し警報制御をtへ出力する。列車が警報開始点を
進出するとSCEはiをセツトし、jがSCFにより
セツトされる。列車が警報終止点に進入するとr
から列車検知条件が入力されSCGからの出力k
によりjはリセツトされる。列車が警報終止点を
進出するとSCGからのkのリセツトによりSCH
はlをセツトし、SCJは列車数を減算して結果が
0のとき警報制御を解除する。また、同時にSCJ
は列車が警報終止点から脱け側始動点へ通過し終
るのを確認するために脱け側の列車数を加算す
る。列車が脱け側始動点へ進入するとcからの条
件入力によりSCIはmをセツトしSCHはlをリセ
ツトする。列車が脱け側始動点を進出するとSCI
のmのリセツトによりSCJは脱け側列車数を減算
する。このようにSCJは列車走行にしたがつて
i,j,k,l,mの動作順序と在線状態を監視
しており、列車通過を確実に判別することが可能
である。第4図においてTCは単線用の警報制御
出力回路であり、上り方向および下り方向別に設
けるSCからの出力がどちらか一方の場合に限り
Tに出力する。 Next, an embodiment using a single wire will be described based on FIG. 4. FIG. 8 shows a specific example of a single-line SC, and FIG. 10 shows an example of its operation. The train detection condition Tg for the warning end point is common to both the up and down directions; for example, if the down direction warning start point is Te, the up direction warning start point is Tf. Now, to explain the case where a train is traveling in the down direction as an example, when the train enters the warning starting point, stable train detection data output from the TI is input to s of the SC. The SCJ adds the number of trains based on the output i of the SCE, and when the number of trains reaches 1 for the first time, sets n and outputs an alarm control to t. When the train advances beyond the warning starting point, the SCE sets i and j is set by the SCF. When the train approaches the warning end point, r
The train detection conditions are input from , and the output from SCG is k
j is reset by When the train advances beyond the warning end point, the SCH is reset by resetting k from the SCG.
sets l, SCJ subtracts the number of trains, and when the result is 0, cancels the alarm control. Also, at the same time SCJ
adds the number of trains on the escape side to confirm that the train has passed from the alarm ending point to the escape side starting point. When the train approaches the starting point on the exit side, SCI sets m and SCH resets l based on the condition input from c. SCI occurs when the train advances beyond the exit side starting point.
By resetting m, SCJ subtracts the number of trains on the deviating side. In this way, the SCJ monitors the order of operations of i, j, k, l, and m as the train travels, as well as the track status, and can reliably determine whether a train is passing. In FIG. 4, TC is an alarm control output circuit for a single line, and outputs to T only when the output from the SC provided separately for the up and down directions is either one.
本発明にかかる列車追跡可能な点制御式踏切制
御装置は、上記実施例により説明したように、不
安定動作した列車検知条件を補正することが可能
であるため安定した警報制御を提供できると共に
続行列車対策用の踏切制御子を不要とし警報開始
点と警報終止点の列車検知条件のみによる標準化
制御回路を提供できる。
As explained in the above embodiment, the point-controlled level crossing control device capable of train tracking according to the present invention is capable of correcting conditions for detecting an unstable train, and therefore can provide stable warning control and continue operation. It is possible to provide a standardized control circuit that eliminates the need for a level crossing controller for train countermeasures and uses only the train detection conditions at the alarm start point and alarm end point.
第1図は複線の線路図、第2図は単線の線路図
第3図は本発明の複線の実施例、第4図は本発明
の単線の実施例、第5図は列車検知回路の具体例
で第6図はその説明用のタイムチヤート、第7図
は複線用の列車追跡および制御回路の具体例で第
9図はその説明用のタイムチヤート、第8図は単
線用の列車追跡および制御回路で第10図はその
説明用のタイムチヤートである。
なお、A,C,E,F……警報開始点、B,
D,G……警報終止点、TI……列車検知回路、
DC……複線用列車追跡および制御回路、TC……
制御出力回路、SC……単線用列車追跡および制
御回路、TIA……記憶回路、TIB……タイマ回
路、TIC……補正回路、TID……タイマ回路、
SCA,SCB,SCC,SCE,SCF,SCG,SCH,
SCI……記憶回路、SCD……複線用制御回路、
SCJ……単線用制御回路。
Fig. 1 is a double-track track diagram, Fig. 2 is a single-track track diagram, Fig. 3 is a double-track embodiment of the present invention, Fig. 4 is a single-track embodiment of the present invention, and Fig. 5 is a specific example of the train detection circuit. As an example, Fig. 6 is a time chart for explaining the same, Fig. 7 is a specific example of a train tracking and control circuit for double track, Fig. 9 is a time chart for explaining the same, and Fig. 8 is a time chart for train tracking and control circuit for single track. FIG. 10 is a time chart for explaining the control circuit. In addition, A, C, E, F... alarm starting point, B,
D, G...Alarm end point, TI...Train detection circuit,
DC...Train tracking and control circuit for double track, TC...
Control output circuit, SC...train tracking and control circuit for single track, TIA...memory circuit, TIB...timer circuit, TIC...correction circuit, TID...timer circuit,
SCA, SCB, SCC, SCE, SCF, SCG, SCH,
SCI...memory circuit, SCD...double track control circuit,
SCJ...Single wire control circuit.
Claims (1)
る点制御式踏切制御装置であつて、 列車検知回路TIは、補正手段を有し、踏切警
報制御区間A〜Bの警報開始点における列車検知
地点Aを列車が通過中に発生する列車検知条件信
号Taと、警報終止点における列車検知地点Bを
列車が通過中に発生する列車検知条件信号Tbと
を入力して、それぞれの列車検知地点A,Bへの
列車の進入から進出までの監視時間mをそれぞれ
に記憶し、不安定な検知状態により列車がいるに
もかかわらず一時的にOFFとなり、またONに戻
るというように検知出力が不正に動作した場合で
も、監視時間mの間であれば不正なOFF状態を
連続的なON状態に補正するものであり、 計数回路SCDは、動作順序の記憶手段e,f,
gと制御手段とを有し、動作順序の記憶手段e,
f,gが警報開始点上へ列車がいる状態の記憶e
と警報終止点上へ列車がいる状態の記憶gと警報
開始点と警報終止点の間に列車がいる状態の記憶
fとを、警報開始点と警報終止点を列車が通過す
る際の列車検知条件Ta,Tbによつて、開始点を
通過し続いて終止点を通過するという一定の順序
e→f→gに対応して記憶し、制御手段が、警報
開始点Aに列車が進入したときに加算し、警報終
止点Bを列車が通過したときに減算する該計数回
路の出力tにより警報制御区間A〜Bに列車が在
線中は踏切警報制御Tを行い、警報終止点Bの列
車検知回路TI動作時にあらかじめ定めた動作順
序e→f→gを満足しないときと列車が警報開始
点Aに進入してから一定時間経過後も警報終止点
の動作gがないときは加算と減算を停止して踏切
警報制御を停止するものである 点制御式踏切制御装置。[Scope of Claims] 1. A point control type level crossing control device having a train detection circuit TI and a counting circuit SCD, wherein the train detection circuit TI has a correction means, and the train detection circuit TI has a correction means, and the alarm of the level crossing alarm control section A to B is Input the train detection condition signal Ta that is generated while the train is passing through the train detection point A at the start point, and the train detection condition signal Tb that is generated while the train is passing through the train detection point B at the alarm end point, and The monitoring time (m) from when a train enters to train detection points A and B is memorized respectively, and the system temporarily turns OFF even though there is a train due to an unstable detection condition, and then returns to ON again. Even if the detection output operates incorrectly during the monitoring period m, the incorrect OFF state is corrected to a continuous ON state, and the counting circuit SCD has operation order storage means e, f,
g and control means, and operation order storage means e,
f, g are memory e of the state where the train is above the alarm starting point
, a memory g of a state in which a train is above the alarm end point, and a memory f of a state in which a train is between the alarm start point and the alarm end point, and a train detection when the train passes the alarm start point and the alarm end point. According to the conditions Ta and Tb, when the train enters the warning starting point A, the train is stored in correspondence with a certain sequence e→f→g of passing through the starting point and then passing through the ending point. When the train passes the warning end point B, the output t of the counting circuit is added to the warning end point B, and the output t of the counting circuit is used to perform the level crossing warning control T while the train is in the warning control section A to B, and detect the train at the warning end point B. Addition and subtraction are stopped when the predetermined operation order e → f → g is not satisfied when circuit TI is activated, or when there is no operation g at the alarm end point even after a certain period of time has passed since the train entered the alarm start point A. This is a point-controlled level crossing control device that stops the level crossing warning control.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP608987A JPS63176769A (en) | 1987-01-16 | 1987-01-16 | Train traceable point control type railroad crossing controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP608987A JPS63176769A (en) | 1987-01-16 | 1987-01-16 | Train traceable point control type railroad crossing controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63176769A JPS63176769A (en) | 1988-07-21 |
JPH0573626B2 true JPH0573626B2 (en) | 1993-10-14 |
Family
ID=11628804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP608987A Granted JPS63176769A (en) | 1987-01-16 | 1987-01-16 | Train traceable point control type railroad crossing controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63176769A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0752777Y2 (en) * | 1989-07-11 | 1995-12-06 | 日本信号株式会社 | Railroad crossing control device |
JPH04201677A (en) * | 1990-11-30 | 1992-07-22 | Kyushu Riyokaku Tetsudo Kk | Device for detecting train occupied line |
JP4976622B2 (en) * | 2001-06-22 | 2012-07-18 | 東日本旅客鉄道株式会社 | Crossing control device and crossing control network |
JP6501731B2 (en) * | 2016-07-14 | 2019-04-17 | 東邦電機工業株式会社 | Train direction detection device |
-
1987
- 1987-01-16 JP JP608987A patent/JPS63176769A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS63176769A (en) | 1988-07-21 |
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EXPY | Cancellation because of completion of term |