JPH0573364A - Most priority alarm output circuit - Google Patents

Abstract

PURPOSE:To output the most priority alarm even if many number of alarms are issued in an alarm output processing time by writing a code to show a range of the most priority alarm output processing and a priority level showing code for each alarm. CONSTITUTION:A code showing hte most priority alarm output processing range and a priority level showing code are written in a ROM 1 with each alarm. In an alarm input state, the processing range showing code outputted to a processing range control part 2, and the alarm name and the priority level are outputted to a comparator 3. The comparator 3 compares the received priority level with the priority level received from a priority processing register 4. When the former level is higher than the latter one, the alarm name and the priority level are sent to the register 4 kept in the selected processing range. When the write is complete with these alarm name and priority level, the register 4 outputs the most priority alarm written for each register.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a plurality of processing ranges,
The present invention relates to an improvement of a top priority alarm output circuit of a digital transmission device that outputs a top priority alarm among a plurality of alarms having a priority to be input.

The point of outputting the highest priority alarm among a plurality of alarms having a priority order to be input for each of a plurality of processing ranges in a digital transmission device will be described with reference to FIG.

FIG. 3 is a diagram showing an example of alarms having priorities for respective processing ranges. FIG. 3 shows that when all or part of the input signal disconnection alarm RIN, out-of-sync alarm REC, and error occurrence alarm is input for each transmission path interface panel 21, 22, 23, ... The line interface boards 21, 22, and 23 are transmission path interface boards 21, 22, and 2 which are processing ranges.
The alarm with the highest priority is output every 3 ...

When the input signal disconnection alarm RIN is input, the input signal is disconnected.
C. It is meaningless to output the error alarm alarm error, and when the loss-of-synchronization alarm REC is input, it is meaningless to output the error-occurrence alarm error, so the priority order is When RIN>REC> error occurs, RIN, REC, error, RIN, REC, or when RIN and error are input at the same time, only the highest priority RIN is output, and when REC and error are input at the same time, priority is output. It outputs only the REC having a high value.

Recently, digital transmission equipment has taken a step toward higher functionality, and has collected a large number of alarms for a large number of processing ranges.
Among the alarms input for each processing range, the highest priority alarm is output, but the highest priority alarm output circuit capable of processing a large number of alarms without being limited by the capacity of the ROM. It is desired to be provided.

[0006]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional highest priority alarm output circuit. Conventionally, the ROM 10 shown in FIG. 2 is used as the highest priority alarm output circuit that collects a large number of alarms for a large number of processing ranges and outputs the highest priority alarm among the alarms input for each processing range.
The input and output terminals of all alarms to be collected are provided for 10 inputs and outputs, and when outputting the alarm with the highest priority among the alarms input for each processing range, the alarm input for each processing range is set. Among the output terminals of the corresponding alarm, 1 is output from the output terminal of the alarm having the highest priority, and 0 is output from the output terminals of the other alarms.

[0007]

However, the ROM has a highest priority alarm output circuit that collects a large number of alarms for a large number of processing ranges and outputs the highest priority alarm among the alarms input for each processing range. To configure,
If the number of all alarms is N, a ROM of 2 ^N bits is required, but the number of bits of the ROM is limited such as 4 Mbits, and the number N of alarms input to the ROM 10 is limited by the capacity of the ROM. There is a problem.

According to the present invention, even if the number of alarms to be intensively processed is large, the highest priority alarm that outputs the highest priority alarm among the alarms input for each processing range is not limited by the capacity of the ROM. The purpose is to provide an output circuit.

[0009]

FIG. 1 is a block diagram of a top priority alarm output circuit according to an embodiment of the present invention. As shown in FIG. 1, a code indicating a processing range for performing the highest priority alarm output processing and a code indicating a priority level are written for each alarm, and when the alarm is input, a code indicating the corresponding processing range is written. ROM that outputs to 2 and outputs the name and priority level of the corresponding alarm to the comparator 3.
When 1 and a code indicating the processing range are input, the comparator 3
In order to write the output of the above, the register corresponding to the code indicating the processing range in the priority processing register 4 is selected, and the processing level control unit 2 that outputs the priority level written previously to the comparator 3 is selected. When the alarm name and priority level are input, the alarm level and priority level are compared with the priority level from the priority processing register 4, and if the priority is high, the alarm name and priority level are registered in the register of the relevant processing range of the priority processing register 4. Is sent to each of the registers of the processing range, and the name and priority level of the sent alarm are written. When a series of alarms have been input to the ROM 1, the registers of the processing range are written. The priority processing register 4 for outputting the highest priority alarm is configured.

[0010]

According to the present invention, the code indicating the processing range for performing the highest priority alarm output processing and the code indicating the priority level are written in the ROM 1 for each alarm, and when the alarm is input, the corresponding processing range is stored. The indicated code is output to the processing range control unit 2, and the name and priority level of the corresponding alarm are output to the comparator 3.

When the code indicating the processing range is input, the processing range control unit 2 selects the register corresponding to the code indicating the processing range in the priority processing register 4 in order to write the output of the comparator 3. The priority level previously written is output to the comparator 3.

When the alarm name and the priority level are input, the comparator 3 compares them with the priority level from the priority processing register 4, and if the priority is high, registers of the corresponding processing range selected by the priority processing register 4 are compared. Send the alarm name and priority level to.

Then, the priority processing register 4 writes the name and priority level of the sent alarm for each register of the corresponding processing range. When the above operation is continued until a series of alarms have been input, the highest priority alarm among the alarms to be input for each processing range is written in the register for each processing range of the priority processing register 4. The processing register 4 outputs this.

That is, since the code indicating the processing range for performing the highest priority alarm output processing and the code indicating the priority level may be written in the ROM 1 for each alarm, R
If the code indicating the processing range is, for example, 4 bits and the code indicating the priority level is 4 bits, the amount of data to be written to the OM1 is the number of alarms × 8 bits, and the number of alarms is large. Both ROM1
It is possible to obtain the highest priority alarm output circuit that outputs the highest priority alarm among the alarms input for each processing range without being limited to the capacity of the above.

[0015]

1 is a block diagram of a highest priority alarm output circuit according to an embodiment of the present invention. FIG. 1A shows the highest priority alarm output circuit, and FIG. 1B shows an example of alarm names A to F written in a ROM 1. The code of the processing range and the priority level code are shown.

For example, the alarm names are A, B, C, D,
E, F, the code of the processing range of A, E, F is 1, B,
The code of the processing range of C and D is 2, the alarm of the highest priority 3 in the processing range 1 is A, the alarm of the second highest priority 2 is E, the highest priority Low priority 1
Is F, the alarm of priority 3 is D, the alarm of priority 2 is C, and the alarm of priority 1 is B in the processing range 2. As shown in FIG. ,
The processing range codes and priority level codes for alarms A, B, C, D, E, and F are assigned addresses 001, 002.
Write in the rows 003, 004, 005, 006.

Therefore, for example, when alarms A, B, C, and E simultaneously occur and the alarms A, B, C, and E are sequentially input to the ROM 1, the ROM 1 initially sets the code 1 of the processing range of the alarm A to the processing range. The alarm name A and the priority level 3 are sent to the control unit 2 and input to the comparator 3.

In the processing range control section 2, the register in the priority processing register 4 corresponding to the code 1 of the processing range sent is selected for writing the output of the comparator 3, and the priority written therein is selected. Level (do not write at first)
Is sent to the comparator 3.

The comparator 3 compares the input priority level 3 with the sent priority level (initially 0), and since the priority level is higher, the alarm name A is registered in the selected priority processing register 4. And write priority level 3.

Next, when the alarm B is input to the ROM 1, the processing range code 2 is sent to the processing range control unit 2, and the alarm name B and the priority level 1 are input to the comparator 3.
In the processing range control unit 2, the register in the priority processing register 4 corresponding to the transmitted processing range code 1 is selected in order to write the output of the comparator 3, and the priority level written here (first Is not written) to the comparator 3.

In the comparator 3, the inputted priority level 1 is compared with the sent priority level (0 at the beginning), and since the priority level is high, the alarm name B is registered in the register in the selected priority processing register 4. And write priority level 1.

Next, when the alarm C is input to the ROM 1, the same operation as described above is performed, and since the alarm C has a higher priority level than the alarm B in the processing range 2, the processing range 2 in the priority processing register 4 The alarm name C and priority level 2 are written in the register.

Next, when the alarm E is input to the ROM 1, the same operation as described above is performed, and in the processing range 1, since the alarm A has a higher priority level than the alarm E, the processing range 1 in the priority processing register 4 The name A of the alarm and the priority level 3 are written in the register.

Since a series of alarm processing is completed,
The priority processing register 4 outputs the alarm name A and the priority level 3 written in the processing range 1 register, and the alarm name C and the priority level 2 written in the processing range 2 register.

In this case, since the code of the processing range represented by 2 bits and the code of the priority level represented by 3 bits may be written in the ROM 1 for each alarm, the data written in the ROM 1 is the alarm. Score x 5
Become a bit.

That is, the data to be written in the ROM 1 may be the sum of the code indicating the processing range and the code indicating the priority level for the number of alarms, which is much smaller than the conventional one, and is processed intensively. The number of alarms is not limited to the capacity of the ROM, and it becomes possible to output the alarm with the highest priority among the alarms input for each processing range.

[0027]

As described in detail above, according to the present invention, the number of alarms to be processed in a concentrated manner is not limited by the capacity of the ROM, and the alarm having the highest priority among the alarms input for each processing range. There is an effect that a high-priority alarm output circuit capable of outputting a high alarm is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a highest priority alarm output circuit according to an embodiment of the present invention,

FIG. 2 is a block diagram of a conventional prioritized alarm output circuit,

FIG. 3 is a diagram showing an example of alarms having priorities for respective processing ranges.

[Explanation of symbols]

 Reference numerals 1 and 10 represent a ROM, 2 represents a processing range control unit, 3 represents a comparator, 4 represents a priority processing register, and 21 to 23 represent transmission line interface boards.

Claims (1)

[Claims] 1. A code indicating a processing range for performing the highest priority alarm output processing and a code indicating a priority level are written for each alarm, and when the alarm is input, a code indicating the corresponding processing range is added to the processing range control unit ( Output to 2),
When the ROM (1) that outputs the name and priority level of the corresponding alarm to the comparator (3) and the code indicating the processing range are input, in order to write the output of the comparator (3), the priority processing register ( 4) Select the register corresponding to the code indicating the processing range in 4) and output the previously written priority level to the comparator (3), the processing range control unit (2), and the alarm name and priority. When the level is entered,
Compare with the priority level from the priority processing register (4),
If the priority is high, the comparator (3) for sending the alarm name and the priority level to the register of the applicable processing range selected by the priority processing register (4), and the alarm sent for each register of the applicable processing range Name and priority level, and when a series of alarms have been input to the ROM (1), the priority processing register (4) for outputting the highest priority alarm written for each register in the processing range is displayed. A high-priority alarm output circuit having.