JPH0573352B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a heterogeneous semiconductor junction.

[Conventional technology]

Conventional semiconductor devices with heterojunctions (different semiconductor junctions), such as hot electron transistors, use a semiconductor with a wide forbidden band width for the emitter and a semiconductor with a narrow forbidden band width for the base, and the carrier injected from the emitter into the base becomes the collector. We take advantage of gatherings. Since the carrier's travel time during the base is short, in principle high-speed operation can be expected.

Further, although the current-voltage characteristic between the emitter and the base of the hot electron transistor exhibits an exponential characteristic, the rise characteristic is not necessarily sufficient because the carrier is not degenerated.

Furthermore, if the impurity concentration of the semiconductor is increased, it becomes a tunnel junction, so it is not possible to sufficiently reduce the parasitic resistance of a semiconductor with a particularly wide bandgap, and it is not possible to achieve high-speed operation as expected in principle. I can't.

[Problem that the invention seeks to solve]

In the above-mentioned conventional semiconductor devices having a heterojunction, the impurity concentration cannot be increased except for special devices that use tunnel junctions, so the parasitic resistance of the semiconductor with a wide forbidden band width cannot be reduced, so it is not possible to sufficiently reduce the parasitic resistance of the semiconductor. The disadvantage is that it is not possible to perform high-speed operations. Furthermore, since the carrier is not degenerated, there is also the drawback that the current does not rise sharply enough with respect to the voltage.

[Means for solving problems]

The first semiconductor device of the present application includes a strongly degenerate N (or P) type first semiconductor, and a degenerate semiconductor device in which the first semiconductor and the conduction band (or valence band) form a continuous junction. a barrier layer of a predetermined thickness made of a second semiconductor with a predetermined height, and a third semiconductor having a smaller forbidden band width than the second semiconductor, which contacts the barrier layer with a potential barrier of a predetermined height; It is said that it has.

The semiconductor device of the second invention of the present application has an emitter region made of a strongly degenerate N (or P) type first semiconductor, and a junction where the first semiconductor and the conduction band (or valence band) are continuous. a first barrier layer of a predetermined thickness made of a non-degenerate second semiconductor to be formed, and a first barrier layer that is in contact with the first barrier layer with a first potential barrier of a predetermined height, a base region made of a third semiconductor with a small forbidden band width; and a non-degenerate fourth semiconductor that contacts the base region with a second potential partition wall smaller in height than the first potential barrier. a collector region comprising a second barrier layer and a fifth N (or P) type semiconductor in which the second barrier layer and the conduction band (or valence band) form a continuous junction; It has a configuration that includes a transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a side view of a diode chip showing the main parts of an embodiment of the first invention of the present application.

This example was doped with a donor of 10 ²⁰ cm ^-3
A strongly degenerate N-type first semiconductor made of an N ⁺ type Al _0.7 Ga _0.3 As substrate 1-1, with a thickness of approximately 5 to 100 mL to form a continuous junction with the first semiconductor 1-1 in conduction bands.
A barrier layer consisting of a 200 nm non-doped Al _0.7 Ga _0.3 As layer 1-2 containing a donor of 10 ¹⁵ cm- ³ or less, and a barrier layer that is in contact with this barrier layer with a potential barrier of a predetermined height and is prohibited from Al _0.7 Ga _0.3 As. Small band width 10 ²⁰
N ⁺ type GaAs type 1-3 doped with cm- ³ donor
It is a diode having a heterogeneous semiconductor junction consisting of an anode and a cathode metal electrode (not shown) provided on an N ⁺ type Al _0.7 Ga _0.3 As substrate 1-1 and an N-type GaAs layer 1-3, respectively. do.

To obtain such a structure, for example, N-type
Al _0.7 Ga _0.3 As Non-doped Al _0.7 Ga _0.3 on the main surface of the substrate
The As layer and the N ⁺ type GaAs layer may be sequentially deposited by molecular beam epitaxial method.

Next, the characteristics of this embodiment will be explained.

FIGS. 2a and 2b are energy band diagrams of the diode in a thermal equilibrium state and in a bias voltage application state, respectively.

In Figure 2a, N ⁺ for Fermi levels 1-4
The bottom 1-5W of the conduction band of the type Al _0.7 Ga _0.3 As substrate is located below and is strongly degenerated. Further, the bottom 1-5N of the conduction band of the N ⁺ type GaAs layer is also below the Fermi level 1-4 and is strongly degenerated. At this time, the conduction band bottoms 1-5 of the barrier layer act as potential barriers for the two semiconductor electrons. Fermi level 1
The height of the barrier V _T from −4 is the threshold voltage of the diode.

Next, as shown in Figure 2b, N ⁺ type Al _0.7 Ga _0.3
When As substrate 1-1 is positively biased, N ⁺ type Al _0.7
Ga _0.3 Fermi level 1-7W on As side is N ⁺ type GaAs
The bias voltage V is higher than the Fermi level 1-7N on the side.

Now, at this time, the Fermi level 1-7W of N ⁺ type Al _0.7 Ga _0.3 As is the bottom 1 of the conduction band of Al _0.7 Ga _0.3 As at the interface.
-8 above by V−V _T , N ⁺ type Al _0.7 Ga _0.3
Electrons in As are released into N ⁺ type GaAs. This emission current density J is given by the following equation.

J=mq/4π ² 〓3[q(V-V _T )] ² , V≧V _T (l) Here, m is the effective mass of the electron, q is the amount of charge of the electron,
〓 is a blank constant. Effective mass of electrons in Al _0.7 Ga _0.3 As m=0.2×9.1×10 ^-29 , q=1.8×
10 ^-29 g, = 1.05 x 10 ^-27 erg-sec, q = 1.6 x
10 ¹⁹ By substituting C, the above equation becomes the following equation.

=1.5×10 ⁹ (V-V _T ) ² A/cm ² (2) J is a function that rises rapidly when V≧V _T , for example, J
= 10 ³ ~ To obtain ^{10 5} A/cm ² , V-V _T = 0.8 mV ~
8mV is fine.

The N ⁺ type GaAs layer and the N ⁺ type Al _0.7 Ga _0.3 As substrate are highly doped, so they have low resistance, and the Al _0.7
Since the Ga _0.3 As layer is thin, with a thickness of 5 to 200 nm, the diode of this example has low parasitic resistance and rises sharply with respect to voltage, allowing high-speed operation and making it possible to construct digital circuits with a logic amplitude of 10 mV or less. .

Note that the thickness of the barrier layer may be set to such a thickness that tunnel current can be ignored. When a junction is formed with the strongly degenerate first semiconductor, the effective thickness of the barrier layer is the part where the bottom of the conductor is above the Fermi levels 1-4, as shown in Figure 2a. , the geometrical thickness may be appropriately determined in consideration of the type of semiconductor and the impurity concentration.

Furthermore, although AlGaAs having the same composition ratio has been used as an example of the first and second semiconductors, the first and second semiconductors have the same composition ratio.
As a semiconductor, it is sufficient that the band on the carrier side of a strongly degenerate semiconductor forms a junction continuously without producing spikes or notches.

In this embodiment, a junction between N ⁺ -Al _1-X GaxAs and N ⁺ -GaAs has been described, but this may also be a P/P junction. It goes without saying that other types of semiconductor junctions may also be used.

FIG. 3 is a side view of a transistor chip showing the main parts of an embodiment of the second invention of the present application.

This example has an emitter region consisting of a strongly degenerate N ⁺ type Al _0.3 Ga _0.7 As layer 2-3 doped with a donor of 10 ²⁰ cm ^-3 , and an N ⁺ type Al _0.3 Ga _0.7 As layer 2-3. A first barrier layer with a thickness of 5 to 20 nm consisting of an Al _0.3 Ga _0.7 As layer 2-4 containing no impurities or containing a low concentration of N-type impurities forming a continuous junction between conduction bands; Al _0.3 Ga _0.7 As layer 2-4 is in contact with the first barrier layer 2-4 with a first potential barrier having a predetermined height.
Contains a donor with a smaller forbidden band width of 10 ¹⁰ cm ^-3
A base region with a thickness of 100 nm consisting of an N ⁺ type GaAs layer 2-5, a second potential barrier having a height smaller than the first potential barrier, and an impurity-free or low concentration N layer in contact with the base region. a second barrier layer with a thickness of 5 to 20 nm consisting of an Al _0.2 Ga _0.8 As layer 2-2 containing type impurities (10 ¹⁶ cm ^-3 or less);
The barrier layer and the conduction band form a continuous junction.
10 Doped with ²⁰ cm ^-3 donor (Si) and strongly degenerate
This transistor has a collector region made of an N ⁺ type Al _0.2 Ga _0.8 As layer 2-2. Note that in order to obtain the structure of this example, on an N ⁺ type Al _0.2 Ga _0.8 As substrate, an Al _0.2 Ga _0.8 As layer, an N ⁺ type GaAs layer, an N ⁺ type
It is sufficient to epitaxially grow Al _0.3 Ga _0.7 As layers in sequence.

Next, the characteristics of this embodiment will be explained.

FIGS. 4a and 4b are energy band diagrams of the transistor according to the embodiment in a thermal equilibrium state and in a state where a positive bias voltage V is applied to the emitter region and a negative bias is applied to the collector region with respect to the base region.

As shown in Figure 4a, for the Fermi level 2-6, the bottom 2-1 of the conduction band 2-1, 2-5, 2-3
7C, 2-7B, and 2-7E are below, and these semiconductors are strongly degenerate.

Next, when a bias is applied as shown in FIG. 4b, electrons are emitted from the emitter region to the base region, similar to the description of the first embodiment of the invention. These emitted electrons are accelerated by the potential difference of V _TE -V _TC , and since the base width is sufficiently thin as 100 nm, they pass through and reach the collector region from the second barrier layer. That is, it operates as a transistor. The formula for the injection current is obtained by substituting V _TE for V _T in formula (l), and is a sharply rising function of the emitter-base bias voltage V.

The thickness of the first and second barrier layers, the relationship between the forbidden band width between the emitter region and the first barrier layer, and the relationship between the forbidden band between the collector region and the second barrier layer are as explained in the first invention. Since it is the same as that, I will not explain it in detail again.

This second invention improves the voltage-current characteristics and parasitic resistance of the conventional hot electron transistor using a heterojunction, enables high-speed operation, and constitutes a digital circuit with a logic amplitude of 10 mV or less.

Further, in the embodiment, the collector region is also strongly degenerated, but this is not necessarily necessary. The fact that the collector region is strongly degenerated means that
This is because it is not a necessary condition to obtain sharp rise characteristics.

It is obvious that the first and second inventions can be applied not only to ordinary semiconductors but also to those using superlattices, without needing to explain them in detail again.

〔Effect of the invention〕

In the semiconductor device of the present invention, by interposing a thin barrier layer in a strongly degenerate semiconductor heterojunction, a semiconductor device with sharp current-voltage characteristics can be obtained.
As a result, it is possible to realize a circuit that can operate at high speed and has a small logic amplitude (approximately 10 mV).

[Brief explanation of the drawing]

Figure 1 is a side view of a diode chip showing the main parts of an embodiment of the first invention of the present application, Figures 2a and b
3 is an energy band diagram of the embodiment of the first invention in a thermal equilibrium state and a bias voltage application state, respectively; FIG. 3 is a side view of a transistor chip showing the main part of an embodiment of the second invention of the present application; and FIG. Figures a and b are energy band diagrams of the embodiment of the second invention in a thermal equilibrium state and a bias applied state, respectively. 1-2...N ⁺ type GaAs layer, 1-2...Al _0.7
Ga _0.3 As layer, 1-3...N ⁺ type GaAS layer, 1-4...
...Felmi level, 1-5...Bottom of conductor in barrier layer, 1-5N, 1-7N...Felmi level on N-type GaAs side, 1-5W, 1-7W...N-type Al _0.7
Ga _0.3 Fermi level on As side, 1-6...N ⁺ type
Bottom of conduction band of GaAs layer, 1-8...Al _0.7 Ga _0.3 As
Bottom of conduction band of layer, 2-1...N ⁺ type Al _0.2 Ga _0.8 As
Layer, 2-2...Al _0.2 Ga _0.8 As layer, 2-3...N ⁺ type
Al _0.3 Ga _0.7 As layer, 2-4...Al _0.3 Ga _0.7 As layer, 2
-5...N ⁺ type OaAs layer, 2-6...Fermi level, 27-B...Bottom of conduction band of N ⁺ type GaAs layer 2-5, 27-C...N ⁺ type Al _0.2 Ga _0.8 Bottom of conductor of As layer 2-1, 27-E...N ⁺ type Al _0.3 Ga _0.7 As layer 2-
The bottom of the conduction band of 3.

Claims (1)

[Claims] 1. A strongly degenerate N (or P) type first semiconductor,
a barrier layer of a predetermined thickness made of a non-degenerate second semiconductor in which the first semiconductor and the conduction band (or valence band) form a continuous junction; and a bodential barrier of a predetermined height with respect to the barrier layer. 1. A semiconductor device comprising a dissimilar semiconductor junction comprising a third semiconductor that is in contact with each other and has a smaller forbidden band width than the second semiconductor. 2. An emitter region made of a strongly degenerate N (or P) type first semiconductor, and a non-degenerate second emitter region in which the first semiconductor and the conduction band (or valence band) form a continuous junction. a first barrier layer made of a semiconductor and having a predetermined thickness; and a third semiconductor that is in contact with the first barrier layer with a first potential barrier of a predetermined height and has a smaller forbidden band width than the second semiconductor. a second barrier layer made of a non-degenerate fourth semiconductor contacting the base region with a second potential barrier smaller in height than the first potential barrier; 2
A semiconductor comprising a transistor comprising a barrier layer and a collector region made of an N (or P) type fifth semiconductor in which conduction bands (or valence bands) form a continuous junction. Device.