JPH0572101B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a bipolar transistor using a heterojunction for the emitter-base junction. [Technical background of the invention and its problems] Conventional bipolar transistors have an emitter,
It has an npn or pnp structure using the same semiconductor material for each layer of the base and collector. in this case,
Both the emitter junction and the collector junction are homozygous. Recently, bipolar transistors in which one or both of the emitter junction and the collector junction are heterojunctions have attracted attention and are becoming the subject of research and development. One advantage of a heterojunction bipolar transistor is that emitter injection efficiency can be increased by forming the emitter layer from a semiconductor material with a wider bandgap than the base layer. Due to the difference in band gap between the emitter layer and the base layer,
This is because, while carrier injection from the emitter to the base easily occurs when the emitter junction is forward biased, carrier injection from the base to the emitter is suppressed. Therefore, it is possible to obtain a higher current gain than a normal homojunction bipolar transistor. The basic concept of such a heterojunction bipolar transistor has been known for a long time, and several examples have been published recently. The conventional basic structure when a heterojunction is used as the emitter junction is shown in FIG. The figure shows GaAs−
In this example, an n ⁺ type GaAs substrate 1 is used, an n type GaAs collector layer 2 is placed on top of the n + type GaAs substrate 1, and a p type
GaAs base layer 3, n-type Ga _1-x Al _x As emitter layer 4
It has a structure in which layers are sequentially laminated. 5 is a collector electrode, 6 is a base electrode, and 7 is an emitter electrode. The emitter layer 4 includes a first emitter layer 4 ₁ with a high impurity concentration (n ⁺ ) on the emitter electrode 7 side,
The base layer 3 side is constituted by a second emitter layer 4 ₂ having a lower impurity concentration (n ^- ) than this. Many of the previously announced products are based on the second emitter layer 4 ₂
What they have in common is that they have sufficient thickness.
The reason why the emitter layer has a two-layer structure of a high impurity concentration layer and a low impurity concentration layer and the thickness of the second emitter layer with a low impurity concentration is made sufficiently large is to reduce the emitter junction capacitance C _JE and increase the switching speed. (For example, H. Kroemer, “Heterostructure, Bipolar
“Transistors and Iterated Circuits”, Proc.
IEEE, Vol.70, No.1, pp.13−25,
January 1982). In fact, in a one-sided stepped junction where the impurity concentration differs significantly across the junction surface, if the thickness of the low impurity concentration layer is sufficiently large, the junction capacitance C _JE can be expressed as C _JE ∝ using the impurity concentration N _E of the low impurity concentration layer. As is well known, it is expressed as N _E ^1/2 . To clarify the following discussion, let us clarify the concept of transistor switching speed. In general, the switching operation of a transistor includes turn-on and turn-off, and the propagation delay time t _pd , which is the average of the turn-on time t _po and the turn-off time t _pff , is used as the standard for switching speed. The turn-on time t _po is the time for the output current to rise from 0% to 50%, and the turn-off time t _pff is the time when the output current rises to 100%.
This is the time it takes to fall from 50% to 50%. The above relationship is shown in FIG. The present inventors have recently investigated in detail the relationship between the thickness of each layer, impurity concentration, and switching speed using a numerical analysis model for the heterojunction bipolar transistor shown in Fig. Theory of motion” Showa
1955 Kindai Kagakusha, M.Kurata, “Numerical
Analysis for Semiconductor Devices”, 1982,
Lexington Books DCHeath and Company.
etc.) As a result, a conclusion contrary to the conventional theory was obtained. In other words, according to the numerical analysis model, the switching speed of a conventional transistor with a thick second emitter layer with a low impurity concentration (hereinafter referred to as type A) is lower than the switching speed of a transistor without such a second emitter layer and with a thick second emitter layer. It is significantly inferior to that of a transistor (hereinafter referred to as type B) consisting of only a single layer of high impurity concentration. The analysis results are shown in Table 1.

[Purpose of the invention]

The present invention has been made based on the above considerations, and an object of the present invention is to provide a heterojunction bipolar transistor that provides optimal design criteria regarding switching speed and breakdown voltage. [Effects of the Invention] In the transistor according to the present invention, the emitter layer is made of a semiconductor material with a wider bandgap than the base layer, and the emitter layer is composed of a first emitter layer with a high impurity concentration and a second emitter layer with a lower impurity concentration. Basically, the base layer is made of a layer with a higher impurity concentration than the second emitter layer. In this respect, the transistor according to the present invention belongs to the above-mentioned type A. In this basic structure, the present invention improves the impurity concentration of the second emitter layer.
The relationship between N _E and its thickness w is expressed as N _E w ² ≦ as a condition for making the switching speed sufficiently high within the range where the maximum electric field in the second emitter layer in the state of zero applied voltage does not exceed the allowable maximum electric field. 2ε _s ε ₀ /qV _bi ...(1) is set to be satisfied. In equation (1), q is the absolute value of electron charge (=1.6×10 ^-19 clones), ε ₀ is the dielectric constant of vacuum (=8.86×10 ^-14 farads/cm), and ε _s is the ratio of the second emitter layer. dielectric constant,
V _bi is the built-in potential of the heterojunction formed by the second emitter layer and the base layer. The reason for giving such a design standard will be explained next. When the voltage applied to the emitter-base heterojunction is zero, the internal potential difference generated across the junction is V _bi . The electric field distribution generated at the heterojunction due to this potential difference is as shown in FIG. Figure 4a
When the thickness w of the second emitter layer is sufficiently large, in the figure b, when the thickness w of the second emitter layer is equal to the thickness w _dep of the depletion layer that extends due to the internal potential difference, in the figure c, w is smaller than w _dep . This is the case. Now, the impurity concentration N _{E of the second emitter layer is the impurity concentration N E} of the base layer.
Assuming that it is much lower than N _B , the following formulas hold true for the cases a and b in FIG. 4, respectively, according to well-known theory. E ⁽⁰⁾ _nax =qN _E /ε _s ε ₀ w _dep ...(2) 1/2E ⁽⁰⁾ _nax w _dep =V _bi ...(3) Eliminating E ⁽⁰⁾ _nax from both equations, N _E w ² _dep = 2ε _s ε ₀ /qV _bi ...(4). Similarly, in the case of FIG. 4c, the following formula holds true. E _nax −E _nio = q/ε _s ε ₀ N _E w …(5) E _nio w+1/2(E _nax −E _nio )w=V _bi …(6) Calculating E _nax from both equations, , E _nax =qN _E /2ε _s ε ₀ w+V _bi /w ...(7). However, in the above, the maximum value of the electric field in the second emitter layer is _Enax , and the minimum value of the electric field is _Enio . Based on the above relationships, the impurity concentration N _E and thickness w of the second emitter layer are set so as to satisfy the relationship in equation (1) within the range where the maximum electric field shown in equation (7) does not exceed the allowable maximum electric field. As a result, a sufficiently high switching speed is achieved while ensuring voltage resistance. Note that the built-in potential V _bi of the heterojunction between the second emitter layer and the base layer is expressed by the following equation (8). V _bi = kT/qln [N _E N _B /n _i (T) ² ] +x _B −x _E /q...(8) where k is Boltzmann's constant, T is absolute temperature,
N _B is the impurity concentration of the base layer, n _i (T) is the intrinsic electron density of the base layer, x _B is the electron affinity of the base layer, and x _E is the electron affinity of the second emitter layer. In equation (8), the first term on the right side is the same as in a normal homozygote, and the second term is a term unique to a heterozygote. Specifically, N-type Ga _0.7 is used as the second emitter layer.
The table below shows numerical examples of V _bi for typical combinations of impurity concentrations when Al _0.3 As and p-type GaAs are selected as the base layer.

〔Effect of the invention〕

According to the present invention, by setting N _E w ² to the minimum necessary value, it is possible to realize a heterojunction bipolar transistor that is capable of high-speed switching operation while ensuring an emitter-base breakdown voltage. [Embodiments of the Invention] Examples of the present invention will be described below. GaAlAs−
FIG. 5 shows the structure of an embodiment using GaAs. To explain this according to the manufacturing process, first, an n ⁺ type GaAs substrate 11 with a high impurity concentration is used as a starting substrate, and an n type GaAs collector layer 12 with a low impurity concentration doped with Si as an impurity is epitaxially formed thereon. Make it grow. This is the case when the collector-base junction is a homojunction, and when a heterojunction is introduced also in this junction, n-type Ga _1-x Al _x
The As layer may be epitaxially grown. In either case, epitaxial growth is performed using MBE or
It is preferable to use the MOCVD method. The same applies to the following steps. Thereafter, a p-type GaAs base layer 13 doped with, for example, Be as an impurity and having a relatively high impurity concentration is epitaxially grown on the collector layer 12. The thickness of the base layer 13 is preferably 1000 Å or less in order to realize high-speed switching operation. After this, a second emitter layer 14 ₂ made of n ^- type Ga _1-x Al _x As with a low impurity concentration is formed on the base layer 13, followed by an n ⁺ type layer with a high impurity concentration.
A first emitter layer 14 ₁ made of Ga _1-x Al _x As is grown epitaxially. In both cases, impurities are, for example,
Let it be S _i . At this time, the relationship between the concentration and thickness of the second emitter layer 14 ₂ is set to satisfy equation (1). Finally, etching is performed to remove the emitter center part and remove the peripheral part to expose the surface of the base layer 13.
Form 16 and 17 to complete. This will be explained using more specific numerical examples. Bandgap energy as second emitter layer 14 ₂
A 1.80 eV Ga _0.7 Al _0.3 As layer is used, its donor impurity concentration is N _E =3×10 ¹⁶ cm ^-3 , and its thickness is set to w = 0.1 μm. On the other hand, as the base layer 13, the acceptor concentration
N _B = 10 ¹⁸ cm ^-3 , band gap energy is 1.42eV
GaAs is used. At this time, room temperature T = 300
_The built-in potential V _bi at _〓 is ^expressed in equation (8) _as
As cm ^-3 , V _bi =1.52V. Therefore, when the applied voltage between the emitter and the base is zero, if the low concentration second emitter layer is sufficiently thick, the thickness w _dep of the depletion layer and the maximum electric field E ⁽⁰⁾ _nax that should be expanded are (2), ( When calculated from equation 3), with ε _s = 12.0, w _dep = 0.260 μm, and E ⁽⁰⁾ _nax = 1.17×10 ⁵ V/cm. However, in the present case, since w=0.1 μm, w<w _dep . At this time, the maximum electric field E _nax is E _nax =1.75×10 ⁵ V/cm from equation (7). Impurity concentration
Since the maximum electric field value that can be tolerated without junction breakdown for N _E = 3 × 10 ¹⁶ cm ^-3 is about 5.1 × 10 ⁵ V/cm (see, for example, SMSge, “Physics of
Semiconductor Devices”, 1969, Wiley−
(see Interscience), the above E _nax is lower than this,
The above design example can be actually adopted. For reference, if we calculate the applied voltage such that the maximum electric field E _nax is exactly the maximum allowable electric field mentioned above, the value is approximately
The voltage is 3.3V, ensuring sufficient voltage resistance for practical use. Next, as another design example, a case will be described in which the same materials as above are used, and N _E =10 ¹⁷ cm ^-3 , w = 0.1 μm, and N _B = 10 ¹⁸ cm ^-3 . At this time, V _bi = 1.55V, w _dep
= 0.144 μm, E ⁽⁰⁾ _nax = 2.16×10 ⁵ V/cm. At this time, w<w _dep . Also, E _nax = 2.30×
10 ⁵ V/cm, but the maximum allowable electric field corresponding to an impurity concentration of 10 ¹⁷ cm ^-3 is approximately 6.4×10 ⁵ V/cm.
This design example can also be adopted in reality. Similar to the previous design example, the allowable applied voltage is found to be approximately
The voltage is 4.0V, which is sufficient for practical use. Table 3 shows the switching characteristics determined by the numerical analysis model when the above two design examples are applied. The circuit conditions are the same as in Table 1.

[Table] As is clear from comparing these results with Table 1 above, the switching speed is slightly inferior to Type B, but far superior to Type A. Moreover, in Type B, it is difficult to ensure a breakdown voltage between the emitter and the base, whereas in this embodiment, it is easy to ensure a practically sufficient breakdown voltage. Note that the present invention is not limited to the above embodiments. For example, as a combination of semiconductor materials, it is possible to use Gap for the emitter layer of a wide band gap and Si for the base layer of a narrow band gap, or it is also possible to use GaAs for the emitter layer of a wide band gap and Gl for the base layer of a narrow band gap. .

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a conventional heterojunction bipolar transistor, Fig. 2 is a diagram for explaining the switching characteristics of the transistor, Fig. 3 is a circuit diagram for similarly determining the switching characteristics, and Figs. 5c is a diagram showing an impurity concentration distribution and an electric field distribution for explaining the features of the present invention, and FIG. 5 is a diagram showing a heterojunction bipolar transistor according to an embodiment of the present invention. 11...n ⁺ type GaAs substrate, 12...n type GaAs
Collector layer, 13...p-type GaAs base layer, 14 ₁
……n ⁺ type Ga _1-x Al _x As first emitter layer, 14 ₂ ……
n ^- type Ga _1-x Al _x As second emitter layer, 15-17...
………electrode.

Claims (1)

[Claims] 1. The emitter layer is made of a semiconductor material with a wider bandgap than the base layer, and is composed of a first emitter layer with a high impurity concentration on the electrode side and a second emitter layer with a low impurity concentration on the base side. , and in a heterojunction bipolar transistor in which the impurity concentration of the base layer is higher than that of the second emitter layer, the relationship between the impurity concentration N _E and the thickness w of the second emitter layer is expressed as the second emitter layer in the state of zero applied voltage. The maximum electric field E _nax = qN _B /2ε _s ε ₀ w + V _bi /w is set to satisfy N _B w ² ≦2ε _s ε ₀ /qV _bi within a range that does not exceed the maximum allowable electric field. Heterojunction bipolar transistor. However, in the above equation, q: Absolute value of electronic charge ε ₀ : Permittivity of vacuum ε _s : Relative dielectric constant of the second emitter layer V _bi : Built-in potential of the heterojunction formed by the second emitter layer and the base layer 2 Emitter layer is Ga _1-x Al _x As, and the base layer is
The heterojunction bipolar transistor according to claim 1, wherein the collector layer is GaAs or GaAlAs.