JPH0570925B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field of the Invention) The present invention detects alignment marks on the exposed substrate such as a wafer when exposing a pattern formed on a mask to a substrate to be exposed, such as a wafer, to align the mask and the substrate. Regarding how to align.

(Background of the Invention) In recent years, reduction projection type exposure equipment has been widely introduced to VLSI production sites, and has brought great results.

In such an exposure apparatus, a pattern drawn on a reticle or mask is projected through a projection optical system, such as a 1/5 reduction projection lens, and the projected image is transferred to a photosensitive substrate (wafer, etc.) on which a pattern has been formed in advance. ), the desired semiconductor device is regraphed by overprinting. At this time, if the projected image of the reticle or mask pattern is not accurately formed on the wafer, a blurred pattern will be formed on the wafer, causing a problem of so-called poor resolution.

Furthermore, unless the projected image and the pattern formed on the wafer are accurately aligned,
This may cause problems such as the characteristics of the manufactured semiconductor device becoming inadequate or, in extreme cases, the semiconductor device itself becoming inoperable. In order to solve these problems, it is required to accurately focus the projected image on the surface of the wafer and to accurately align the reticle (mask) and the wafer. In recent years, so-called through-the-lens (TTL) alignment has been developed in which the alignment marks formed on the wafer are observed together with the alignment marks on the reticle through a reticle (or mask) and projection optical system. ) type alignment equipment came into use. In this TTL method, marks on the wafer and marks on the reticle are detected at the positions to be projected and exposed via the projection optical system, so high alignment accuracy can be expected. This TTL type alignment device is disclosed in, for example, Japanese Patent Application Laid-Open No. 55-41739. here,
Wafer alignment marks and other wafer alignment marks are formed on predetermined chips formed in a matrix on a wafer, with extension lines intersecting each other almost perpendicularly and arranged radially outward from the center. A rectangular or linear reticle alignment mark is formed at a position on the reticle corresponding to the position of this linear wafer alignment mark, and a reduction projection lens is disposed between the wafer and the reticle. The wafer alignment mark and the reticle alignment mark are illuminated by a reduction projection lens at at least two locations where the X-Y table on which the wafer is mounted is moved forward at each chip interval, and the wafer alignment mark and reticle alignment mark are capturing a light image with an imaging device;
The relative displacement of both marks (for each of the X-axis direction and Y-axis direction) is determined from the resulting video signal.
An apparatus is disclosed that detects the wafer and the reticle and relatively displaces the wafer and reticle so that each displacement disappears.

By the way, since the wafer alignment mark is formed so as to protrude or recess with respect to the base (substrate), the following problems occur. In other words, since alignment between the wafer and reticle is performed with the wafer coated with photoresist, stable wafer alignment is affected by various conditions such as the difference in level between the wafer alignment mark and the base, the refractive index of the resist, and the film thickness of the resist. Mark information cannot be obtained. In an alignment apparatus such as that disclosed in the above-mentioned patent publication, a wafer alignment mark is illuminated with monochromatic light (same wavelength as the exposure light) through a reticle and a reduction projection lens,
A wafer alignment mark and a reticle alignment mark are superimposed and imaged on a predetermined conjugate plane,
This is imaged by an imaging device, converted into a video signal, and the imaged signal is subjected to predetermined signal processing to align the reticle and wafer. Then, because there is a difference in level between the base of the area corresponding to the wafer alignment mark and the base of the surrounding area, the illumination light reflected from the surface of the resist film and the illumination light reflected from the base of the area corresponding to the wafer alignment mark interfere with each other. wake up We identified the following two causes of this interference.

(1) First cause: This is due to the difference in level between the base of the portion corresponding to the wafer alignment mark and the base around it, and the size of the wafer alignment mark. For example, a wafer alignment mark made by sputtering aluminum or the like on a base made by an anisotropic dry etching process has a steep step. When a photoresist is applied on top of the photoresist, the film thickness of the photoresist changes continuously. FIG. 8a schematically shows the relationship among the underlayer 1, photoresist 2, and wafer alignment mark AM1.
The alignment mark AM1 is formed recessed in the base 1 (it may also be formed to protrude), and a translucent photoresist 2 is applied thereon. Base 1 has light reflective properties. FIG. 8b shows the film thickness of the photoresist.
As is clear from this, the stepped portions 1a and 1b
The film thickness changes in the vicinity. A steep change in film thickness does not pose much of a problem, but there is a film thickness that satisfies the interference condition at gentle changes on both sides, and interference occurs there.

Now, the optical refractive index of photoresist 2 is n
When the distance between the resist surface and the base 1 (that is, the thickness of the resist film) is d, the optical distance D between the resist surface and the base can be expressed as D=n·d. Therefore, the condition when the monochromatic illumination light reflected from the resist surface and the base interferes is as follows, where λ is the wavelength of the monochromatic illumination light, n・d=
It becomes λ/2. That is, d=λ/2n.
For example, if it is illuminated with monochromatic light of λ=436 nm and n=1.67, then d=130 nm. Therefore, interference fringes will occur when the thickness of the resist film is an integral multiple of 130 nm (of course, if the wavelength of monochromatic light differs, the thickness of the resist film where interference fringes occur will differ).

Therefore, if the resist film thickness at the portion corresponding to the wafer alignment mark AM1 satisfies the above interference condition, interference fringes 3a to 3a as shown in FIG. 9a will be formed.
3e occurs. The imaging device captures an optical image whose contrast changes depending on the resist film thickness, and generates a corresponding video signal. For example, when scanning is performed as shown by the arrow in FIG. 9a, the video signal has a waveform as shown by the solid line S1 in FIG. 9b. This video signal contains many noise components corresponding to interference fringes, resulting in a poor S/N ratio. On the other hand, if interference fringes do not occur, the contrast will constantly change between the wafer alignment mark AM1 and both sides thereof, as shown by the dotted line S2 in FIG. 9b.
The position of wafer alignment mark AM1 can be recognized, for example, by detecting the rising and falling parts of the video signal (corresponding to the parts where the contrast of the image changes) and detecting the center of these rising and falling parts. do. Therefore, if interference fringes occur, the position of the wafer alignment mark will be misrecognized.

As described above, interference fringes occur near the step portion and become a problem when the distance between the steps 1a and 1b (width of the mark) is approximately 4 μm or more. When this distance is about 4 μm or less, the surface of the photoresist becomes substantially flat due to the viscosity of the resist, as shown in FIG. 10a. Therefore, the film thickness of the photoresist changes as shown in FIG. 10b. In other words, the photoresist film thickness changes sharply, and even if interference fringes occur, there will be only about one, so the S/N ratio of the video signal is good. In fact, photoresist OFPR800 manufactured by Tokyo Ohka Co., Ltd. (viscosity
20cp), it has been confirmed that the relationship between the occurrence of interference fringes and the mark width is as described above.

(2) Second cause: This is unrelated to the size of the step or mark mentioned above, and the resist film thickness is d.
If the wavelength is an integral multiple of ≒130 nm, interference fringes will occur at locations other than the step portion. Therefore, for any of the wafer alignment marks shown in FIGS. 8a and 10a, if the resist film thickness satisfies the interference condition, interference fringes will occur and the same problem as described above will occur.

(Objective of the Invention) The main object of the present invention is to provide an alignment method that is free from the influence of interference fringes caused by the first and second causes.

(Summary of the Invention) When a pattern formed on a mask (reticle) is transferred onto a resist layer 2 on a substrate (wafer 1) by a projection exposure device, an alignment pattern is formed on the surface of the substrate 1 with an uneven structure. The mark is optically detected by the mark detection means in the exposure device (an alignment device that observes the mark using a through-the-lens method or detects the mark from the image signal of the imaging device), and based on the detection result. In the method of aligning the exposed area (IC chip patterns C ₁ to _{C 6} ) on the substrate 1 with the pattern of the mask (reticle), the width in the detection direction by the mark detection means (scanning direction of the imaging device) is 4μ on 1
m or less, a pair of the first protruding mark 31A and the first recessed mark 31B, and the width in the detection direction is
forming a pair of a second protruding mark 30A and a second recessed mark 30B larger than 4 μm on the surface of the substrate 1, and applying a resist layer 2 thereon; ,30B,31A,
31B by the mark detection means through the resist layer 2, and select one mark with the best detection result from among the four marks, and during subsequent alignment, the selected one is detected. The mark form is used to align a mask (reticle) and a substrate (wafer).

As in the present invention, a pair of a protruding mark and a recessed mark having a small width and a pair of a protruding mark and a recessed mark having a large width are formed on a wafer and used in the alignment method of the present invention. In some cases, a plurality of pairs or sets are formed. This is a method in which alignment is performed using wafer alignment marks provided at different positions during each exposure. In other words, wafer alignment marks are provided in advance on the wafer in a number equal to the number of times of repeated exposure. One of the marks is used for alignment with the reticle, but once the mark is used for alignment, it may be deformed by exposure and development processing, so it is never used again, and one of the remaining marks is used for the next exposure. This alignment method uses two methods. Each mask is provided with a reticle mark corresponding to a prespecified alignment mark on the wafer.

In addition, a pair or a set of alignment marks are formed in the first baking process on the wafer as disclosed in Japanese Patent Publication No. 52-34907, and are aligned with a series of reticles in the subsequent baking process. In the method commonly used for matching, it is sufficient to prepare one pair or one set.

Now, the meanings of marks with a width of 4 μm or more and marks with a width of 4 μm or less used in the present invention will be explained. When a wafer alignment mark is bounded by a steep step as in an anisotropic dry etching process, it is desirable to reduce the size (width) of the mark so that interference fringes are less likely to occur. FIG. 2 shows three examples of the shapes of wafer alignment marks. FIG. 2a shows a square mark, FIG. 2b shows a triangular mark, and FIG. 2c shows a trapezoidal mark. The width (W ₁ ) of each mark is set to a value that makes it difficult for interference fringes to occur when photoresist is applied, for example, W ₁ <4 μm. This width direction is the direction scanned by the imaging device. on the other hand,
The length _H1 of each mark is determined by how much scanning the imaging device needs in this length direction, and is actually 8 to 10 μm. Note that the mark in FIG. 2a does not preclude the fact that it is a square with W ₁ =H ₁ . Further, the standard for determining the width W ₁ of the mark is W ₁ <2d ₀ when the depth of the step portions 1a and 1b is d ₀ (shown in FIG. 10a). depth d ₀
is 1 to 1.5 .mu.m in a normal wafer process, so the mark width _W1 is preferably 1 to 3 .mu.m.

By doing this, the surface of the photoresist film becomes almost flat (if the mark width is small, the surface of the photoresist film tends to be flat even if the underlying surface is slightly uneven), and as a result, the photoresist film becomes flat. The film thickness becomes steep as shown in FIG. 10b. Therefore, even if interference fringes occur, there will be only about one, and the S/N ratio of the video signal of the imaging device will improve.

On the other hand, when forming wafer alignment marks using a selective oxidation process (LOCOS), the larger the wafer alignment marks, the better the image quality when optically overlapping with the reticle mark after resist application. (In the case of LOCOS, the slope of the stepped portion shown in FIG. 10a is gentle). Therefore, if the large wafer alignment marks shown in Fig. 2 d, e, and f and the small wafer alignment marks shown in Fig. 2 a, b, and c are formed on the same wafer (base), they will be different. A small wafer alignment mark formed by the directional dry etching process or a large wafer alignment mark formed by the selective oxidation process can be selectively photoelectrically converted by an imaging device. In this way, the wafer alignment mark to be imaged can be selected and imaged according to the wafer alignment mark forming process. In FIGS. 2 d to e, the width (W ₂ ) of the imaging device in the scanning direction is preferably 4 μm or more, for example, W ₂ =about 10 μm. Set the length H ₂ as necessary, and W ₂ =
It may be _H2 .

Figure 3 shows the reticle used to transfer small and large wafer alignment marks onto the wafer.
Indicates R ₁ ′. The mark patterns 13, 14, 30, and 31 are arranged with respect to the optical axis 15 of the imaging optical system in a positional relationship rotated by 90 degrees around the circuit pattern area 11. Mark patterns 13 and 14 for small wafer alignment and mark patterns 30 and 31 for large wafer alignment marks
are arranged in tandem on a ray passing through the optical axis 15, respectively.

By the way, as explained above, when the resist film thickness becomes d≈130 nm, interference fringes occur, leading to erroneous recognition of the position of the wafer alignment mark. Therefore, in the present invention, as shown in FIG. 4, at least one pair of a protruding wafer alignment mark AM10 and a recessed wafer alignment mark AM20 is formed on the same substrate. and,
A photoresist 2 is applied onto this base 1 using a resist coating device. The resist coating device rotates the wafer and drops liquid photoresist onto it. Therefore, the photoresist is spread over the entire surface of the wafer by centrifugal force, and when the rotation of the wafer is then stopped, the surface of the photoresist becomes a substantially flat surface. Therefore, the resist film thickness at the portion corresponding to the protruding wafer alignment mark AM10 is
d ₁ becomes thinner than the surrounding resist film thickness d ₃ .
In addition, the resist film thickness _d2 of the portion corresponding to the recessed wafer alignment mark AM20 is the film thickness around it.
d will be thicker than ₃ .

When the protruding mark AM10 and the recessed mark AM20 are formed as a pair in this way, for example, if the resist film thickness at the protruding mark AM10 satisfies the interference condition (d ₁ ≒ 130 nm), the recessed mark AM2
The resist film thickness at the 0 portion does not satisfy the interference condition (d ₁ ≠130 nm). Therefore, even if one of the pair of marks AM10 and AM20 generates interference fringes and cannot be used for alignment with the reticle, the other mark does not generate interference fringes or can be ignored even if they occur. There is. The operator may observe a microscope, a television monitor, etc., determine which mark has interference fringes, and select the mark to be used for alignment with the reticle. Note that the shape of the wafer alignment mark depends on the alignment method, and may be selected from rectangular, triangular, circular, etc. depending on the alignment method.

FIG. 5 shows a reticle R ₁₀ used to transfer raised and recessed wafer alignment marks onto a wafer. A rectangular circuit pattern area 11 is formed in the center of the reticle _R10 , and a light shielding area 12 in which chrome or the like is vapor-deposited is formed around the rectangular circuit pattern area 11. Circuit pattern area 11
For example, the first layer pattern for making an IC is formed. Patterns for forming protruding and recessed wafer alignment marks are formed in the light-shielding region 12 . A pattern 18 for forming a protruding wafer alignment mark extending in the Y-axis direction is constructed by providing a light-transmitting portion 18 of a predetermined shape in the light-shielding region 12. The pattern 19 for forming a recessed wafer alignment mark extending in the Y-axis direction is constructed by leaving a light-shielding portion 19 of a predetermined shape in the light-shielding region 12 and forming a light-transmitting portion 20 around the light-shielding portion 19 . A pattern 21 for forming a protruding wafer alignment mark extending in the X-axis direction is constructed by providing a light-transmitting portion 21 of a predetermined shape in the light-shielding region 12. The pattern 22 for forming a recessed wafer alignment mark extending in the X-axis direction is constructed by leaving a light-shielding portion 22 of a predetermined shape in the light-shielding region 12 and forming a light-transmitting portion 23 around the light-shielding portion 22 . Also, regarding the optical axis 15 of the projection optical system that projects the pattern on the reticle onto the wafer, the reticle
The patterns 18 and 19 on _R10 are arranged in tandem in the same radial direction centered on the optical axis, and the patterns 21 and 22 are also arranged in cascade in the same radial direction centered on the optical axis. This reticle _R10 is transferred onto a wafer using a step-and-repeat reduction projection exposure device and developed to form IC chip patterns _C1 to _C6 and wafer alignment marks.
AM10 and AM20 are arranged as shown in FIG. In FIG. 6, each IC chip pattern is formed as a mark group AMX for the X direction and a mark group AMY for the Y direction.

Note that the patterns 18, 19; 21, 22 are not limited to being arranged in tandem as described above, but can be arranged in various ways depending on the alignment method.

FIG. 7 shows optically superimposed images of the reticle alignment mark (transparent part) 24 and the protruding and recessed wafer alignment marks. The illustrated state is a state in which the reticle for exposure of the second and subsequent layers and the wafer are correctly aligned. To align the reticle alignment mark and the wafer alignment mark, first, the optical image shown in Figure 7 is scanned by an imaging device in the direction of the arrow to convert the video signal, and the respective boundaries between the reticle alignment mark and the wafer alignment mark are To detect. and,
Both boundaries 24a of the reticle alignment mark,
The reticle and the wafer are relatively moved so that the center of the interval 24b matches the center of the interval between the boundaries 26a and 26b of the wafer alignment mark. (Positioning using the so-called sandwich method). If this is done in the X-axis direction, the reticle and wafer (strictly speaking, each IC chip pattern on the wafer) are accurately positioned. Various video signal processing methods for this positioning have been proposed, and since they are not directly related to the present invention, their explanations will be omitted.

Now, the present invention is a combination of both the pair of a small mark and a large mark and the pair of a protruding mark and a recessed mark as described above.
Even if interference fringes occur due to both the first and second causes, the interference fringes are not affected by the interference fringes.
FIG. 1 shows a reticle pattern for simultaneously forming four types of wafer alignment marks on a wafer: small, large, protruding, and recessed. The light shielding portion 12 around the reticle includes a pattern (large rectangle) 30A for forming a large-sized protruding wafer alignment mark, a pattern (large rectangle) 30B for forming a large-sized depressed wafer alignment mark,
A pattern (small rectangle) 31A for forming a small protruding wafer alignment mark and a pattern (small rectangle) 31B for forming a small recessed wafer alignment mark are provided. The patterns 30A and 31A are formed by providing a light-transmitting region in the light-shielding portion 12. pattern 30B,
31B is a predetermined light transmitting area (rectangular) in the light shielding part 12.
32 and leave a light shielding part therein. This pattern 30A, 30B,
Various types of 31A and 31B can be selected as shown in the second diagram.

The pattern on the reticle corresponding to each of the above wafer alignment marks is larger than the wafer alignment pattern by the imaging magnification of the imaging optical system. In the case of 1:1 true-magnification imaging, the reticle pattern corresponding to the wafer alignment pattern may be the actual size.Also, the patterns for forming wafer alignment marks on the reticle were arranged vertically in the radial direction; The arrangement is not limited to this and may be arranged in parallel. Furthermore, although the wafer alignment marks are placed directly on the substrate,
The mark may be formed by forming a layer of another substance on the base and etching or the like.

(Effects of the Invention) According to the present invention as described above, since large and small wafer alignment marks and protruding and recessed wafer alignment marks are formed in combination, even if interference fringes occur on one wafer alignment mark, they will not appear on the other. No interference fringes occur, or even if they do occur, they can be ignored. Therefore, compared to the conventional method in which only one alignment mark is formed, the success rate of alignment with the reticle is greatly improved. Considering that if repeated printing is performed while there is an error in alignment with the reticle, the pattern previously transferred onto the wafer will be misaligned, resulting in the IC chip being a defective product. Being able to select a wafer alignment pattern that does not occur (or occurs less often) greatly contributes to improving yield.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a reticle for transferring four types of wafer alignment marks, small, large, protruding, and recessed, onto a wafer according to an embodiment of the present invention;
Figures 2 a to f are diagrams showing the shapes of wafer alignment marks according to embodiments of the present invention, and Figure 3 shows reticles for transferring small and large wafer alignment marks on wafers according to embodiments of the present invention. Figures 4a and 4b are diagrams schematically showing the relationship between the protruding and recessed wafer alignment marks, the underlayer, and the photoresist film according to the embodiment of the present invention,
5 is a diagram showing a reticle for transferring protruding and recessed wafer alignment marks on a wafer according to an embodiment of the present invention, and FIG. 6 is a diagram showing a reticle for transferring an IC chip and a wafer alignment mark according to FIG. A diagram showing the arrangement relationship, FIG. 7 is a diagram showing an optically superimposed image of a reticle alignment mark and a wafer alignment mark, and FIG. 8a is a diagram showing a wafer alignment mark.
Figure 8b is a diagram schematically showing the relationship between the base and photoresist film, Figure 8b is a diagram showing the film thickness of the photoresist, Figure 9a is a diagram showing how interference fringes occur, and Figure 9b is an image. FIG. 10A is a diagram showing the waveform of the signal, FIG. 10A is a diagram schematically showing the relationship between the wafer alignment mark, the underlayer, and the photoresist film, and FIG. 10B is a diagram showing the film thickness of the photoresist film.

Claims (1)

[Scope of Claims] 1. When transferring a pattern formed on a mask to a resist layer on a substrate using an exposure device, an alignment mark formed with an uneven structure on the surface of the substrate is transferred into the exposure device. In the alignment method, the exposure area on the substrate is optically detected by a mark detection means, and the pattern of the mask is aligned with the exposed area on the substrate based on the detection result, before the substrate is supplied to the exposure apparatus. a pair of a first protruding mark and a first recessed mark whose width in the detection direction by the mark detection means is 4 μm or less on the substrate; and a second pair whose width in the detection direction is larger than 4 μm on the substrate. forming a pair of a protruding mark and a second recessed mark on the surface of the substrate, and applying a resist layer thereon; a step of detecting with a mark detection means and selecting one mark form with the best detection result from among the four marks; during subsequent alignment between the substrate and the mask;
and using the selected one mark form. 2. The method according to claim 1, wherein the width of the first protruding mark and the first recessed mark is set in a range of 1 to 3 μm. 3. A patent characterized in that the width W ₁ of the first pair of marks is set to W ₁ ≦2d ₀ , where the step amount of the first protruding mark or the first recessed mark is d ₀ . The method according to claim 1 or 2.