JPH0570216B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a motor control circuit, and particularly to a motor control circuit that automatically corrects the speed offset of a speed control system and further intentionally gives a slight speed offset from its operating point. , relates to a motor control circuit suitable for fine speed adjustment.

[Background of the invention]

Until now, there has been no literature related to a steady-state speed error correction device as dealt with in the present invention, so an explanation will be provided based on an example previously proposed by the applicant.

FIG. 1 is a block diagram showing an embodiment of a magnetic recording/reproducing apparatus previously proposed by the applicant, and FIG. 2 is a diagram for explaining its operation.

In FIG. 1, 1 is a magnetic tape, 2 is a rotary head for recording and reproducing image information, 3 is a cylinder motor,
4 is generated by the rotation of the cylinder motor 3,
A signal generator that generates a signal with a frequency proportional to the rotational speed; 5 and 12 are speed offset correctors 6 and 13;
is a frequency-voltage converter (hereinafter abbreviated as -v converter); 7 and 14 are amplifiers; 8 and 15 are drivers for the motor 3; 9 is a capstan motor that runs the magnetic tape 1; and 10 is a capstan motor. 9 is a rotation signal generator, and 11 is a frequency divider. The control systems for the motors 3 and 9 have the same configuration except for the frequency divider 11, and form a speed control system. In actual motor control, phase control is also performed to synchronize the rotational phases of both motors, but this will not be discussed here. Control by this system during normal recording and playback is the same for both motors, and will be explained below by taking the control system of the cylinder motor 3 as an example. The difference between this embodiment and general control is the speed offset corrector 5. Expressing the influence of the disturbance ΔV at the output point of the -v converter 6 on the motor angular velocity ω using only other factors, it becomes ω(S)=AI/JS/1+AI/JSDΔV(S). However, A: Transfer function of amplifier 7 I: Transfer function of motor driver 8 1/JS: Transfer function of motor 3 D: Transfer function of -v converter 6. When the steady-state deviation is determined with S=0, Δω=1/DΔV(0), and the voltage offset ΔV causes the speed offset Δω. To cancel this, −
The speed offset corrector 5 is responsible for DC shifting the characteristics of the v converter 6. The operation of the speed offset corrector 5 will be explained below with reference to FIG. Figure 2 is a characteristic diagram of the -v converter 6, where the vertical axis is the output voltage;
The horizontal axis is the input frequency, ₀ is the desired frequency, and 19 to 25 indicate the operating points, respectively. now,
The -v converter characteristic is 17 and it should operate at the operating point 20 which outputs the voltage V ₀ , but if a voltage disturbance -ΔV occurs due to variations etc. and it operates at the operating point 24, the rotation speed will be ₁ (in the delay direction) I can wear it. In this case, the speed offset corrector 5 measures the period using an internal accurate clock, and moves the -v characteristic stepwise in parallel to the high voltage output. and,
At the operating point 22 where the disturbance -ΔV is canceled, the parallel movement effect by the corrector 5 is continued until it operates according to the characteristic 18. At this point, the motor 3 is controlled so that the motor rotation signal has a cycle with a desired value of ₀ . Contrary to the above operation,
When a voltage disturbance +ΔV occurs, the motor 3 rotates so as to generate a rotation signal having a frequency of ₂ (over-rotation direction) at an operating point 25. After accurate period measurement using the internal clock, the corrector 5 gradually moves the -v characteristic parallel to the low voltage output direction, and finally the characteristic 16.
It operates at operating point 23 and frequency ₀ according to . These operations are similar in the speed control system of the capstan motor 9. In this way, the motor rotational speed is automatically driven to a value very close to the desired value, and the previously required volume adjustment is no longer necessary. Here, normal recording and playback is performed very smoothly. In contrast, next we will consider operations in fast playback or slow motion playback, which is generally called variable speed playback. For example, in the case of quick playback, the frequency divider 11 in FIG. 1 divides the frequency of the rotation detection signal by n. Then, the system operates so that the n-divided signal matches the original frequency, and as a result, the system rotates at n times the speed. In this way, the tape speed is increased by n times. The track pattern recorded at this time is transferred to the rotating head 2.
Since the tape 1 and the head 2 cross each other, the relative speed between the tape 1 and the head 2 becomes different from that during recording. Therefore, the horizontal synchronization signal period of the reproduced signal is shifted. On the other hand, in the signal processing system, the horizontal synchronization period H is used as a unit.
Processing such as adding to the signal from 1H before is performed, but
Since the time amount of 1H is fixed for each component, a time lag occurs, which interferes with image reproduction. For example, since a 1H delay element is used for color processing,
This may cause color shift or blurring. In order to cope with such a phenomenon, it is necessary to finely adjust the speed of the drum motor 3. The theoretical value of this fine adjustment amount is determined as follows. The relationship among the track pattern described above, the speed of the head on the drum, the tape speed, etc. will be clarified using FIG. FIG. 3A is a track pattern recorded on the magnetic tape 1, and FIG. 3B is a velocity vector diagram on coordinates fixed on the tape 1, with 0 as the origin. In b, 30 to 36 are velocity vectors, and 30 is a velocity vector of the head on the cylinder 31 is a velocity vector during standard recording and playback of the tape 1. Since these coordinates are fixed on the tape 1, the velocity vector of the tape 1 is displayed in the opposite direction to the running direction. If tape 1 now follows velocity vector 31, the actual head motion vector will be 32. On the other hand, when the vehicle travels at n times the speed, the velocity vector changes as shown in 33. At this time, the composite vector is 34, and its absolute value is smaller than the vector 32, that is, the value at the time of recording. On the other hand, to match the relative velocity at the time of recording, the vector 3
The resultant vector 35 may be set equal to the absolute value of 2, and for this purpose, the head velocity vector is slightly changed as shown in the vector 36. The ratio x of the amount of change in the magnitude α is x=α _H (n-1)/N _H (1) using α _H in the figure. However, N _H is the number of horizontal synchronization signals in one track pattern, and in NTSC TVs,
There are 262.5 pieces. n is a double speed number, which changes from a positive number in the 0 standard direction when the tape is stationary to a negative number in the reverse direction. In this way, during variable speed playback, it is necessary to finely adjust the head speed, ie, the speed of the cylinder motor 3 during standard recording and playback, by the ratio shown in equation (1).

[Purpose of the invention]

The purpose of the present invention is to eliminate the need to adjust the speed of the motor speed control system, ensure performance at standard speed, and
Another object of the present invention is to provide a motor control circuit for a magnetic recording and reproducing device that provides high quality reproduced images during variable speed reproduction.

[Summary of the invention]

The main focus of the present invention is to change the output of the speed offset corrector by a predetermined amount so that the -v conversion characteristic automatically set during steady recording and playback is further moved by a predetermined minute adjustment, and to reproduce the -v characteristic. It's about resetting.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In FIG. 4, 40 is an adder and 41 is a constant voltage generating circuit. Further, to explain the operation of this embodiment, the -v conversion characteristic diagram shown in FIG. 5 will be used. 4 in the diagram
5 and 46 are -v conversion characteristics, and 47 and 48 are operating points. In this operation, the speed offset corrector 5 moves the operating point of the initial setting characteristic 17 from the desired frequency ₀ to 24 by the voltage offset -ΔV to the operating point 22 of the characteristic 18. operates as described above. Here, ₀ is the desired rotation detection signal frequency of the cylinder motor 3 that moves the head 2 during standard recording and playback, and as mentioned above, during fast playback and slow motion playback.
It is necessary to slightly change the ratio shown in equation (1). For this purpose, the constant voltage generation circuit 41 is
This is to add or subtract a DC voltage of Δv. As an example, a detailed explanation of an actual magnetic recording/reproducing device will be continued. In the NTSC system, the number of H per screen scan N _H = 262.5H, and in a certain recording mode of the VHS (registered trademark) system, α _H = 1.5H,
When performing quick playback at a forward speed of 5 (n=5), the desired value of the minute change amount x is +2.3%. In FIG. 5, when the constant voltage generator 41 generates Δv ₁ , Δv ₁ is added to the output from the corrector 5 (based on the element 40), and a transition is made to the characteristic 48. Then, the system comes to operate at the operating point 48, so a rotation detection signal with a frequency of ₄ higher than ₀ is generated, causing the motor to rotate. ₄ =
If Δv ₁ is generated so that it becomes 1.023× ₀ , an appropriate small amount of speed change will be given. Conversely, the number of reverse speeds n=
-5, the desired value of x is -3.4%, so
When the constant voltage generator 41 generates -Δv ₂ , it is sufficient to generate -Δv ₂ so that ₃ = 0.966× ₀ at the operating point 47. In this way, if the output from the constant voltage generating circuit 41 is switched and controlled by a reproduction mode signal such as quick reproduction, a good reproduced image without color shift, color blurring, etc. as described above can be obtained. Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 6, 50 is a pulse generator, 51 and 53 are counters, 52 and 55 are latches, 54 is an up-down counter, 56 is a digital-analog converter, and 5
7 and 60 are bit pattern generators, 58 is an adder, 59 is a clock generator, 61 to 64 are signals,
65 is a bit pattern switching circuit, 66 is a variable speed command signal, and 67 is a hold circuit. In this embodiment, the control system for the capstan motor 9 is the same as in the previous example, and will be omitted hereafter. FIG. 6 is an example in which the analog expression in the previous embodiment is implemented using a digital circuit. The following explanation will be given using a time chart (Fig. 7) in which the pattern of signals 61 to 64 displayed in Fig. 6 and the counts of counters 51 and 53 are quantitatively shown as 75 and 76 on the vertical axis. . Note that 75 and 76 are originally digital count values that increase in a stepwise manner.
Now, in FIG. 6, the pulse generator 50 receives the rotation detection signal 61 and outputs a signal 62 which becomes low for a certain period of time at the rising edge of the detection signal 61, for example. This signal 62 controls the operation period of each of the counters 51 and 53, and for example, in this example, the counting operation continues only during this high period. Further, the pulse generator generates a latch pulse 64 and a preset pulse 63 at appropriate timings (signal 64 is earlier than signal 63) during the low period of signal 62. Now, if the clock signal period generated from the clock generator 59 is T _CL and the desired rotation detection signal period during standard recording and playback is T ₀ , then the predetermined number N of clock measurements for one period is T ₀ /T _CL .
However, in reality, the counter stop time T _I (signal 6
(period of 2 rows), so N=(T _O −T _I )/T _CL . Now, the count value of the counter (00001) ₂ (binary number)
In order to ensure that _every rising edge _of the rotation detection signal 61 is observed with a period of _T0 at the moment when it reaches the midpoint between . (At this time, the bit pattern generator 60 outputs M.) Then, when the period of the signal 61 is greater than _T0 , the count value
Since the MSB is 1 and becomes 0 when it is small, by latching this with the latch 52, the direction of deviation from the desired rotation value can be determined. On the other hand, assuming that the up-down counter 54 is initialized to zero in advance when the motor 3 is stopped, the output from the bit pattern generator 57 itself becomes the output of the adder 58. This value is the preset value of the counter 53 and corresponds to 67 in FIG. Now, when the output from the bit pattern generator 57 is made to match the output from the bit pattern generator 60, that is, the above-mentioned M, the counters 51 and 53 perform equal counting operations. At this time, if speed control is performed at a period T ₁ that is slower than the desired period T ₀ , each timing chart is
It becomes as shown by the broken line in the figure. In contrast, an appropriate clock pulse (signal 63 may be used) generated from the pulse generator 50 is input to the up-down counter 54, and the output of the latch 52 described above is used as an up-count or down-count mode switching signal. For example, the output to adder 58 changes from an initial value of zero. Here, the output of latch 52 is 1
If 0 indicates up and 0 indicates down, if the desired period is in the direction of delay as shown in Fig. 7, the signal 61
The up-down counter 54 counts up every cycle. Therefore, the output of the adder 58 changes in an increasing direction with respect to the initial value (67 in FIG. 7). The counter 53, which has this value as its preset value, is also shifted in the direction where the counted value becomes larger, and the value latched at 55 also increases. This operation is performed by signal 61
The speed deviation continues until the period of T ₀ ±T _CL is within T ₀ ±T _CL , and then the speed deviation is reduced until it repeats a slight fluctuation at T 0 ±T CL. On the contrary, if the frequency deviates from the desired frequency in a faster direction, the up-down counter 54 counts down and the output of the adder 58 changes in the decreasing direction. In this way, the motor is decelerated and driven to within the period deviation ±T _CL .

Next, the operation of the bit pattern switching circuit 65 as the color blur prevention circuit in this system will be explained. It was mentioned earlier that the rotation speed of the drum motor 3 should be finely adjusted by +2.3% in the forward 5x fast playback.

Now, assuming that the preset value M, the clock cycle T _CL , and the desired rotation detection signal cycle are T ₀ for the predetermined number N of clock measurements during standard playback, the desired number of clock measurements N ₁ during 5x quick playback is N ₁ = N ×(1-0.023)=N-0.023N. As explained above, during standard reproduction, the system operates so that the number of clocks measured is close to N within the rotation detection signal period T ₀ ±T _CL . On the other hand, during 5x speed playback, the hold circuit 67 operates in response to the command signal 66 to hold the output of the up-down counter 54, and at the same time the bit pattern generator 5
The bit pattern switching circuit operates so that 7 outputs M+0.023N. Then, the rotation is accelerated by an amount corresponding to the increase in the preset value of the counter 51 (0.023N). At this time, the number of clocks counted during one period of the rotation detection signal is N-0.023N, which coincides with the desired value.

On the other hand, taking reverse direction 5x quick playback as an example, the desired value for the fine adjustment amount is -3.4%, so the desired clock count value N ₂ is N ₂ = N x (1 + 0.034) = N + 0.034N. be. Therefore, the output of the bit pattern generator 65 may be M-0.034N.

Considering these things, the desired output value of the bit pattern generator 65 for the preset value is M+N× _{α H ( n-} 1)/N _H. Here, M: Preset value bit pattern during standard playback α _H : Discrepancy between recording patterns on the magnetic tape
Value converted into a number n: Running speed ratio to tape running speed during standard playback (forward direction +, reverse direction -) N _H : Number of H per track (number of H per one screen scan) N : The number of clocks counted per cycle of the rotation detection signal during standard running. An example in which the adder 58 in this example is unnecessary will be described below.

FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. 9 is a corresponding waveform diagram of essential parts. Reference numeral 90 in FIG. 8 is a counter start signal for starting the counter 53. Also, 80,8 in Figure 9
1 quantitatively shows the counts of the counters 51 and 53, and 82, 83, 84, and 85 show how the counts change depending on the playback speed. Furthermore, 86 and 87 indicate constant count values. Now, in the above example, the counters 51 and 53 always performed counting operations simultaneously and independently, but in this embodiment, the counters 51 and 53
3 are operated temporally in series. That is, when the count value 80 of the counter 51 reaches the value 86, the counter 53 is then operated. Counter 5 at this time
The initial value of 3 (87 in FIG. 9) uses the bit information of the up-down counter 54. This bit information is automatically corrected so that there is no speed offset during single-speed playback, and is held by the hold circuit 67 during variable-speed playback, as in the previous example. Furthermore, in this example, the initial value of the counter 51, that is, the value of the bit pattern generator 60, is switched by a bit pattern switching circuit 65. That is, the above-mentioned M is subjected to fine adjustment corresponding to α _H (n-1)/N _H ×N. For example, while the counter 51 operates at the count value shown in FIG. 982 at the standard 1x speed, when playing back at the nx speed, the bit pattern which is the preset value is changed to α _H (n-1)/N _H ×N. By causing the counter 51 to operate according to the characteristic indicated by 83. Then, the time required to reach the count value of 86 is different, and therefore the counter 5
The operation start time of No. 3 is changed. In this way, the rotation of the motor 3 is controlled so that the period of the signal 61 is finely adjusted at a ratio of α _H (n-1)/ _NH , and a predetermined operation is realized.

As described above, according to the present invention, it is not necessary to adjust the volume in the speed control system, and it is possible to always obtain high-quality reproduced images at various reproduction speeds such as quick playback.

[Effects of the Invention] According to the present invention, by eliminating the speed adjustment volume, it is possible to reduce costs such as parts costs and labor costs for adjustment, and improve reliability of the control system.
Appropriate speed correction is applied at various playback speeds, resulting in improved performance.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining the conventional example, Fig. 2 is an explanatory diagram of the operation of the example shown in Fig. 1, Fig. 3 is a diagram for explaining deficiencies in the conventional example, and Fig. 4 is a book A block diagram of one embodiment of the invention, FIG. 5 is an explanatory diagram of the operation of the example shown in the block diagram of FIG. 4, FIG. 6 is a block diagram showing another embodiment of the invention, and FIG. FIG. 3 is a waveform diagram of main parts of the embodiment shown in the figure. FIG. 8 is a block diagram showing another embodiment of the present invention, and FIG. 9 is a waveform diagram of the main part of FIG. 50... Pulse generator, 51, 53... Counter, 52, 55... Latch, 54... Up-down counter, 56... Digital-to-analog converter, 57, 60... Bit pattern generator, 59
...Clock generator.

Claims (1)

[Claims] 1. Counting the period of a frequency signal proportional to the rotation speed of the motor 3 of the magnetic recording/reproducing device from an initial value N using a reference clock of a constant frequency supplied from the reference clock oscillation means 59. 1 clock counting means 53, and a second clock counting means ₅₁ that counts from an initial value N0 in parallel with the first clock counting means using a reference clock having the period of the frequency signal during single speed reproduction. and, with respect to the count result _N1 of the second clock counting means, if the value ( _N1 - _N0 ) counted in the period of the frequency signal is larger than a predetermined value Nm, the output digital value M is increased; (N ₁ −N ₀ ) is the predetermined value Nm
an output digital value M increase/decrease unit 54 that decreases the output digital value M when the output digital value M is smaller; a first data holding unit 57 that outputs the digital value L; an output digital value M of the increase/decrease unit 54; an addition means 58 for adding the digital value L of the data holding means 57, N=L+M, as the initial value N of the first clock counting means;
and stop means 67 for stopping the above-mentioned increase/decrease operation of the output digital value M of the output digital value increase/decrease means described above at times other than when playing at 1x speed; A switching means 65 for switching the value L, a second data holding means 55 for holding the count value of the first clock counting means, and a voltage converting means 56 for converting the output of the second data holding means into a voltage signal. A motor control circuit using a steady speed error correction device, comprising: and a motor drive means 8 which uses the output of the voltage conversion means as a drive voltage of the motor.