JPH0567957A - Semiconductor unit - Google Patents
Semiconductor unitInfo
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- JPH0567957A JPH0567957A JP3229082A JP22908291A JPH0567957A JP H0567957 A JPH0567957 A JP H0567957A JP 3229082 A JP3229082 A JP 3229082A JP 22908291 A JP22908291 A JP 22908291A JP H0567957 A JPH0567957 A JP H0567957A
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- Prior art keywords
- gate
- mos
- fet
- charge
- turned
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.
【０００２】[0002]
【従来の技術】従来の技術としては、例えば図５の回路
図に示すようなものがあり、以下図５に従って説明す
る。図５は正逆転できるモ−タ１０を駆動するためのＨ
ブリッジ型半導体装置を示す。その構成を説明すると、
ＭＯＳ ＦＥＴ１、２のドレインが共に電源のプラス端
子に接続され、ＭＯＳ ＦＥＴ８のドレインが前記ＭＯ
Ｓ ＦＥＴ１のソ−スに、ＭＯＳ ＦＥＴ９のドレイン
が前記ＭＯＳＦＥＴ２のソ−スにそれぞれ接続され、前
記ＭＯＳ ＦＥＴ８、９のソ−スは共に接地されてい
る。前記モ−タ１０は、前記ＭＯＳ ＦＥＴ１のソ−ス
と前記ＭＯＳ ＦＥＴ２のソ−スとの間に接続されてい
る。この場合、前記ＭＯＳ ＦＥＴ１、９がオン、且
つ、前記ＭＯＳ ＦＥＴ２、８がオフの時に、図中に示
されているＡの向きに電流がながれ、負荷である前記モ
−タ１０が正回転する。また、前記ＭＯＳ ＦＥＴ１、
９がオフ、且つ、前記ＭＯＳ ＦＥＴ２、８がオンの時
に、図中のＢの向きに電流がながれ、前記モ−タ１０が
逆回転する。2. Description of the Related Art As a conventional technique, for example, there is one shown in the circuit diagram of FIG. 5, which will be described below with reference to FIG. FIG. 5 shows H for driving the motor 10 capable of rotating in the forward and reverse directions.
1 shows a bridge-type semiconductor device. Explaining the configuration,
The drains of the MOS FETs 1 and 2 are both connected to the positive terminal of the power source, and the drain of the MOS FET 8 is the above-mentioned MO.
The drain of the MOS FET 9 is connected to the source of the S FET 1 and the source of the MOSFET 2, respectively, and the sources of the MOS FETs 8 and 9 are both grounded. The motor 10 is connected between the source of the MOS FET1 and the source of the MOS FET2. In this case, when the MOS FETs 1 and 9 are on and the MOS FETs 2 and 8 are off, a current flows in the direction of A shown in the figure, and the motor 10 as a load rotates forward. .. In addition, the MOS FET1,
When 9 is off and the MOS FETs 2 and 8 are on, a current flows in the direction of B in the figure, and the motor 10 rotates in the reverse direction.
【０００３】図６のグラフには、前記ＭＯＳ ＦＥＴ
１、２それぞれのゲ−ト電圧Ｖ１、Ｖ２の変化を時間の
関数として示してある。電荷Ｑ１の供給にともなってＶ
１が上昇し、Ｑ２の引き抜きにともなってＶ２が降下し
ている。尚、一方のＭＯＳ ＦＥＴをタ−ンオンすると
同時に他方のＭＯＳ ＦＥＴをタ−ンオフするような半
導体装置として、図５に示すＨブリッジ以外にも、例え
ば、インバ−タ回路や３相交流モ−タの駆動回路などが
ある。The graph of FIG. 6 shows the above-mentioned MOS FET.
The changes in the gate voltages V1 and V2 of the respective 1 and 2 are shown as a function of time. V with the supply of charge Q1
1 goes up, and V2 goes down as Q2 is pulled out. As a semiconductor device for turning on one MOS FET and turning off the other MOS FET at the same time, other than the H bridge shown in FIG. 5, for example, an inverter circuit or a three-phase AC motor can be used. Drive circuit.
【０００４】[0004]
【発明が解決しようとする課題】このような従来の半導
体装置においては、前記ＭＯＳ ＦＥＴ１をタ−ンオン
するための電荷Ｑ１の供給と、前記ＭＯＳ ＦＥＴ２を
タ−ンオフするための電荷Ｑ２の引き抜きを、別々に外
部回路によって行っていた。また、前記ＭＯＳＦＥＴ
１、２は前記モ−タ１０に電流を流すための電力用トラ
ンジスタなのでサイズが大きく、従って寄生容量も大き
いので、外部より充放電する前記電荷Ｑ１、Ｑ２が多
く、外部回路の駆動電力が大きい。しかも、図５中のｃ
点は、接地されているため電位０ボルトなので前記ＭＯ
Ｓ ＦＥＴ８、９をオンするために必要なゲ−ト、ソ−
ス間の電圧は、該ＭＯＳ ＦＥＴ８、９のしきい値電圧
でよい。しかし、前記ＭＯＳ ＦＥＴ１、２に関して
は、ソ−ス・ドレイン間の抵抗による電圧降下が非常に
小さいためｂ１、ｂ２点の電位はａ点の電位にほぼ等し
くなり、前記ＭＯＳ ＦＥＴ１をオンしておくために
は、しきい値電圧にさらに電源電圧を加えた電圧が必要
なので、外部回路と前記ＭＯＳ ＦＥＴ１のゲ−トとの
間には昇圧回路が必要になり、この昇圧回路による前記
ＭＯＳ ＦＥＴ９のスイッチング速度に対する相対的な
スイッチング速度の遅れ、外部回路の電力損失及び発熱
量が大きくなってしまうという問題点があった。In such a conventional semiconductor device, the supply of the charge Q1 for turning on the MOS FET1 and the extraction of the charge Q2 for turning off the MOS FET2 are performed. , Was done separately by an external circuit. Also, the MOSFET
Since 1 and 2 are power transistors for supplying a current to the motor 10, they are large in size and therefore have large parasitic capacitance, so that the charges Q1 and Q2 charged and discharged from the outside are large and the driving power of the external circuit is large. .. Moreover, c in FIG.
Since the point is grounded, the potential is 0 V
Gate and source required to turn on SFET8, 9
The voltage between cells may be the threshold voltage of the MOS FETs 8 and 9. However, regarding the MOS FETs 1 and 2, since the voltage drop due to the resistance between the source and the drain is very small, the potentials at the points b1 and b2 become substantially equal to the potential at the point a, and the MOS FET 1 is turned on. In order to achieve this, a voltage obtained by adding a power supply voltage to the threshold voltage is required. Therefore, a booster circuit is required between the external circuit and the gate of the MOS FET 1, and this booster circuit is used to boost the MOS FET 9. There is a problem that the switching speed is relatively delayed with respect to the switching speed, the power loss of the external circuit and the amount of heat generation increase.
【０００５】この発明は、前述した課題を解決すべくな
された物で、トランジスタをタ−ンオン、タ−ンオフす
るための外部回路の駆動電力、発熱を減少し、トランジ
スタのスイッチング速度を上昇させた半導体装置を提供
する事を目的としている。The present invention has been made in order to solve the above-mentioned problems, and reduces driving power and heat generation of an external circuit for turning on / off a transistor and increasing the switching speed of the transistor. The purpose is to provide a semiconductor device.
【０００６】[0006]
【課題を解決するための手段】かかる目的を達成するた
め、請求項１に記載された発明は、２個以上のトランジ
スタを有し、その中の一方のトランジスタＡをタ−ンオ
ンし、同時に、他方のトランジスタＢをタ−ンオフする
ように動作する半導体装置において、前記トランジスタ
Ａのゲ−トと前記トランジスタＢのゲ−トとの間に設け
られたゲ−ト短絡手段を有することを特徴とする半導体
装置を構成し、請求項２に記載された発明は、上記請求
項１の半導体装置のゲ−ト短絡手段を、ゲ−ト短絡用素
子と、電流逆流防止用素子とから構成した。In order to achieve the above object, the invention described in claim 1 has two or more transistors, one of which is turned on, and at the same time, A semiconductor device which operates so as to turn off the other transistor B has a gate short-circuit means provided between the gate of the transistor A and the gate of the transistor B. According to the invention described in claim 2, the gate short-circuit means of the semiconductor device according to claim 1 is composed of a gate short-circuit element and a current backflow prevention element.
【０００７】[0007]
【作用】請求項１に記載の発明においては、トランジス
タＡをタ−ンオンさせ、同時にトランジスタＢをタ−ン
オフさせようとするとき、ゲ−ト短絡手段によって、前
記トランジスタＡと前記トランジスタＢとのゲ−ト間を
短絡させ、該トランジスタＢのゲ−トの電荷の一部を前
記トランジスタＡのゲ−トへ移す。又、請求項２に記載
の発明においては、ゲ−ト短絡素子によって、該トラン
ジスタＡと前記トランジスタＢとのゲ−ト間を短絡さ
せ、該トランジスタＢのゲ−トの電荷の一部を前記トラ
ンジスタＡのゲ−トへ移す際に、外部より該トランジス
タＡのゲ−トへ供給される電荷が、前記ゲ−ト短絡手段
を通って前記トランジスタＢのゲ−トへ流れるのを、電
流逆流防止用素子が防止する。According to the first aspect of the present invention, when the transistor A is turned on and the transistor B is turned off at the same time, the gate short-circuiting means connects the transistor A and the transistor B together. The gates are short-circuited, and a part of the charge of the gate of the transistor B is transferred to the gate of the transistor A. Further, in the invention of claim 2, a gate short-circuit element is used to short-circuit between the gates of the transistor A and the transistor B, and a part of the charge of the gate of the transistor B is transferred to the gate. At the time of transferring to the gate of the transistor A, the electric charge supplied from the outside to the gate of the transistor A flows through the gate short-circuit means to the gate of the transistor B, so that the reverse current flows. Preventing element prevents.
【０００８】[0008]
【実施例】以下、図１の回路図に従って、この発明の第
１実施例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the circuit diagram of FIG.
【０００９】まず構成を説明する。２個以上のトランジ
スタの一方のトランジスタＡであるＭＯＳ ＦＥＴ１を
タ−ンオンし、同時に、他方のトランジスタＢであるＭ
ＯＳ ＦＥＴ２をタ−ンオフするように動作する半導体
装置において、ゲ−ト短絡手段が、ＭＯＳ ＦＥＴ１の
ゲ−トＡとＭＯＳ ＦＥＴ２のゲ−トＢとの間に設けら
れたゲ−ト短絡用素子であるゲ−ト短絡用のＭＯＳ Ｆ
ＥＴ３と、電流逆流防止用素子であるダイオ−ド４とか
らなる。First, the configuration will be described. One of the two or more transistors, which is one transistor A, is turned on, and at the same time, the other transistor, B, is turned on.
In a semiconductor device that operates to turn off the OS FET2, a gate short-circuit means is provided between the gate A of the MOS FET1 and the gate B of the MOS FET2. MOS F for gate short circuit
It is composed of ET3 and a diode 4 which is a current backflow prevention element.
【００１０】次にこの実施例の作用を説明する。例え
ば、今、前記ＭＯＳ ＦＥＴ１がオフ、前記ＭＯＳ Ｆ
ＥＴ２がオンしているとする。この状態では、前記ＭＯ
Ｓ ＦＥＴ３をオフにしておけば、前記ゲ−トＡ、前記
ゲ−トＢ間に干渉はない。この時、前記ＭＯＳ ＦＥＴ
１をタ−ンオンするには、外部より前記ゲ−トＡへ電荷
Ｑ１ａを供給し、同時に前記ＭＯＳＦＥＴ３をオンにす
る。また、同時に前記ＭＯＳ ＦＥＴ２をタ−ンオフす
るために、前記ゲ−トＢの電荷Ｑ２ａを外部へ引き抜く
ようにする。この時前記ＭＯＳ ＦＥＴ３によって、前
記ゲ−トＡと、該ゲ−トＡより電位の高い前記ゲ−トＢ
が短絡されるために、該ゲ−トＢの電荷の一部Ｑ２ｂが
前記ゲ−トＡへ移動する。ここで、前記ＭＯＳ ＦＥＴ
１をタ−ンオンするための電荷Ｑ１、前記ＭＯＳ ＦＥ
Ｔ２をタ−ンオフするための電荷Ｑ２と、Ｑ１ａ、Ｑ２
ａ、Ｑ２ｂとの関係は、 Ｑ１＝Ｑ１ａ＋Ｑ２ｂ、Ｑ２＝Ｑ２ａ＋Ｑ２ｂ となっている。今、前記ＭＯＳ ＦＥＴ１と前記ＭＯＳ
ＦＥＴ２のゲ−ト容量が等しいと仮定すると、理論
上、該ゲ−トＢの全電荷Ｑ２の半分が、前記ゲ−トＡへ
移動する。また、前記ＭＯＳ ＦＥＴ３は、前記ＭＯＳ
ＦＥＴ２のゲ−ト電荷の一部を移動させるだけなの
で、前記ＭＯＳ ＦＥＴ１、前記ＭＯＳ ＦＥＴ２に比
べて容量の小さい、すなわち、消費電力の少ないもので
良い。Next, the operation of this embodiment will be described. For example, when the MOS FET1 is off and the MOS F is
Assume that ET2 is on. In this state, the MO
If the SFET3 is turned off, there is no interference between the gate A and the gate B. At this time, the MOS FET
To turn on 1, the charge Q1a is externally supplied to the gate A, and at the same time, the MOSFET 3 is turned on. At the same time, in order to turn off the MOS FET 2, the charge Q2a of the gate B is extracted to the outside. At this time, the gate A and the gate B having a higher potential than the gate A are generated by the MOS FET 3.
Is short-circuited, a part of the charge Q2b of the gate B moves to the gate A. Here, the MOS FET
Charge Q1 for turning on 1 and the MOS FE
Charge Q2 for turning off T2 and Q1a, Q2
The relationship between a and Q2b is: Q1 = Q1a + Q2b, Q2 = Q2a + Q2b. Now, the MOS FET1 and the MOS
Assuming that the gate capacitances of the FET2 are equal, theoretically, half of the total charge Q2 of the gate B moves to the gate A. Further, the MOS FET3 is the MOS
Since only a part of the gate charge of the FET 2 is moved, the capacity of the FET 2 may be smaller than that of the MOS FET 1 and the MOS FET 2, that is, the power consumption may be small.
【００１１】尚、前記ＭＯＳ ＦＥＴ１のゲ−トへの電
荷供給及び前記ＭＯＳ ＦＥＴ２のゲ−トからの電荷引
き抜きの直前にＭＯＳ ＦＥＴ３をオンさせたほうが、
本発明の効果はより高くなる。It should be noted that it is better to turn on the MOS FET 3 immediately before the charge is supplied to the gate of the MOS FET 1 and the charge is extracted from the gate of the MOS FET 2.
The effect of the present invention becomes higher.
【００１２】以上の電荷の移動によって前記ゲ−トＡの
電圧が急激に上昇し、同時に前記ゲ−トＢの電圧が急激
に降下する。その後もＱ１ａの供給によって、前記ゲ−
トＡの電圧がさらに上昇し、Ｑ２ａの引き抜きによっ
て、前記ゲ−トＢの電圧がさらに降下する。この時、前
記ダイオ−ド４によって、前記ゲ−トＡの電荷が前記Ｍ
ＯＳ ＦＥＴ３を通って前記ゲ−トＢへ流れる事が防止
される。Due to the above-mentioned movement of charges, the voltage of the gate A sharply rises, and at the same time, the voltage of the gate B sharply drops. After that, by supplying Q1a,
The voltage of the gate A further increases, and the voltage of the gate B further decreases due to the extraction of Q2a. At this time, the charge of the gate A is transferred to the M by the diode 4.
Flow to the gate B through the OS FET 3 is prevented.
【００１３】図２のグラフに前記ゲ−トＡの電圧Ｖ１ａ
と前記ゲ−トＢの電圧Ｖ２ｂの時間変化を示す。前記電
圧Ｖ１ａの時間変化を、点線に示す従来の場合と比較す
ると、前記ゲ−トＡへ、外部からＱ１ａ、前記ＭＯＳ
ＦＥＴ３を通ってＱ２ｂが供給されるため、従来よりも
Ｖ１ａの上昇が速く、同様に、前記電圧Ｖ２ｂの場合も
従来より速く降下する。The voltage V1a of the gate A is shown in the graph of FIG.
And the time variation of the voltage V2b of the gate B. Comparing the time change of the voltage V1a with the conventional case shown by the dotted line, the gate A is externally connected to Q1a, the MOS
Since Q2b is supplied through the FET3, V1a rises faster than before, and similarly, the voltage V2b also drops faster than before.
【００１４】以上の作用の説明より、外部から供給され
る電荷Ｑ１ａ及び、外部へ引き抜かれる電荷Ｑ２ａを従
来の場合より少なくできる。そのため、外部回路におけ
る駆動電力が小さくなり、発熱量も少なくなる。From the above description of the operation, the electric charge Q1a supplied from the outside and the electric charge Q2a drawn to the outside can be made smaller than in the conventional case. Therefore, the driving power in the external circuit is reduced and the amount of heat generation is also reduced.
【００１５】また、前記ゲ−トＡの充電時間及び前記ゲ
−トＢの放電時間を短くでき、前記ＭＯＳ ＦＥＴ１、
前記ＭＯＳ ＦＥＴ２のスイッチング時間を短くでき
る。Further, the charging time of the gate A and the discharging time of the gate B can be shortened, and the MOS FET1,
The switching time of the MOS FET 2 can be shortened.
【００１６】次に図３の回路図に従って、この発明の第
２実施例を説明する。尚、第１実施例と同一の部分は、
同一の符号を付し、その説明を省略する。この実施例
は、第１実施例に示した、前記ＭＯＳ ＦＥＴ１をタ−
ンオンするための短絡手段（前記ＭＯＳ ＦＥＴ３と前
記ダイオ−ド４）の他に、前記ＭＯＳ ＦＥＴ２をタ−
ンオンするための短絡手段（ＭＯＳ ＦＥＴ５とダイオ
−ド６）も備えている。ＭＯＳ ＦＥＴ５、該ダイオ−
ド６は、前記ＭＯＳ ＦＥＴ３、前記ダイオ−ド４と、
逆向き、並列に接続されている。Next, a second embodiment of the present invention will be described with reference to the circuit diagram of FIG. The same parts as in the first embodiment are
The same reference numerals are given and the description thereof is omitted. This embodiment is a modification of the MOS FET 1 shown in the first embodiment.
In addition to the short-circuiting means for turning on (the MOS FET 3 and the diode 4), the MOS FET 2 is turned on.
It also has a short-circuit means (MOS FET 5 and diode 6) for turning on. MOS FET5, the diode
The gate 6 includes the MOS FET 3, the diode 4,
Reversed, connected in parallel.
【００１７】前記ＭＯＳ ＦＥＴ１をタ−ンオフし、前
記ＭＯＳ ＦＥＴ２をタ−ンオンする際には、前記ＭＯ
Ｓ ＦＥＴ５をオンにし、前記ゲ−トＡの電荷を前記ゲ
−トＢへ移す。その結果、第１実施例の効果に加えて更
に、前記ＭＯＳ ＦＥＴ２をタ−ンオンするときにも、
第１実施例で説明した前記ＭＯＳ ＦＥＴ１をタ−ンオ
ンするときと同じ効果を得ることが出来る。When turning off the MOS FET1 and turning on the MOS FET2, the MO
The SFET 5 is turned on, and the electric charge of the gate A is transferred to the gate B. As a result, in addition to the effects of the first embodiment, when turning on the MOS FET 2,
The same effect as when turning on the MOS FET 1 described in the first embodiment can be obtained.
【００１８】次に図４の回路図に従ってこの発明の第３
実施例を説明する。尚、第１実施例と同一の部分は同一
の符号を付し、その説明は省略する。この図４には、前
記ＭＯＳ ＦＥＴ３の制御回路の例を示している。前記
ゲ−トＡと前記ＭＯＳ ＦＥＴ３のゲ−トＣが入力抵抗
７を介して接続されていて、該ＭＯＳ ＦＥＴ３のソ−
スは、前記ゲ−トＡと同電位に接続されている。また、
前記ＭＯＳＦＥＴ１と前記ＭＯＳ ＦＥＴ２のソ−スは
共に接地されている。Next, the third embodiment of the present invention will be described with reference to the circuit diagram of FIG.
An example will be described. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. FIG. 4 shows an example of the control circuit of the MOS FET 3. The gate A and the gate C of the MOS FET 3 are connected via an input resistor 7, and the source of the MOS FET 3 is connected.
The gate is connected to the same potential as the gate A. Also,
The sources of the MOSFET 1 and the MOS FET 2 are both grounded.
【００１９】次にこの実施例の作用を説明する。前記入
力抵抗７によって、前記ＭＯＳ ＦＥＴ３のゲ−トＣの
電位が前記ゲ−トＡの電位つまり前記ＭＯＳ ＦＥＴ３
のソ−ス電位より高くなるので、前記入力抵抗７を介し
て電圧を印加することにより、該ゲ−トＡへ電荷供給す
れば、前記ＭＯＳ ＦＥＴ３を自動的にタ−ンオンする
ことが出来る。この実施例の場合、第１実施例の効果に
加えて更に、前記ＭＯＳ ＦＥＴ３のゲ−トＣに電圧を
印加するための外部端子を減らすことが出来るという効
果がある。Next, the operation of this embodiment will be described. By the input resistor 7, the potential of the gate C of the MOS FET 3 is the potential of the gate A, that is, the MOS FET 3
Since it becomes higher than the source potential of the MOS FET 3, if a charge is supplied to the gate A by applying a voltage via the input resistor 7, the MOS FET 3 can be automatically turned on. In the case of this embodiment, in addition to the effect of the first embodiment, there is an effect that the number of external terminals for applying a voltage to the gate C of the MOS FET 3 can be reduced.
【００２０】尚、以上説明してきた実施例の前記ゲ−ト
Ａ、前記ゲ−トＢの短絡手段として、Ｎ型ＭＯＳ ＦＥ
Ｔが用いられてきたが、この発明においてはこれに限る
ことなく、Ｐ型ＭＯＳ ＦＥＴ、トランスファ−・ゲ−
ト、ＮＰＮバイポ−ラトランジスタやＰＮＰバイポ−ラ
トランジスタなどを用いることも可能である。以上説明
してきた実施例では、電流逆流防止のためにダイオ−ド
４が用いられているが、例えば、ゲ−ト短絡用ＭＯＳ
ＦＥＴをオンにしてから、一定時間後にオフするように
制御すると、電流逆流防止用のダイオ−ド４を取り付け
なくてもすむ。次に、本発明を図５に示すＨブリッジに
使用した場合の問題点と、その解決法を説明する。一般
的に、Ｈブリッジに用いられるＭＯＳ ＦＥＴはしきい
値を低く設定してオン抵抗を下げている。従って、前記
ＭＯＳ ＦＥＴ２のゲ−ト電荷の一部が前記ＭＯＳ Ｆ
ＥＴ１へ移動すると、該ＭＯＳ ＦＥＴ１はすぐにタ−
ンオンするが、前記ＭＯＳ ＦＥＴ２がまだタ−ンオフ
していないという瞬間がある。すなわち、前記ＭＯＳ
ＦＥＴ１、前記ＭＯＳ ＦＥＴ２の両方ともオンになる
時間が存在するのである。この間に電流が、前記ＭＯＳ
ＦＥＴ１と前記ＭＯＳ ＦＥＴ８、または前記ＭＯＳ
ＦＥＴ２と前記ＭＯＳ ＦＥＴ９を通って流れると、
電源の短絡ということになり、大電流が回路内を流れる
ことになるので、素子破壊が起きてしまうという問題が
ある。その解決法としては、前記ＭＯＳ ＦＥＴ８と前
記ＭＯＳ ＦＥＴ９を一旦タ−ンオフしてから、前記Ｍ
ＯＳＦＥＴ１と前記ＭＯＳ ＦＥＴ２の電荷移動を始め
て、前記ＭＯＳ ＦＥＴ１、前記ＭＯＳ ＦＥＴ２の一
方がオフになってから、前記ＭＯＳ ＦＥＴ８または前
記ＭＯＳ ＦＥＴ９をタ−ンオンするという方法があ
る。An N-type MOS FE is used as a means for short-circuiting the gate A and the gate B in the embodiment described above.
Although T has been used, the present invention is not limited to this, and P-type MOS FET, transfer gate
It is also possible to use an NPN bipolar transistor, a PNP bipolar transistor, or the like. In the embodiment described above, the diode 4 is used to prevent current backflow. For example, a gate shorting MOS is used.
If the FET is turned on and then turned off after a certain period of time, it is not necessary to attach the diode 4 for preventing current backflow. Next, problems and their solutions when the present invention is used in the H bridge shown in FIG. 5 will be described. Generally, the MOS FET used for the H-bridge has a low threshold value to reduce the on-resistance. Therefore, a part of the gate charge of the MOS FET2 is not included in the MOS F2.
When moving to ET1, the MOS FET1 is immediately turned on.
It turns on, but there is a moment when the MOS FET 2 is not yet turned off. That is, the MOS
There is a time when both the FET1 and the MOS FET2 are turned on. During this time, the current is
FET1 and the MOS FET8, or the MOS
When flowing through the FET2 and the MOS FET9,
This is a short circuit of the power supply, and a large current flows in the circuit, which causes a problem that element destruction occurs. The solution is to turn off the MOS FET 8 and the MOS FET 9 once, then
There is a method in which charge transfer between the OSFET1 and the MOS FET2 is started and one of the MOS FET1 and the MOS FET2 is turned off, and then the MOS FET8 or the MOS FET9 is turned on.
【００２１】[0021]
【発明の効果】以上説明してきたように、この発明によ
ればゲ−ト電荷を有効に利用でき、外部回路の駆動電力
及び発熱を減少、トランジスタのスイッチング速度を上
昇させる事ができるという効果が得られる。As described above, according to the present invention, the gate charge can be effectively used, the driving power and heat generation of the external circuit can be reduced, and the switching speed of the transistor can be increased. can get.
【図１】第１実施例の回路図FIG. 1 is a circuit diagram of a first embodiment.
【図２】第１実施例のＭＯＳ ＦＥＴ１、ＭＯＳ ＦＥ
Ｔ２のゲ−ト電圧変化を示す時間−電圧グラフFIG. 2 is a MOS FET1 and a MOS FE of the first embodiment.
Time-voltage graph showing the gate voltage change of T2
【図３】第２実施例の回路図FIG. 3 is a circuit diagram of a second embodiment.
【図４】第３実施例の回路図FIG. 4 is a circuit diagram of a third embodiment.
【図５】従来例の回路図FIG. 5 is a circuit diagram of a conventional example.
【図６】従来例のＭＯＳ ＦＥＴ８，ＭＯＳ ＦＥＴ９
のゲ−ト電圧変化を示す時間−電圧グラフFIG. 6 MOS FET8, MOS FET9 of a conventional example
Time-voltage graph showing the change in gate voltage
１…ＭＯＳ ＦＥＴ ２…ＭＯＳ ＦＥＴ ３…ゲ−ト短絡用ＭＯＳ ＦＥＴ ４…電流逆流防止用ダイオ−ド ５…ゲ−トＡ ６…ゲ−トＢ ７…ゲ−ト短絡用トランジスタ ８…電流逆流防止用ダイオ−ド ９…ゲ−トＣ １０…入力抵抗 １１…ＭＯＳ ＦＥＴ １２…ＭＯＳ ＦＥＴ １３…モ−タ DESCRIPTION OF SYMBOLS 1 ... MOS FET 2 ... MOS FET 3 ... Gate short circuit MOS FET 4 ... Current reverse current prevention diode 5 ... Gate A 6 ... Gate B 7 ... Gate short circuit transistor 8 ... Current reverse current Prevention diode 9 ... Gate C 10 ... Input resistance 11 ... MOS FET 12 ... MOS FET 13 ... Motor
Claims (2)
一方のトランジスタＡをタ−ンオンし、同時に、他方の
トランジスタＢをタ−ンオフするように動作する半導体
装置において、前記トランジスタＡのゲ−トと前記トラ
ンジスタＢのゲ−トとの間にゲ−ト短絡手段を設けたこ
とを特徴とする半導体装置。1. A semiconductor device comprising two or more transistors, one of which is turned on and the other of which is turned off at the same time. A semiconductor device comprising a gate short-circuit means provided between the gate and the gate of the transistor B.
と、電流逆流防止用素子から構成されていることを特徴
とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the gate short-circuit means comprises a gate short-circuit element and a current backflow prevention element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3229082A JPH0567957A (en) | 1991-09-09 | 1991-09-09 | Semiconductor unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3229082A JPH0567957A (en) | 1991-09-09 | 1991-09-09 | Semiconductor unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0567957A true JPH0567957A (en) | 1993-03-19 |
Family
ID=16886471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3229082A Pending JPH0567957A (en) | 1991-09-09 | 1991-09-09 | Semiconductor unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0567957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012169272A1 (en) * | 2011-06-06 | 2012-12-13 | 住友電気工業株式会社 | Switching circuit |
-
1991
- 1991-09-09 JP JP3229082A patent/JPH0567957A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012169272A1 (en) * | 2011-06-06 | 2012-12-13 | 住友電気工業株式会社 | Switching circuit |
| JP2012253664A (en) * | 2011-06-06 | 2012-12-20 | Sumitomo Electric Ind Ltd | Switching circuit |
| US8766699B2 (en) | 2011-06-06 | 2014-07-01 | Sumitomo Electric Industries, Ltd. | Switching circuit |
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