JPH0567793A - Semiconductor device - Google Patents

Abstract

PURPOSE:To test transient change of a size of consumption current during operation of an inside circuit in a short time by measuring change of a size of consumption current as change of output electric potential from a specified outside terminal of a semiconductor device. CONSTITUTION:In addition to a circuit part 54 constituting a conventional flash EEPROM, a transient current detecting circuit 500 for detecting change of current flowing inside the circuit part 54 and outside terminals TIP and TIM are further provided. When a high electric potential is applied from an outside to the outside terminal TIP and a transistor 65 is turned ON, a comparison circuit 51 functions as a differential amplifier to two input voltages VPP, VINTPP. If a high voltage VPP from an outside is higher than an inside current voltage VINTPP, a transistor 64 is turned ON which is deeper than a transistor 63. Since a transistor 62 is turned OFF due to potential rise of a node N2, a current is not supplied from the output terminal TIP to the node N1. As a result, electric potential of the node N1 lowers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a circuit for measuring a change in current consumption during operation.

[0002]

2. Description of the Related Art Semiconductor memory devices include volatile memories such as DRAM (dynamic random access memory) and SRAM (static random access memory), and non-volatile memories. All data stored in the volatile memory is lost when the power is turned off. However, the data stored in the non-volatile memory does not disappear even when the power is turned off.

As such a non-volatile semiconductor memory device, the user can write information and electrically erase the written information to rewrite the information as many times as desired.
PROM (electrically erasable)
e and programmable Read O
There is a nly Memory). EEPROM capable of collectively erasing data stored in all memory cells or data stored in memory cells in one block
M is called a flash EEPROM.

FIG. 3 shows "IEEE Journal o".
f Solid-State Circuits, vo
l. 23, no. 5, October 1988 pp.
1157 to 1163 "of conventional flash EE
It is a schematic block diagram which shows the whole structure of PROM. Figure 4
FIG. 4 is a sectional view showing a structure of a memory cell in a flash EEPROM. FIG. 5 is a circuit diagram showing the configurations of the memory cell array 1 and the Y gate 2.

The structure and operation of the conventional flash EEPROM will be described below with reference to FIGS.

The memory cell array 1 includes a plurality of memory cells MC arranged in a matrix in the row and column directions. FIG. 5 illustrates a case where the memory cell array 1 includes nine memory cells MC arranged in a matrix of 3 rows × 3 columns.

In each memory cell MC, as shown in FIG. 4, a FAMOS (floating gate aval) capable of storing charges in a floating gate.
an injection injection MOS) transistor is used. In FIG. 5, each memory cell MC is represented by a transistor symbol.

The FAMOS transistor includes a control gate 17, a floating gate 16, N-type regions 18 and 19 respectively formed as a source and a drain on a P-type substrate 15, and an insulating layer 20.

The floating gate 16 is a P-type substrate 1.
5 over the N-type regions 18 and 19,
It is formed via the insulating layer 20.

The control gate 17 is formed on the floating gate 16 via an insulating layer 20.

The control gate 17 and the floating gate 16 are both made of polysilicon.

The insulating layer 20 is formed of an oxide film such as SiO ₂ . The thickness of the oxide film 20 between the P-type substrate 15 and the floating gate 16 is usually about 100Å, which is very thin.

On the other hand, the thickness of the oxide film 20 between the floating gate 16 and the control gate 17 is usually 20.
It is about 0 Å, which is thicker than the thickness of the oxide film between the floating gate 16 and the P-type substrate 15.

As shown in FIG. 5, in memory cell array 1, one word line WL1 to WL3 and one bit line BL1 to BL3 are provided corresponding to each memory cell row and each memory cell column. Be done.

The control gates 17 of the FAMOS transistors forming each memory cell row are commonly connected to one corresponding word line. The drains 19 of the FAMOS transistors forming each memory cell column are commonly connected to one corresponding bit line. Source 18 of FAMOS transistor that constitutes all memory cells MC
Are commonly connected to one source line 28.

At the time of data writing, referring to FIG. 4, control gate 17 and drain 19 are supplied with 12 V and 6.
A high potential of 5V is applied, while the source 18 is grounded via the source line 28.

Control gate 17 and source 18
This transistor is turned on by the voltage applied between them, and a channel current flows between the source 18 and the drain 19. At this time, electron (hot electron) -hole pairs are generated near the drain 19 by impact ionization. The holes flow toward the grounded substrate 15. Most of the electrons flow into the high potential drain 19. But,
Since a high potential is applied to the control gate 17, some of the electrons are accelerated by the electric field between the floating gate 16 and the drain 19, pass through the insulating film 20 between the floating gate 16 and the substrate 15, and pass through the floating gate. Injected into 16.

Since floating gate 16 is electrically insulated from control gate 17, source 18, and drain 19 by oxide film 20, electrons injected into floating gate 210 do not flow out. Therefore, the electrons once injected into the floating gate 16 do not flow out of the floating gate 16 for a long time and are accumulated even after the power is turned off.

A state in which electrons are stored in the floating gate 16 and a state in which no electrons are stored in the floating gate 16 correspond to data "0" and "1", respectively.

Therefore, the data stored in the memory cell MC is retained even after the power is turned off. Now, when electrons are accumulated in the floating gate 16, the polarity of the source region 18 and the drain region 19, that is, the channel region, shifts in the positive direction due to the electric field from the accumulated electrons. Therefore, the inversion layer is less likely to occur in the channel region. Therefore, when electrons are accumulated in the floating gate 16, the voltage applied to the control gate 17 (that is, the threshold voltage of the transistor) required to flow a channel current in the transistor becomes the electrons in the floating gate 16. Higher than if not accumulated.
That is, this transistor is not turned on unless a higher voltage is applied to the control gate 17 than when electrons are not accumulated in the floating gate 16.

In the case of erasing stored data, in FIG. 4, a high potential of 12 V is applied to the source 18 via the source line 28, while the control gate 17 is grounded via the corresponding word line. The drain 19 is in a floating state.

The high potential applied to the control gate 17 causes a tunneling phenomenon, and the electrons in the floating gate 16 are extracted to the source 18 through the oxide film 20.

Therefore, the electrons injected into floating gate 16 at the time of data writing are removed from floating gate 16. As a result, the threshold voltage of this transistor is lowered.

At the time of data reading, in FIG. 5, the control gate 17 is supplied with a normal power supply potential V _CC (= 5V) which is a high level potential via the corresponding word line, and the source 18 supplies the source line 28. Grounded through.

If no electrons are stored in the floating gate 16, the threshold voltage of this transistor is low, so that a channel current flows between the source 18 and the drain 19 due to the power supply potential of 5 V applied to the control gate 17. However, if electrons are accumulated in the floating gate 16, the threshold voltage of this transistor is high, so that the control gate 17 receives the power supply potential 5
A channel current does not flow between the source 18 and the drain 19 even when V is applied.

Therefore, the transistors constituting the memory cell whose stored data is "1" are O-during data reading.
The current flows from the corresponding bit line to the source line 28 since it becomes N. However, since the transistor forming the memory cell in which the stored data is “0” is in the OFF state at the time of data reading, no current flows from the corresponding bit line to the source line 28.

Therefore, at the time of data reading, the sense amplifier detects whether or not a current flows through the bit line corresponding to the memory cell from which data is to be read. If a current flows through the bit line, it is determined that the stored data is "1", and if no current flows through the bit line, the stored data is determined as "0".

Specific circuit operations during data writing, data erasing, and data reading will be described below with reference to FIG.

First, the circuit operation during data writing will be described. The X decoder 4 selectively applies a high potential V _{PP of} 12 V to any one of the word lines WL1 to WL3 in the memory cell array 1.

The Y gate 2 serves as a transfer gate between the input / output line 27 connected to the write circuit 7 and the sense amplifier 8 and each of the bit lines BL1 to BL3 in the memory cell array 1. And an N channel MOS transistor 26 provided. Transistor 2
The respective gates of 6 are connected to the Y decoder 5 via different connection lines Y1 to Y3. That is, the connection lines Y1 to Y
3 are provided so as to have a one-to-one correspondence with the bit lines BL1 to BL3.

The Y decoder 5 selectively sets only one of the connection lines Y1 to Y3 to a high level in order to turn on only one of the transistors 26 in the Y gate 2. The potential of is applied. As a result, of the bit lines BL1 to BL3 in the memory cell array 1,
Only one of the connection lines (any of Y1 to Y3) to which a high-level potential is applied is electrically connected to the input / output line 27.

Write circuit 7 is activated in accordance with the data supplied from input / output buffer 9 of FIG.
A high voltage V _PP is applied to 7. Since the input / output line 27 is electrically connected to only one bit line (one of BL1 to BL3), the high voltage V _PP applied from the write circuit 7 to the input / output line 27 is It is applied to only one bit line.

The source line switch 3 applies the ground potential, which is a low level potential, to the source line 28.

Input / output buffer 9 amplifies a data signal externally applied to input / output terminals VO0 to VO7 and applies it to write circuit 7 during data writing.

As a result of such circuit operation, a high potential is applied to both the control gate 17 and the drain 19 in only one memory cell in the memory cell array 1. Therefore, hot electrons are generated and injected into the floating gate 16 only in this one memory cell. That is, this one memory cell M
Data “0” is written in C.

Therefore, for example, if the X decoder 4 applies the high voltage V _PP to the word line WL1, the Y decoder 5 applies the high level potential to the connection line Y1, and the write circuit 7 is activated. Data "0" is written in the memory cell MC surrounded by the dotted line in the figure.

If the data supplied from the input / output buffer 9 of FIG. 3 to the writing circuit 7 is "1", the writing circuit 7
Is not activated. Therefore, in such a case,
1 to which a high-level potential is applied by the Y decoder 5
One bit line (any one of BL1 to BL3) corresponding to one connection line (any one of Y1 to Y3) does not have a high potential. Therefore, with this one bit line,
Injecting into the floating gate 16 in one memory cell MC in which the drain 19 and the control gate 17 are connected to one word line (one of WL1 to WL3) to which the high voltage V _PP is applied by the X decoder 4. Hot electrons that can be generated do not occur. Therefore, the storage data of this memory cell MC remains "1".

Thus, at the time of data writing, one word line and one bit line are selected by X decoder 4 and Y decoder 5, respectively, and write circuit 7 is also selected.
By applying a high potential to the selected bit line according to the data from the input / output buffer 9, external data is written in one memory cell MC.

Next, the circuit operation at the time of erasing data will be described. The X decoder 4 is inactivated and all the word lines WL1 to WL3 in the memory cell array 1 become the ground potential V _SS . As a result, all memory cells M
The control gate 17 of C becomes the ground potential.

Similarly, the Y decoder 5 is also deactivated,
The potentials of the connection lines Y1 to Y3 connected to all the transistors 26 in the Y gate 2 become low level.
This ensures that all transistors 2 in Y-gate 2
Since 6 is in the OFF state, the drains 19 of all the memory cells MC are in the floating state.

The source line switch 3 applies a high voltage V _PP to the source line 28. By such circuit operation, in all the memory cells MC, a high electric field with the source 18 on the high potential side is generated between the floating gate 16 and the source 18, and a tunnel phenomenon occurs. Therefore, the floating gate 1 in all memory cells MC
Electrons flow out from 6. That is, the memory cell array 1
The stored data in all the memory cells MC in the memory cell are erased collectively.

Next, the circuit operation during data writing will be described. The X decoder 4 sets only one of the word lines WL1 to WL3 in the memory cell array 1 to a high level and sets the other word lines to a low level. As a result, 5V is applied to the control gates 17 of all the memory cells connected to this one word line.
Is applied.

The Y decoder 5 applies a high level potential to only one control gate 17 of the transistors 26 in the Y gate 2. As a result, one bit line (BL
Only any one of 1 to BL3) is electrically connected to the sense amplifier 8 via the input / output line 27.

The source line switch 3 sets the source line 28 to the ground potential V _SS as in the data writing.

By such circuit operation, the drain 19 and the control gate 17 are respectively connected to one transistor 26 turned on by the Y decoder 5 and one word line to which a high level potential is applied by the X decoder 4. The storage data of one connected memory cell MC is read by the sense amplifier 8.

For example, the connection line Y1 and the word line WL
It is assumed that a high level potential is applied to 1. In such a case, the presence / absence of a current flowing through the bit line BL1 electrically connected to the input / output line 27 is determined by the stored data in the memory cell MC surrounded by the dotted line in the drawing.

That is, since the threshold voltage of the memory cell whose stored data is "1" is higher than the low level potential, the word lines WL2, WL3 at the low level potential are set.
The memory cell whose control gate is connected to is in the OFF state regardless of the stored data. In contrast,
The high-level potential is higher than the threshold voltage of the memory cell whose storage data is "1" and lower than the threshold voltage of the memory cell whose storage data is "0". Therefore, whether the memory cell whose control gate is connected to the word line WL1 at the high level potential is in the ON state or the OFF state is determined by the stored data of this memory cell.

Therefore, the memory cell M surrounded by the dotted line
If the data stored in C is "0", this memory cell MC
Is in the OFF state, the input / output line 27 is connected to the connection line Y.
Transistor 26 whose gate is connected to 1, bit line B
Source line 28 via L1 and this memory cell MC
There is no current flowing through. However, this memory cell MC
If the storage data of the memory cell is "1", the memory cell MC is turned on, so that the transistor 26 whose gate is connected to the connection line Y1 from the input / output line 27 and the bit line BL
A current flows through the source line 28 via the memory cell MC1 and the memory cell MC1.

When a current flows from the bit line electrically connected to the input / output line 27 to the source line 28, the potential of the input / output line 27 decreases, but the bit line electrically connected to the input / output line 27. If no current flows from the source line 28 to the source line 28, the potential of the input / output line 27 does not decrease. The sense amplifier 8 detects the presence or absence of current flowing in the bit line electrically connected to the input / output line 27 by detecting such potential change of the input / output line 27.

If no current flows through the bit line electrically connected to the input / output line 27, the sense amplifier 8 gives a voltage signal corresponding to data "0" to the input / output buffer 9 of FIG. When a current flows through the bit line electrically connected to the input / output line 27, the sense amplifier 8 gives a voltage signal corresponding to the data “1” to the input / output buffer 9 in FIG.

Input / output buffer 9 supplies the data signal applied from sense amplifier 8 to input / output terminals VO0-VO7 during data reading.

Next, the overall circuit operation of the flash EEPROM will be described with reference to FIG. 3 and FIGS. 6 to 9.

FIG. 6 shows a flash E for erasing data.
FIG. 7 is an operation flow chart showing a circuit operation flow of the entire EPROM.

FIG. 7 shows a flash E for writing data.
FIG. 7 is an operation flow chart showing a circuit operation flow of the entire EPROM.

FIG. 8 is a timing chart showing changes in input / output signals of the flash EEPROM during data writing.

FIG. 9 is a timing chart showing changes in input / output signals of the flash EEPROM at the time of erasing data.

In the following description, a negatively active signal is indicated by a / in front of the symbol indicating it.

In the flash EEPROM, programming and erasing modes are set by a combination of input control signals. That is, the mode setting is performed by the rising data of the write enable signal / WE.

In writing, first, normal drive voltage V _CC (FIG. 8 (f)) and high voltage V _PP (FIG. 8) are used.
(G)) is raised to its original value. (Step S1 in FIG. 7) Next, the write enable signal / WE (FIG. 8 (d))
Is lowered. (Step S2 in FIG. 7) Then, in synchronization with the rise of the write enable signal / WE, the data signal 40 externally applied to the input / output terminals VO0 to VO7.
_H (FIG. 8E) is latched in the command register 12 via the input / output buffer 9. (Step S2 in FIG. 7)
Next, this data signal is decoded by the command decoder 13, and the operation mode of this flash EEPROM is set to the program mode for data writing. (Step S2 of FIG. 7) Next, the write enable signal / WE is fallen again, and the address register 6 (FIG. 8A) externally latched in the address register 6.
Further, in response to the rising of the write enable signal / WE, the data signal D _IN (FIG. 8E) externally applied to the input / output terminals VO0 to VO7 is transferred via the input / output buffer 9 to the write circuit 7 Latched on. (Step S3 in FIG. 7)
After that, a high voltage V _PP pulse is generated from the program voltage generation circuit 10 and supplied to the X decoder 4 and the Y decoder 5. The Y decoder 5 connects this high-voltage pulse to one bit line of the transistor 26 in the Y gate 2 provided corresponding to the memory cell column indicated by the address signal latched in the address register 6. It is given only to the gate of one transistor. The X-decoder 4 is provided with this high-voltage pulse 1 corresponding to the memory cell row indicated by the address signal latched in the address register 6.
Give only to the word line of the book. As a result, the data latched in the write circuit 7 is written only in one memory cell MC in the memory cell array 1 according to the principle described above. (Step S4 in FIG. 7) Next, the write enable signal / WE is lowered, and the data signal CO _H (FIG. 8 (e)) externally applied to the input / output terminals VO0 to VO7 is latched in the command register 12. To be done. Then, in synchronization with the rising of the write enable signal / WE, a program verify mode for inspecting whether data has been correctly written is set. (Step S5 in FIG. 7) At this time, the verify voltage generation circuit 11 applies a voltage of about 6.5 V, which is higher than the voltage of 5 V applied to the control gate of the memory cell MC during normal data read, from the high voltage V _PP. , Generated as a so-called program verify voltage, and applied to the X decoder 4 and the Y decoder 5.

The X decoder 4 supplies this program verify voltage to one word line provided corresponding to the memory cell row indicated by the address signal latched in the address register 6. Similarly, the Y decoder 5 connects the program verify voltage to the one bit line provided corresponding to the memory cell column indicated by the address signal latched in the address register 6 in the Y gate 2. Supply to the gate of one transistor 26. As a result, the stored data of one memory cell MC commonly connected to the memory cell row and the memory cell column indicated by the address signal latched in the address register 6 is read by the sense amplifier 8 according to the above-described principle. To be done. (Step S6 in FIG. 7) However, since the control gate of the memory cell to which data is to be read is applied with a higher potential than that during normal reading, data "0" is written in this memory cell. However, if the threshold voltage is not sufficiently high, this memory cell is turned on, so that the data "1" is read by the sense amplifier 8. That is, in order to facilitate detection of so-called write failure, electrons are not sufficiently injected into the floating gate of the memory cell at the time of writing data “0”, and the threshold voltage of this memory cell does not shift sufficiently high. In addition, the verify voltage generation circuit 11 generates such a program verify voltage.

Next, if the data read by the sense amplifier 8 (FIG. 8 (e)) does not match the data latched in the write circuit 7, steps S2 to S in FIG.
The circuit operation of 7 is repeated again, and the data is written in the same memory cell as before. If the data read by the sense amplifier 8 matches the data latched in the write circuit 7, it can be determined that the data has been correctly written. Therefore, the command decoder 13 uses the flash EE.
The PROM is set to the read mode in which the circuit operation for normal data read can be executed. (Step S8 in FIG. 7)
As described above, in the EEPROM, the floating gate 1 is applied by applying a high voltage between the control gate 17 and the source 18 of the memory cell at the time of erasing data.
Data erasure is accomplished by forcing a bend in the energy band between 6 and source 18 so that electrons tunnel from floating gate 16 to source 18.

Therefore, the amount of electrons extracted from the floating gate 16 depends on the magnitude of the high voltage applied to the source line 28, the time for which the high voltage is applied, and the oxide film interposed between the floating gate 16 and the source 18. 20 thickness, floating gate 16 and control gate 1
7 depends on the thickness of the oxide film 20 interposed between the oxide film and the like.

On the other hand, the memory cells forming the memory cell array 1 have manufacturing variations. That is, the thickness of the oxide film 20, the shapes of the control gate 17 and the floating gate 16, the length of the channel region, etc. are slightly different for each memory cell and do not completely match. Therefore, even if a high voltage for erasing data is collectively applied to all the memory cells MC in the memory cell array 1, it is actually possible to reduce the threshold voltage of all the memory cells MC to the same value. Have difficulty.

That is, in some of the memory cells to which a high voltage for erasing data is collectively applied, only the electrons injected from the floating gate 16 by the circuit operation in step S11 of FIG. In some other memory cells, more electrons than the amount injected by the circuit operation in step S11 of FIG. 6 are removed from the floating gate 16 in some other memory cells, and in some other memory cells, Only a small part of the electrons injected by the circuit operation in step S11 of FIG. 6 is removed from the floating gate.

The phenomenon in which more electrons than the electrons injected by the data writing are extracted from the floating gate is called over-erasing or over-erasing.

When over-erasing occurs in a memory cell, the floating gate 16 thereof is positively charged.
A channel is formed between the source 18 and the drain 19 of the control gate 17 although no positive potential is applied to the control gate 17. This is the control gate 17
This means that the memory cell is in the ON state regardless of any potential of 0 V or more applied to the memory cell.

As a result, at the time of data reading, a current flows through the corresponding bit line although the high level potential is not applied to the control gate of this memory cell. Therefore, when data is read from a memory cell connected to the same bit line as the over-erased memory cell,
Even if the data stored in this memory cell is "0", the data read by the sense amplifier 8 is "1".

Further, at the time of data writing, if an attempt is made to write data "0" to an over-erased memory cell or a memory cell connected to the same bit line as the over-erased memory cell, this data "0" is written. The hot electrons generated in the memory cell in which "" is to be written leaks to the bit line as the channel current of the overerased memory cell. Therefore, electrons are not sufficiently injected into the floating gate 16 of the memory cell in which the data “0” should be written. Therefore, if there are over-erased memory cells, the writing characteristics at the time of data writing are deteriorated and writing becomes impossible.

As described above, the over-erasure reverses the polarity of the threshold voltage of the memory cell to a negative value, which hinders subsequent data reading and data writing.

Therefore, in order to prevent such over-erasure,
The following methods are currently used.

That is, the source line 2 is used for erasing data.
The pulse width of the high-voltage pulse applied to 8 is shortened, and every time the high-voltage pulse having the short pulse width is applied to the source line 28, the stored data of all the memory cells MC in the memory cell array 1 are read out and all Check if it becomes "1". If even one memory cell whose stored data is not "1" is detected, the pulse having the short pulse width as described above is applied to the source line 28 again.

Whether the stored data in the memory cell MC becomes "1" by applying a high voltage pulse for erasing data to the source line 28, that is, whether the stored data in the memory cell is completely erased or not. Confirming that is called erase verify.

The erase verify and the application of the high voltage pulse for data erase to the source line 28 are repeated until the data in all the memory cells MC in the memory cell array 1 are completely erased.

FIG. 6 shows a circuit operation flow of the entire flash EEPROM for erasing data including such erase verification.

Next, a flash EE for erasing data
The circuit operation of the entire PROM will be described.

First, the normal power supply voltage V _cc (see FIG. 9)
(F)) and the high voltage V _PP (FIG. 9 (g)) are started up. (Step S10 of FIG. 6) Subsequently, the circuit operation of steps S2 to S7 of FIG. 7 is repeated for all the addresses (FIG. 9A) in the memory cell array 1 so that all the memories in the memory cell array 1 are processed. Data "0" is written in the cell MC. (Step S11 of FIG. 6) Next, the write enable signal / WE (FIG. 9)
(D)) is lowered, and the data signal 20 _H input from the outside to the input / output terminals VO0 to VO7 is input / output buffer 9
It is latched in the command register 12 via. This is because the erase command, which is an instruction to erase the stored data in the memory cell array 1, is the flash EEPROM.
Means that was given to. (Step S1 of FIG. 6
2) Subsequently, as an erase confirmation command, which is an instruction for confirming whether or not the stored data in the memory cell array 1 is completely erased, as input / output terminals VO0 to VO7 after the fall of the write enable signal / WE, The data signal 20 _H supplied from the outside is latched in the command register 12. (Step S13 in FIG. 6) Subsequently, the command decoder 13 decodes the data signal indicating the erase command first latched in the command register 12 to erase the stored data in the memory cell array 1 from the flash EEPROM. Set to erase mode.

When the flash EEPROM is set to the erase mode, the source line switch 3 supplies the high voltage V _PP to the source line 28 in the memory cell array 1 for a short period from the fall of the write enable signal / WE to the rise thereof.
Apply to. As a result, a tunnel phenomenon occurs in all the memory cells MC in the memory cell array 1 based on the above-described principle, and electrons are extracted from the floating gate to the source. (Step S14 in FIG. 6) Source line 2
When the application of the high voltage V _PP to 8 ends and the write enable signal / WE falls, the address register 6 latches the address signal indicating the start address in the memory cell array 1 regardless of the external address signal. ..

Next, in response to the rise of the write enable signal / WE, erase verify, which is an instruction to execute a circuit operation for confirming whether or not the stored data in the memory cell array 1 has been completely erased. As a command, a data signal AO _H (FIG. 9E) externally input to the input / output terminals VO0 to VO7 is latched in the command register 12 via the input / output buffer 9. The command decoder 13 decodes this data signal latched in the command register 12, and sets the flash EEPROM in the erase verify mode for confirming whether the stored data in the memory cell array 1 has been completely erased.
(Step S15 in FIG. 6) When the flash EEPROM is set to the erase verify mode, the verify voltage generating circuit 11 causes the verify voltage generating circuit 11 to slightly lower the voltage (3. 2 V) is applied to the X decoder 4 and the Y decoder 5.

The X decoder 4 supplies this slightly lower voltage to one word line provided corresponding to the memory cell row indicated by the address signal latched in the address register 6. Similarly, the Y decoder 5 outputs this slightly lower voltage to one bit provided in the transistor 26 in the Y gate 2 corresponding to the memory cell column indicated by the address signal latched in the address register 6. Supply only one gate connected to the line. Therefore, one memory cell M indicated by the address signal latched in the address register 6 is operated according to the same principle as in the normal data read.
The data stored in C is read by the sense amplifier 8.
(Step S16 in FIG. 6) However, since the potential applied to the control gate of the memory cell from which data is to be read is lower than that at the time of normal data read, the threshold voltage of this memory cell MC is the same as the previous data erase. Unless the memory cell MC is shifted to a sufficiently low value, the data read by the sense amplifier 8 does not become data "1".

That is, if the electrons injected into the floating gate of the memory cell MC are not completely removed by the circuit operation for erasing the data by the circuit operation in step S11 of FIG. Although the threshold voltage does not drop sufficiently, the voltage applied to the control gate is high to some extent, and if it is above this threshold voltage, this memory cell MC is in the ON state despite insufficient data erasing. Becomes However, if the voltage applied to the control gate is low, only the memory cell having a sufficiently low threshold voltage is turned on.

Therefore, in order to more surely confirm whether or not the data stored in each memory cell MC has been completely erased,
The voltage supplied to the control gate for data reading in the erase verify mode is set lower than that during normal data reading.

If the data read by the sense amplifier 8 in step S16 of FIG. 6 is "0", the stored data in the memory cell MC indicated by the address signal currently latched in the address register 6 is still completely erased. Since it can be determined that it is not (step S17 in FIG. 6),
The circuit operation of steps S12 to S17 of FIG. 6 is repeated again.

If the data read by the sense amplifier 8 in step S16 is "1", it can be determined that the stored data in the memory cell indicated by the address signal currently latched in the address register 6 has been completely erased. Therefore, in this case, if the address signal latched in the address register 6 does not indicate the final address in the memory cell array 1 (step S19 in FIG. 6), the address signal latched in the address register 6 (see FIG. 9 (a)) is incremented (see FIG. 6).
Step S18), and the circuit operation after Step S15 is repeated.

As a result of such circuit operation, when the address signal latched in the address register 6 indicates the final address in the memory cell array 1, the stored data in all the memory cells MC in the memory cell array 1 are completely stored. Since it can be determined that the flash EEPROM has been erased, the command register 12 sets the flash EEPROM to the normal data read mode. (Step S20 in FIG. 6)

[0085]

As described above, according to the flash EEPROM, a current flows through the bit line during any of data writing, data erasing, and data reading.

For example, referring to FIG. 5, at the time of data writing, memory cell MC to which data "0" is to be written is O.
Since it is in the N state, a current flows from the input / output line 27 to the source line 28 via the bit lines BL1 to BL3 connected to this memory cell MC.

At the time of data erasing, in each memory cell MC, electrons are extracted from the floating gate to the source, so that the electrons become a current flowing through the source line 28.

FIG. 10 shows the relationship between the source-drain current I _GS and the source-gate voltage V _GS in each of the memory cell whose stored data is "0" and the memory cell whose stored data is "1". It is a graph which shows.

Referring to FIG. 10, in the memory cell in which electrons are not injected into the floating gate, that is, in the memory cell in which the stored data is "1", the current I _DS between the source and the drain and the current between the source and the gate are The relationship with the voltage V _GS is shown by a curve. On the other hand, in the memory cell in which electrons are injected into the floating gate, that is, in the memory cell in which the stored data is “0”,
The relationship between the source-drain current _IDS and the source-gate voltage _VGS is shown by a curve.

At the time of data writing, the curve showing the relationship between the source-drain current I _DS and the source-gate voltage V _GS is shown by the rise of the threshold voltage Vth as electrons are injected into the floating gate. To the right, and is fixed to the curve by the end of application of the high voltage V _PP for writing data.

On the contrary, when erasing data, the curve showing the relation between the current I _DS between the source and drain of the memory cell and the voltage V _GS between the source and the gate is a threshold voltage Vth as electrons are extracted from the floating gate.
Shifts to the left in the figure due to the decrease of the voltage, and is fixed to the curve when the application of the high voltage V _PP for erasing data is completed.

Therefore, in order to write the data "0"
High voltage on control gate and drain of memory cell
The source of this memory cell is
Voltage between gate and gate V_GSIs constant, so this memo
Channel current I of the recell MC _DSStart applying this high voltage
It is sometimes the largest, and then gradually decreases.

On the other hand, at the time of erasing data, the memory cell MC
Since an amount of electrons corresponding to the potential difference between the floating gate and the source tunnels from the floating gate to the source, a tunnel current having a magnitude corresponding to the potential difference flows between the floating gate and the source. Since the potential of the control gate is constant while the high voltage V _PP for erasing data is applied between the source and the control gate, the potential of the floating gate increases as electrons flow from the floating gate to the source. Therefore, the potential difference between the floating gate and the source becomes small. Therefore, the current flowing through the source line 28 at the time of data erasing is the largest immediately after the high voltage for data erasing is applied to the memory cell MC, and then gradually decreases.

As described above, the magnitude of the current flowing through the memory cell MC at the time of data erasing and data writing is not constant but changes transiently.

On the other hand, in order to measure the current consumption of the semiconductor memory device, conventionally, a constant voltage is applied to the external terminal of the semiconductor memory device for a predetermined period, and the current flowing through the predetermined external terminal during this period is measured. The method of measuring with a meter is used. Therefore, if the period in which the constant voltage is applied is short, the value measured by the ammeter or the like during this period is the average value of the current that has flowed to the predetermined external terminal during this period. That is, according to the conventional method, it is difficult to measure the change in current consumption in a short period.

For example, referring to FIGS. 3 and 5, in the flash EEPROM, at the time of data writing, externally supplied high voltage V _PP or a voltage derived therefrom is applied to any word line in memory cell array 1. W
While being applied to L1 to WL3 and bit lines BL1 to BL3, any transistor 26 in the Y gate 2 from the input / output line 27, bit lines BL1 to BL3 connected to this transistor 26, and this bit line Source line 2 via any memory cell MC connected to
A current flows through 8. Further, at the time of erasing data, a current flows between each memory cell MC and the source line 28 while the high voltage V _PP supplied from the outside is applied to the source line 28.

Therefore, the current consumption during data erasing and data writing can be measured, for example, by measuring the current flowing through external terminal T _pp receiving high voltage V _PP .

However, since the period during which the high voltage is applied to the memory cell MC for data writing and data erasing is very short, the value thus measured is the average value of the current consumption during data erasing. And the average value of the current consumption at the time of data writing is shown.

From the viewpoint of power consumption of the semiconductor device, it is important to grasp the instantaneous value of the magnitude of the current flowing in the circuit. For example, flash EEPR
In the OM, if the change in the magnitude of the current flowing through the memory cell array 1 is not measured at the time of data writing or data erasing, the power consumption at the time of data writing or data erasing of this flash EEPROM can be known accurately. I can't.

Therefore, an object of the present invention is to solve the above problems and provide a semiconductor device capable of measuring a transient change of a current flowing in a circuit during operation within a short time. It is to be.

[0101]

In order to achieve the above-mentioned object, a semiconductor memory device according to the present invention has a first external terminal that receives a predetermined voltage and a first external terminal during normal operation. A circuit means that operates in response to a voltage; a second external terminal that receives a voltage higher than a predetermined voltage from the outside; and a second external terminal that supplies the voltage of the second external terminal to the circuit means during measurement. Electrical path means coupled between the external terminal and the internal circuit means. The semiconductor device according to the present invention further includes impedance control means for changing the impedance of the electric path means by following a change in the difference between the voltage of the second external terminal and the output voltage of the second electric path means during measurement. , Conversion means for converting a current flowing through the electric path means into a voltage according to the magnitude thereof.

[0102]

Since the semiconductor device according to the present invention is configured as described above, the output voltage of the electric path means changes due to the consumption current in the circuit means during measurement, and the output voltage of the electric path means and the predetermined voltage are changed. When the difference changes, the impedance of the electric path means connecting between the second external terminal and the circuit means changes, so that the magnitude of the current flowing through the electric path means changes. This current is converted to a voltage by the conversion means, so that a change in the magnitude of this current appears in the output voltage of the conversion means.

[0103]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a flash EE according to an embodiment of the present invention.
It is a schematic block diagram which shows the whole structure of PROM.

Referring to FIG. 1, this flash EEPR
The OM is a conventional flash EEPROM shown in FIG.
In addition to the circuit section 54 constituting the circuit, a transient current detection circuit 50 for detecting a change in the current flowing in the circuit section 54.
0 and the external terminal T _IP newly provided for this detection
And T _IM .

Since the structure and operation of the circuit portion 54 are the same as those in the conventional flash EEPROM, the description thereof will be omitted. However, in this embodiment, the high voltage V _PP used for writing data in the memory cell array 1 and erasing data in the memory cell array 1 is applied to the circuit section 54 via the transient current detection circuit 500.

The structure and operation of the transient current detection circuit 500 will be described below. The transient current detection circuit 500 is
The _VIP applying circuit 50 for transmitting a signal externally applied to the external terminal T _IP to the circuit portion 54, the high voltage V _PP applied externally for writing and erasing data and the circuit portion 54 Voltage supplied through the transient current detection circuit 500 (hereinafter referred to as internal power supply voltage) VINT _pp
A comparison circuit 51 for comparing the current, a current-voltage conversion circuit 52 for converting the current supplied from the external terminal T _IP to the _VIP application circuit 50 into a voltage proportional to its magnitude, and a power supply switching circuit 5
Including 3.

The power supply switching circuit 53 uses the high voltage V _PP or one of the high voltage V _IP externally applied to the external terminal T _IP as the internal power supply voltage VINT _PP.
Give to 4.

FIG. 2 is a circuit diagram showing the structure of the transient current detection circuit 500 in more detail. Referring to FIG. 2, comparison circuit 51 includes P-channel MOS transistors connected in series with each other between external terminal T _IP and an external terminal receiving ground potential Vss.
Transistor 61, N-channel MOS transistor 63
And 65 and P-channel MOS transistors 62 and 6 connected in parallel with transistors 61 and 63.
Including 4 and.

Externally applied high voltage V _PP and internal power supply voltage VINT _PP are applied to the gates of transistors 63 and 64, respectively. Transistors 61 and 6
The gate of 2 has a connection point N of the transistors 61 and 63.
2 is commonly connected. The gate of the transistor 65 is connected to the external terminal T _IP .

Therefore, when a high potential is externally applied to the external terminal T _IP and the transistor 65 is turned on,
The comparator circuit 51 operates as a differential amplifier for the two input voltages V _PP and VINT _PP .

That is, the external high voltage V_PPInside
Power supply voltage VINT_PPHigher than, transistor 6
4 becomes an ON state deeper than the transistor 63. this
Therefore, from the connection point N1 of the transistors 62 and 64,
It is supplied to the transistor 65 via the transistor 64.
The current flows from the node N2 through the transistor 63 to the transistor
The current supplied to the transistor 65 is larger than
The potential at the connection point N2 between the transistors 61 and 63 is the external end.
Child T_IPRises due to the high potential of. Above the potential of node N2
As the transistor 62 is turned off by the rise,
Output terminal T_IPCurrent is not supplied from node N1 to node N1. This
As a result, the potential of the node N1 is the ground potential V _SSLow to near
Down.

On the contrary, if the external high voltage V _PP is lower than the internal power supply voltage VINT _PP , the transistor 63 is in the ON state deeper than the transistor 64. Therefore, the current supplied from the node N2 to the transistor 65 via the transistor 63 becomes larger than the current supplied from the node N1 to the transistor 65, and the potential of the node N2 decreases. When the transistor 62 is turned on due to the potential decrease of the node N2, the potential of the node N1 rises to this high potential V _IP due to the current flowing from the external terminal T _IP to the node N1 via the transistor 62.

[0113] Thus, the potential of the node N1, the internal power supply voltage VINT _PP increases is higher than the high voltage V _PP from the external, the internal power supply voltage VINT _PP is lower than the high voltage V _PP from the outside If it gets lower. The potential of the node N1 is used as the output of the comparison circuit 51.

If the potential supplied from the outside to the external terminal T _IP is low and the transistor 65 is in the OFF state, the node N
Since the current path between 1 and N2 and the ground potential is not formed regardless of the gate potentials of transistors 63 and 64, comparison circuit 51 does not perform the above operation.

The power supply switching circuit 53 uses a high voltage V from the outside.
A P-channel MOS transistor 69 and an N-channel MOS transistor 70 connected in series with each other between an external terminal Tpp receiving _PP and an external terminal Tss receiving the ground potential Vss, a current-voltage conversion circuit 52, and an external terminal Tpp. P-channel M connected in series with each other between
OS transistors 67 and 68 are included.

The potential of the external terminal T _IP is applied to the gates of the transistors 68 to 70, and
The potential at the connection point of the transistors 69 and 70 is applied to the gate of the.

Therefore, when the potential supplied from the outside to the external terminal T _IP is high, the transistor 69 is turned off and the transistor 70 is turned on, so that the gate potential of the transistor 67 is lowered and the transistor 67 is turned on.
Is turned on. On the other hand, the transistor 68 is turned off.

On the contrary, when the potential supplied from the outside to the external terminal T _IP is low, the transistor 69 is turned on and the transistor 70 is turned off, so that the gate potential of the transistor 67 rises and the transistor 67 is turned off.
It becomes a state. On the other hand, the transistor 68 is turned on.

As described above, one of the transistors 67 and 68 is turned on according to the potential externally supplied to the external terminal T _IP .

Connection point N3 of transistors 67 and 68
Is applied as the internal power supply voltage VINT _{P P} to the circuit portion 54 of FIG. 1 as a high voltage for data writing and data erasing.

If the potential supplied to the external terminal T _IP is high, the internal power supply voltage VINT _PP is supplied to the node N3 by the current-voltage conversion circuit 52, and if the potential supplied from the outside to the external terminal T _IP is low, High voltage V _PP is supplied to node N3 as internal power supply voltage VINT _PP .

V _IP applying circuit 50 includes a P-channel MOS transistor 60 connected between external terminal T _IP and current-voltage converting circuit 52 and receiving the output potential of comparing circuit 51 at its gate.

Current-voltage conversion circuit 52 includes a resistor 66 connected between transistor 60 and transistor 67 in power supply switching circuit 53. The potential of the connection point N4 of the transistor 60 and the resistor 66 is supplied to the external terminal T _IM as the output V _IM of the current-voltage conversion circuit 52.

Therefore, when a high potential is externally applied to the external terminal T _IP , the transistor 60 is in a deeper ON state as the output potential of the comparison circuit 51 is lower.
The current flowing from the external terminal T _IP into the resistor 66 via the transistor 60 increases. The potential V _{IM of the} node N4 rises as the current flowing into the resistor 66 increases.

For example, when the external terminal T _IP is supplied with a high potential from the outside and the internal power supply voltage VINT _PP becomes higher than the external voltage V _PP , the potential of the node N1 reaches the potential V _IP of the external terminal T _IP. Since the voltage rises, the transistor 60 is turned off. By this, the node N4
Is no longer supplied from the external terminal T _IP, and the potential of the node N4 begins to drop.

As the potential of the node N4 decreases, the node N3
If the internal power supply voltage VINT _PP becomes lower than the external voltage V _PP , the potential of the node N1 becomes a low potential close to the ground potential Vss, contrary to the above. As a result,
The transistor 60 is turned on to supply a current from the external terminal T _IP to the resistor 66. Therefore, the node N4
The potential of the transistor 60 is the ON resistance value of the transistor 60
6, to the potential determined by the ratio of the transistor 67 and the total impedance of the circuit section 54 in FIG.

As the potential of the node N4 rises, the node N
When the potential of No. 3, that is, the potential of the internal power supply voltage VINT _PP becomes higher than the external voltage V _PP , the transistor 60 is turned off again by the circuit operation as described above, and the potential of the node N4 is lowered.

In this way, when the external terminal T _IP is supplied with a high potential from the outside, the internal power supply voltage VINT
The input impedance of the transistor 60 is controlled by the comparison circuit 51 so that _PP is always the same as the external voltage V _PP , so that the potential of the node N4, that is, the output potential V _{IM of the} current-voltage conversion circuit 52 becomes It changes according to the potential change of the internal power supply voltage VINT _PP .

Specifically, the output potential V _IM of the current-voltage conversion circuit 52 becomes equal to the potential V _IP of the external terminal T _IP when the input impedance of the transistor 60 is minimum, and the input impedance of the transistor 60 is infinite. (That is, when the transistor 60 is in the OFF state), the node N3 is turned on by the transistor 67 in the ON state.
Since the transmitting potential VINT _PP, external voltage V _PP
Is almost the same value as. In other words, the potential of the node N4 follows the fluctuation of the internal power supply voltage VINT _PP and follows the external voltage V
It varies between _PP and V _IP.

Referring to FIGS. 1 and 2, word lines WL1 to WL1 are used when data is written in memory cell array 1.
If a current flowing from the write circuit 7 to the source line switch 3 through the Y gate 2 and the memory cell array 1 by applying a high voltage to the bit line 3 and the bit lines BL1 to BL3 is large, the node N4 passes through the resistor 66 and the transistor 67. Then, the current flowing through the node N3 that is the supply source of this high voltage increases, so that the potential V _{IM of the} node N4 rises.

Similarly, if the current flowing between the memory cell array 1 and the source line switch 3 due to the application of the high voltage to the memory cell array 1 at the time of erasing the stored data in the memory cell array 1 is large, the node which is the source of the high voltage is supplied. Since the current flowing through the resistor 66 and the transistor 67 between N3 and the node N4 increases, the node N4
Potential rises.

As described above, the larger the current consumption of the circuit portion 54 when writing data to the memory cell array 1 or erasing the stored data in the memory cell array 1, the more the current-voltage conversion circuit 52 and the power supply switching circuit 53 are The current flowing from the node N4 to the node N3 via the resistor 66 and the transistor 67 increases, and the current-voltage conversion circuit 5
The output voltage V _{IM of} 2 largely changes.

Therefore, when it is desired to detect the current consumption during the operation of the circuit portion 54, it is higher than the high voltage V _PP for writing data in the memory cell array 1 and erasing the data in the memory cell array 1 at the external terminal T _IP. When the voltage is supplied from the outside, the same voltage as the normal voltage is supplied to the node N3 as a high voltage for data writing and data erasing, so that the data writing to the memory cell array 1 and the data erasing of the memory cell array 1 are performed as usual. While the circuit operation is executed, the transient change in the current consumption caused by the circuit operation can be detected by the tester or the like as a change in the voltage V _IM appearing at the external terminal T _IM .

If such a transient current is not detected, the comparison circuit 5 can be constructed by grounding the external terminal T _IP.
1 is disabled, and the external voltage V is set by the power supply switching circuit 53.
_PP is supplied to node N3 as a high voltage for erasing data in memory cell array 1 and writing data in memory cell array 1. Therefore, in the state where current detection is not performed by the _VIP applying circuit 50, the comparison circuit 51, and the current-voltage conversion circuit 52, data writing to the memory cell array 1 or data erasing of the memory cell array 1 is normally performed in the circuit section 54. It will be done as follows.

In the above embodiment, the present invention is the flash EE.
Although the case where the present invention is applied to the PROM has been described, the present invention is applicable to the semiconductor device in general, and particularly applied to the semiconductor device that needs to measure the transient change of the current consumption during the operation of the internal circuit. It is more effective.

[0136]

As described above, according to the present invention, the change in the amount of current consumption during the operation of the internal circuit of the semiconductor device is easily changed as the change in the output potential from the predetermined external terminal of the semiconductor device. Can be measured. Therefore, it is possible to easily measure even a transient change in the amount of current consumption during the operation of the internal circuit, and it is also possible to test the characteristics of the internal circuit in a short time.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a flash EEPROM according to an embodiment of the present invention.

2 is a circuit diagram showing an example of a configuration of a transient current detection circuit 500 of FIG.

FIG. 3 is a schematic block diagram showing an overall configuration of a conventional flash EEPROM.

FIG. 4 is a sectional view showing a structure of a memory cell in a flash EEPROM.

5 is a circuit diagram showing a configuration of a memory cell array 1 and a Y gate 2 of FIG.

FIG. 6 is an operation flow diagram showing a circuit operation flow at the time of erasing data in the conventional flash EEPROM.

FIG. 7 is an operation flow diagram showing a circuit operation flow at the time of data writing in the conventional flash EEPROM.

FIG. 8 is a timing chart showing changes in input / output signals when writing data in a conventional flash EEPROM.

FIG. 9 is a timing chart showing changes in input / output signals when erasing data in a conventional flash EEPROM.

FIG. 10 is a graph showing changes in electrical characteristics of a memory cell in a flash EEPROM due to data writing and data erasing.

[Explanation of symbols]

1 memory cell array 2 Y gate 3 source line switch 4 X decoder 5 Y decoder 6 address register 7 write circuit 8 sense amplifier 9 input / output buffer 50 _VIP application circuit 51 comparison circuit 52 current-voltage conversion circuit 53 power supply switching circuit 500 transient Current detection circuit T _IP , T _IM external terminal In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/115 27/10 481 8728-4M 8831-4M H01L 27/10 434

Claims (1)

[Claims] 1. A first external terminal that receives a predetermined voltage, a second external terminal that receives a voltage higher than the predetermined voltage from the outside during measurement, and a voltage applied to the first external terminal during normal operation. Circuit means operating in response to the voltage, and electrical path means coupled between the external terminal and the circuit means for supplying the voltage of the second external terminal to the circuit means during measurement. An impedance control means for changing the impedance of the electric path means by following a change in the difference between the output voltage of the electric path means and the voltage of the first external terminal at the time of measurement; A semiconductor device, comprising: a conversion unit that converts a current flowing through the circuit into a voltage according to the magnitude of the current.