JPH0566940A - Cpu executing instruction analysis system - Google Patents

Abstract

PURPOSE:To facilitate the analysis of the cause of a fault which unable to continue the due processing and to improve the system reliability by storing the instruction carried out by a CPU in a memory together with the data which analyze the execution of the instruction. CONSTITUTION:A CPU 1 is provided to carry out an instruction together with an instruction writing buffer 7 which stores the instruction, an unexecuted data writing buffer 9 which stores the unexecuted data on the instruction carried out by the CPU 1, a memory 13 which stores the instructions stored in both buffers 7 and 9, and a means 11 which stores the instruction stored in the buffer 7 and the data stored in the buffer 9 into the memory 13 when the bit of a status register showing the state of the CPU 1 changes or one of both buffers 7 and 9 is filled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention facilitates the analysis of instructions executed by a CPU by storing in the memory the instruction executed by the CPU and the data necessary for the analysis. The present invention relates to a CPU execution instruction analysis method.

[0002]

2. Description of the Related Art A CPU (Central Processing Unit) for controlling an input / output device, an arithmetic unit, and a storage device of a computer system executes a command which is an operation command to control the computer system.

Conventionally, in a computer system, C
The instruction executed by the PU and the data for analyzing the instruction have not been stored in the storage device or the like. Therefore,
For example, if a trap that cannot continue processing occurs, C
Difficult to parse the instructions executed by the PU,
In particular, CP that executes complicated control such as pipeline control
At U, it was not easy to prevent the efficiency of the system from decreasing.

[0004]

By the way, the conventional CP
In the U execution instruction analysis method, since the instruction executed by the CPU and the data for analyzing the instruction are not stored in the storage device, the cause of the trap is analyzed even if a trap or the like which cannot continue the processing occurs. However, in a system that executes complicated control such as pipeline control, there is a problem that system reliability is deteriorated due to unknown cause.

The present invention has been made in order to solve such a conventional problem, and an object thereof is to store an instruction executed by a CPU and data for analyzing the execution of the instruction in a memory. It is to provide a CPU execution instruction analysis method that facilitates analysis of the cause of a failure in which processing cannot be continued and improves system reliability.

[0006]

In order to achieve the above object, the present invention provides a CPU for executing an instruction, an instruction writing buffer for storing an instruction executed by the CPU, and an instruction executed by the CPU. Of the pre-execution data write buffer for storing the data before execution of, the memory for storing the data stored in the pre-execution data write buffer and the instruction stored in the instruction write buffer, and the CPU If the status register bit indicating the status has changed or if one of the instruction write buffer and pre-execution data write buffer is in the buffer full state, the instruction and pre-execution data write stored in the instruction write buffer Means for storing the data stored in the data buffer in the memory, The gist.

[0007]

With the above arrangement, the status register indicating the state of the CPU and the buffer full flag of the instruction write buffer and the pre-execution data write buffer are monitored. When the bit of the status register indicating the state of the CPU is changed or when either the instruction writing buffer or the pre-execution data writing buffer is in the buffer full state, the instruction and execution stored in the instruction writing buffer are executed. Since the data stored in the previous data writing buffer is stored in the memory, it is possible to easily analyze the cause of the failure in which the processing cannot be continued.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU execution instruction analysis system of the present invention.

In FIG. 1, the CPU 1 has an execution instruction writing unit 3 and a pre-execution data writing unit 5 to execute an instruction which is an operation command to an input / output device, a computing device and a storage device of a computer system. The execution instruction writing unit 3 writes, among the instructions fetched by the CPU 1, an instruction which is determined to be executed, to a predetermined address of an instruction writing buffer 7 described later. Pre-execution data writing unit 5
When the CPU 1 executes an instruction, the data already stored in the general-purpose register 17 when the instruction stored in the instruction-writing buffer 7 to be described later is an instruction to execute writing to the general-purpose register 17 to be described later. Is written in a predetermined address of the pre-execution data write buffer 9 described later.

The instruction writing buffer 7 writes an instruction to be executed by the CPU 1 by the execution instruction writing unit 3 at a predetermined address. In the pre-execution data writing buffer 9, when the pre-execution data writing unit 5 issues an instruction to execute writing to the general-purpose register 17 of the CPU 1, the data already stored in the general-purpose register 17 is written to a predetermined address. ..

The instruction writing buffer 7 and the pre-execution data writing buffer 9 are provided with a buffer full flag. When the buffer becomes full, the buffer full flag becomes "1", for example.

The data storage unit 11 monitors a buffer full flag of the instruction writing buffer 7 and the pre-execution data writing buffer 9 and a status register 23 provided in the CPU 1 which will be described later. When the buffer full flag is "1" indicating the buffer full state or the specific bit of the status register 23 is changed, the data storage unit 11 causes the instruction executed by the CPU 1 written in a predetermined address of the instruction write buffer 7 to be executed. And the data already written in the predetermined address of the pre-execution data writing buffer 9 and already stored in the general-purpose register 17 is stored in the predetermined sector of the magnetic disk 13.

The magnetic disk 13 stores, in a predetermined sector, an instruction executed by the CPU 1 by the data storage unit 11 and data which is data already stored in the general-purpose register 17 and which is necessary to analyze the instruction. The instruction and data stored at the address indicated by the predetermined sector record on the magnetic disk 13 facilitates the investigation of the cause of a trap or the like which makes it impossible to continue processing.

The control of the CPU 1 will be described with reference to the block diagram of FIG.

The CPU 1 has the execution instruction writing unit 3 described above.
In addition to the pre-execution data writing unit 5, a decoder 15, a general-purpose register 17, a fetcher 19 and a status register 23 are provided.

The decoder 15 includes an execution instruction writing unit 3
The CPU 1 outputs an instruction (code) to be executed by the CPU 1 and outputs a destination register selection signal to the pre-execution data writing unit 5.

The general-purpose register 17 has, for example, 32 registers GRO to GR31 and is used by the CPU 1 to store the data already written in the register. The general data register 17 stores the instruction executed by the CPU. It becomes the data necessary for analysis.

When an instruction is input from the decoder 15, the execution instruction writing section 3 stores the input instruction at a predetermined address of the instruction writing buffer 7. The pre-execution data writing unit 5 reads the selection signal of the destination register input from the decoder 15, and when the selection signal is valid, selects the register of the general-purpose register 17 using the selection signal. After the selection, the pre-execution data writing unit 5 reads the data in the selected register and writes the data in a predetermined address of the pre-execution data writing buffer 9. When the selection signal is not valid, it is in a high impedance state.

The fetcher 19 fetches an instruction from the decoder 15 and outputs it to the bus 21.

The status register 23 has a specific bit indicating the state of the CPU 1, and when the state of the CPU 1 changes, the value of the specific bit changes to, for example, "1".

Next, the operation of this embodiment will be described with reference to the flowchart of FIG.

First, after the system is started up, when the instruction (code) to be executed by the CPU 1 is input from the decoder 15 to the execution instruction writing unit 3, the execution instruction writing unit 3 stores it in a predetermined address of the instruction writing buffer 7. Further, the pre-execution data writing unit 5 reads the selection signal of the destination register output from the decoder 15, and when the selection signal is valid, takes in the data stored in the register of the general-purpose register 17 indicated by the selection signal. , Write to a predetermined address of the pre-execution data write buffer 9. On the other hand, if the selection signal is not valid, the system enters a waiting state (steps 100-1).
60).

After writing, the data storage unit 11 monitors specific bits of the status register 23 and the buffer full flag of the instruction writing buffer 7 and the pre-execution data writing buffer 9. When the specific bit is changed or the buffer full flag is "1" indicating the buffer full state, the data storage unit 11 executes the instruction executed by the CPU 1 stored in the instruction writing buffer 7 at a predetermined address and the execution. Data necessary for analysis of the instruction of the CPU 1 written in a predetermined address of the previous data writing buffer 9 is stored in the magnetic disk 13 (steps 170 to 190).

Since the command executed by the CPU 1 and the data necessary for interpreting the command are stored in the magnetic disk 13, it is impossible to execute the process by analyzing the command and the data executed by the CPU 1. The cause of traps, etc. can be reliably analyzed.

In the present embodiment, for example, a computer system which emphasizes a fault tolerant function of continuing the control of the OS (operating system) by the other CPU even if one of the two CPUs has an abnormality occurs. It facilitates analysis of a failure such as a trap in the CPU included therein.

[0027]

As described above, according to the present invention, CP
Since the instruction executed by U and the data necessary for analysis of the instruction are stored in the memory, the continuation of the process cannot be continued by storing the instruction executed by the CPU and the data analyzing the execution of the instruction in the memory. The analysis of possible causes of failure can be facilitated and the system reliability can be improved.

[Brief description of drawings]

FIG. 1 is a CPU execution instruction analysis method of the present invention.

FIG. 2 is a block diagram showing control of a CPU.

FIG. 3 is a flowchart showing the operation of the present invention.

[Explanation of symbols]

 1 CPU 3 Execution command writing unit 5 Pre-execution data writing unit 7 Command writing buffer 9 Pre-execution data writing buffer 11 Data storage unit 13 Magnetic disk 15 Decoder 17 General-purpose register 23 Status register

Claims (1)

[Claims] 1. A CPU for executing an instruction, an instruction writing buffer for storing an instruction executed by the CPU, and a pre-execution data writing buffer for storing data before execution of the instruction executed by the CPU. A memory for storing the data stored in the pre-execution data write buffer and the instruction stored in the instruction write buffer, and a case where a bit of a status register indicating the state of the CPU has changed or the instruction write Means for storing the instruction stored in the instruction write buffer and the data stored in the pre-execution data write buffer in the memory when either the write buffer or the pre-execution data write buffer is in a buffer full state And a CPU execution instruction analysis method.