JPH056660A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a reset data to be written into a memory cell stably by allowing a dummy word signal generation circuit to deactivating a circuit for compensating a reference level at the time of flush write(FW). CONSTITUTION:When a semiconductor memory device is set to an FW mode, a dummy word signal generation circuit 100 performs control to suppress generation of a dummy word signal with the FW mode flag signal which is generated only at the FW mode or a signal which is obtained by performing a logic operation with the FW mode flag signal. In this manner, the FW mode flag signal prevents the dummy word signal from being generated by the FW mode flag signal in the case of the FW mode (deactivation of circuit for compensating a reference level), thus enabling a potential difference between digit lines which is generated by a previous restorage cell data of a memory cell and that between worst digit lines to be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit for high-speed image reset processing (Flash).
Write method).

[0002]

2. Description of the Related Art An image high-speed reset function is one of the recent demands for digitization and high speed of image processing. This function is CR
It is a function of clearing an image formed on T or the like in a short period of time. Generally, this function is
h Write) function (hereinafter, referred to as FW).

FW is a specific mode in a certain RAS cycle, and the semiconductor memory device determines the level of another external input Pin when the write enable signal falls, and becomes the FW cycle.

Here, the semiconductor memory device performs the following operations in the FW cycle. That is, the flash write data is rewritten to the designated flash write data regardless of the data holding the contents of all the memory cells connected to a selected word line. As a result, the contents of the memory cell can be rewritten to the same data at high speed, and high-speed reset of the image data can be realized.

Next, a conventional FW system will be described with reference to the drawings. FIG. 4 shows the circuit configuration of an array for realizing the conventional FW function, and FIG. 5 shows the operation waveform of each signal in the conventional example shown in FIG.

First, a normal dynamic RAM (hereinafter,
Similar to the read / write operation in the DRAM), the digit lines D and DB are separated from the HVCC circuit by the fall of the precharge signal PDL (t1). Next, the dummy word signal DUMMY Word supplied to the sense reference level correction circuit 460 drops (t2), and one word line WL is selected.

During the FW function, the gate opening / closing signal F for FW
By opening the transfer gate 450 with WSW (t
3), FW data buses FWBUS and FWBUS (overline) are connected to digit lines D and DB, respectively. As a result, the FW data is forcibly supplied to the digit lines D and DB, and even if the selected memory cell MC holds the data of the inverse logic level, the sense amplifier SA can detect the FW data. When the voltage difference is applied to the digit lines D and DB, the sense amplifier SA activates the activation signals SE1 (for minute signal amplification) (t4) and SE2.
(For high speed signal amplification) In response to (t5), FW data is amplified.

Here, the word line side digit lines D and DB
And the signal TG for separating the sense amplifier side digit lines D, DB from the digit lines D, DB by the signal SE1 input.
When the fine amplification of the above information amount is completed, the transfer gate is closed, the load on the sense amplifier SA is reduced, and high-speed differential amplification is executed.

The FW data buses FWBUS, FW
The BUS (overline) supplies data bits "1" and "0", respectively. By the way, at the time of the FW function, the FW data is not written to the memory cell MC only by the information amount from the FW data bus FWBUS, but is amplified by the sense amplifier SA to the selected word line WL. The current driving capability of the FW data bus driving amplifier required to rewrite the contents of all the connected memory cells MC is reduced, and the area and noise amount are increased as the transistor size is increased. This is to prevent it.

[0010]

However, in this conventional FW system, Re in a normal DRAM is
Since the dummy word line drops as in the ad / Write operation, the potential difference between the digit lines D and DB during FW greatly differs depending on the data already held, as shown in FIGS. For example, the difference between the potential difference between the digit lines 601 and the digit line 603 is the worst case of the example shown in FIG. The difference in the potential difference between the digit lines D and DB is due to the reduction of the mask design standard accompanying the improvement of the diffusion technique in recent years.
When 01 to 604 come close to each other, there is a problem that noise exerted by the adjacency effect cannot be ignored and normal differential amplification is not performed.

[0011]

SUMMARY OF THE INVENTION The gist of the present invention is to provide an array of memory cells, a plurality of digit line pairs connected to a column of memory cells, and a sense amplifier for amplifying a voltage difference on the digit line pairs. In a semiconductor memory device comprising a transfer gate for supplying flash write data to a plurality of digit line pairs during flash write and a reference level correction circuit connected to the digit line pairs and controlled by a dummy word signal generation circuit, the dummy The word signal generation circuit is to inactivate the reference level correction circuit during flash write.

[0012]

In the normal mode, the dummy word signal generation circuit activates the reference level correction circuit, but in the flash write, it inactivates it.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a dummy word signal generation circuit 100 included in one embodiment of the present invention. The other structure is the same as that of the conventional example shown in FIG. In this embodiment, when the semiconductor memory device enters the FW mode, the dummy word signal generation circuit 100 generates the FW mode flag signal generated only in the FW mode in order to reduce the difference in the potential difference between the digit lines in the FW mode. The control that suppresses the generation of the dummy word signal is performed by a signal that takes a logic with the FW mode flag signal.

As a result, as shown in FIGS. 2 and 3, no matter which data bit is held in the memory cells M100 to M104, the difference between the potential differences on the digit lines 201 to 204 caused by the previous restore cell data is reduced. Compared with the conventional example, the number is reduced, and the potential difference between the worst D and DB can be improved.

[0015]

As described above, according to the present invention, in the FW mode, the generation of the dummy word signal is prevented by the FW mode flag signal. The potential difference between different and worst digit lines can be improved. Therefore, the amount of noise exerted by the adjacency effect can be reduced, and normal differential amplification can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a dummy word signal generation circuit included in an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell and a digit line pair included in an embodiment of the present invention.

FIG. 3 is a waveform diagram showing a voltage on a digit line at the time of flash writing according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is an operation waveform diagram of a conventional example.

FIG. 6 is a circuit diagram showing a memory cell and a digit line pair of a conventional example.

FIG. 7 is a waveform diagram showing a voltage on a digit line during flash writing in a conventional example.

[Explanation of symbols]

 M100, M101, M102, M103 memory cell 201, 202, 203, 204 digit line pair 100 dummy word signal generation circuit SA sense amplifier 450 transfer gate 460 sense reference level correction circuit

Claims (1)

Claim: What is claimed is: 1. An array of memory cells, a plurality of digit line pairs connected to a column of memory cells, a sense amplifier for amplifying a voltage difference on the digit line pairs, and a flash write operation. In a semiconductor memory device comprising a transfer gate for supplying flash write data to a plurality of digit line pairs, and a reference level correction circuit connected to the digit line pairs and controlled by a dummy word signal generation circuit,
A semiconductor memory device, wherein the dummy word signal generation circuit inactivates a reference level correction circuit during flash write.