JPH0565891B2 - - Google Patents

Description

Claim 1: receiving an AC input signal through transformer operation;
and a secondary winding including a transformer core for producing an output; switching means; a feedback circuit responsive to the output of the secondary winding and including a clock having an inhibit input; and a timing circuit responsive to the clock. an inhibit circuit for disabling and enabling the inhibit input of the clock in response to the timing circuit; output means for providing a variable signal output to the switching means in response to the timing circuit; and a resonant winding that changes the magnetic properties of the transformer core in response to an AC input signal to provide a regulated output.

2. The ferro-resonant power supply of claim 1, wherein said timing circuit includes: a monostable circuit responsive to said clock; and a voltage charging network responsive to said monostable circuit.

3. The output means includes: an error amplifier responsive to the secondary winding output; and a comparator circuit responsive to the error amplifier and the timing circuit to provide a pulse width modulated output signal to the switching means. Ferro-resonant power supply described in scope 1.

4. The inhibit circuit is responsive to: a voltage reference circuit; the timing circuit and the voltage reference circuit; 2. A ferro-resonant power supply as claimed in claim 1, including a comparator circuit for providing said inhibit signal of said clock along with a signal disabling said clock at all other times.

[Industrial application field]

The present invention relates to ferro-resonant power supplies, and more particularly to ferro-resonant power supplies with closed feedback loops.

[Conventional technology]

Ferro-resonant transformers are line voltage (line voltage)
Widely used in (line voltage) regulators and DC power supplies. Ferro-resonant power supplies utilize the saturation characteristics of a transformer to adjust the output voltage to changes in the input line voltage. Secondary saturation ensures that the secondary voltage cannot rise above a certain value, independent of changes in the primary (input) voltage.

When the voltage level of the AC input to the ferro-resonant power supply reaches a certain voltage level, the core under the secondary winding saturates on each AC half-cycle. At the saturation point, the impedance of the saturating transformer (reactor) drops rapidly and capacitive current flows through the low impedance, carrying the capacitor charge to the opposite plate of the capacitor. As the capacitor discharges, it cannot sustain the saturation flux density of the secondary winding and the reactor snaps out of saturation. At this point, almost no capacitive current flows. A new half-cycle begins when voltage is applied again to the reactor for a sufficient period of time to begin saturation. The energy stored in the capacitor during each half cycle ensures that secondary saturation occurs over a wide range of loads. Even if the line voltage increases further beyond the saturation cut-in point, the increase is absorbed across the linear inductor. Therefore, the secondary voltage maintains a constant value even if the line voltage changes. A more detailed explanation of ferro-resonance and its application to regulator power supplies can be found in Marcel Detzker (1978).
(2013) can be found in "Transformer and Inductor Design Handbook" by William T. McClyman.

Standard ferro-resonant power supplies utilize core saturation to achieve line regulation. However, since the core is an adjustment element,
It is not possible to adjust for effects external to the core, such as frequency changes and losses in external wiring. Ferro-resonant power supplies can be modified to adjust to changes in frequency and load by adding a feedback control circuit to the ferro-resonant transformer. According to one such improvement, the transformer core never saturates. Instead, an AC switch connects an inductor in parallel with an AC capacitor,
Provides a low impedance discharge path for the capacitor. During a portion of each half cycle,
By closing the AC switch a fero-resonant discharge is simulated and the output voltage of the secondary winding can be varied as required with the feedback loop. This configuration is commonly referred to as a controlled fero-resonant power supply. However, this improvement results in increased loop gain and potential instability at constant frequencies. input
Sustained vibrations can be easily triggered by AC line voltage transients and rapidly changing load conditions.

The prior art teaches increasing stability by reducing the likelihood of sustained oscillations by lowering the ferro-resonant power supply output with the load. Such solutions to the instability problem are unsatisfactory. This is because a portion of the total available power output of the power supply must be consumed to provide stability. As much as 10% more output power than the available output may be required to ensure that the power supply does not oscillate. If this reduction in available output power was found to be unacceptable, an alternative to the prior art was to monitor the output voltage from the fero-resonant power supply with a control circuit to detect output instability. . When vibration occurs, the control circuitry "crowbars" the power supply. This solution is also insufficient. This is because this method may cut off the power supply at inopportune times. Furthermore, "crowbaring" or shutting off the ferro-resonant power supply does not solve the problem, but only serves as a safety mechanism to protect other equipment from damage caused by instability of the ferro-resonant power supply. . Therefore, there is a need for a controlled ferro-resonant power supply that can operate stably over a no-load to full-load range without consuming power output from the power supply or requiring power interruption.
FIG. 1 is a basic block diagram of a prior art controlled ferro-resonant power supply. constant frequency
An AC input signal is provided to the primary winding 11 of the transformer;
This primary winding 11 is magnetically coupled to a low voltage secondary winding 13 and a high voltage resonant winding 19 by the operation of a transformer. The resonant winding 19 consists of a winding wrapped around the saturated transformer core and a capacitor in parallel with the winding. This capacitor is generally referred to as a resonant capacitor, and together with the saturation transformer, it is responsible for the characteristic voltage-dependent resonance of the transformer. The low voltage secondary winding consists of windings wrapped around a saturated transformer core. The output of the low voltage secondary winding 13 is received by a full wave rectifier 15. Full wave rectifier 15
The rectified AC voltage from the filter network 1 has a conventional capacitive input.
7. The output of filter network 17 produces a low ripple DC voltage. Resonant winding 19 also includes an external linear inductor. The feedback circuit provides the required control signals to cause the linear inductor to appear in parallel with the high voltage resonant winding during a portion of each half cycle to simulate saturation in the transformer core.

In FIG. 1, compensation circuit 21 serves to provide sufficient gain and phase margin near the switching frequency of triac 29. An error amplifier 23 compares the output voltage of the power supply with a predetermined reference voltage 25 . The output of error amplifier 23 is a DC voltage representing the error between the current DC output voltage and the reference voltage.
The pulse width modulator 27 receives the DC signal from the error amplifier 23.
The voltage levels and the output from clock 33 are used to generate a pulse width modulated signal that turns triac 29 on and off. The triax 29 operates as a switch, electrically connecting the linear inductor to the resonant winding 19 in a shunt circuit. Synchronizer circuit 32 receives the output from full wave rectifier 15. The synchronizer circuit 32 determines the voltage magnitude of the signal from the full-wave rectifier 15.
, so it is compatible with the input to clock 33. Preferably, this clock 33 is a zero crossing detector clock. resonant winding 19;
The exact configuration and interaction of the triax 29 and the low voltage secondary winding 13 is well known to those skilled in the art of ferro-resonant voltage regulators and will not be dealt with in detail here.

Bleeder load 31 is the minimum load appearing across the DC output of the controlled fero-resonant (voltage regulator) power supply of FIG. Bleeder load 31 can be a simple device such as a high power resistor. The purpose of the bleeder load 31 is to maintain stable operation in the feedback loop of the controlled ferro-resonant power supply of FIG. 1 under no-load or light-load conditions. Bleeder load 31 also operates to stabilize the controlled ferro-resonant power supply under certain input transient conditions. The most troublesome of these load conditions is periodic AC line interruptions (line interruptions).
interrupts) and rapid load changes.

2 and 3 are schematic diagrams showing the component configuration blocks of the pulse width modulator 27 in the block configuration diagram of FIG. 1, and FIGS.
3 is a timing waveform diagram of input and output signals associated with the figure; FIG. FIG. 2 shows pulse width modulator 27 including timer 35 and comparator 37. FIG. Waveform A in Figure 3
shows signal A as the output of full wave rectifier 15 which provides an input signal to synchronizer circuit 32. Waveform B is the output of zero crossing detector clock 33. The output B of zero crossing detector clock 33 is used as a timing input to timer 35 of pulse width modulator 27. Timer 35 can be a simple RC network whose discharging and charging are synchronized with the output signal of zero crossing detector clock 33.
The output of timer 35 is the ramp voltage represented by waveform C in FIG. Timer 35 generates a ramp voltage output that is discharged each half cycle when the output clock output voltage falls below a predetermined threshold.

In FIG. 3, the ramp voltage portion of waveform C is the output of timer 35 sent to the positive input of comparator 37, while the DC voltage from the error amplifier output is sent to the negative input of comparator 37, which It is shown as a dashed line in C. The output of comparator 37 is shown in waveform D of FIG. This output is (first
It is a pulse width modulated waveform that serves to turn on and off the triax 29 (as shown symbolically in the figure). The specific designs of clock 33 and timer 35 are well known and conventional designs. Comparator 37 may be constructed in a known manner, but any suitable pulse width modulator technology may be used.

As the magnitude of the DC voltage from error amplifier 23 changes, the duty cycle of the output of comparator 37 changes correspondingly. Therefore, by changing the duty cycle of the output from the comparator 37 (waveform D in FIG. 3), the firing of the triax 29 can be changed;
Varying the time of simulated saturation for the transformer core. The low voltage secondary winding 13 can be controlled via transformer operation. This is the third
This can be easily determined by examining waveforms C and D in the figure. As the lamp voltage from timer 35 increases, it reaches a point where it becomes higher than the DC voltage from error amplifier 23 (this DC voltage is indicated by the dashed line in waveform C of FIG. 3). . At this point comparator 37
switches from a low state to a high state. When the lamp voltage discharges, comparator 37 changes from a high state to a low state because the DC error voltage is higher than the lamp voltage appearing at the positive input of comparator 37.

When the voltage at the DC output of a fero-resonant power supply changes,
produces a control feedback signal which changes the firing time of the triac 29 and thus changes the DC
Maintain the output at its desired voltage. As discussed above for the case without bleeder load 31, the ferro-resonant power supply, both with and without feedback control circuitry, operates under light, no-load or transient load conditions. If the main line voltage is interrupted or the primary line voltage is interrupted, unstable operation is likely to occur. Loading a bleeder circuit into a fero-resonant power supply consumes or sacrifices 10% or more of the total power that can be delivered to maintain stability under all normal operating conditions. This has a significant impact on the efficiency of the ferroresonant power supply, and increases the cost of its operation and manufacture, so it should not be controlled by any means other than bleed off a portion of the available output power. It is necessary to stabilize the ferro-resonant power supply.

[Problem to be solved by the invention]

It is an object of the present invention to provide a controlled ferro-resonant power supply that maintains operational stability against input line voltage transients and rapid changes in output load.

Another object of the invention is to provide a controlled fero-resonant power supply capable of stable operation without external loading.

[Means to solve the problem]

The configuration of the present invention is as shown below. That is,
The present invention comprises a secondary winding 13 comprising a transformer core that receives an AC input signal and produces an output by means of transformer operation; switching means 29; , a feedback circuit including a clock 39 having an inhibit input; and a timing circuit 2 responsive to said clock 39.
7, 41; an inhibit circuit 40 for disabling and enabling the inhibit input of the clock 39 in response to the timing circuits 27, 41; and a variable signal output G in response to the timing circuits 27, 41; output means 43 for providing to said switching means 29; and a resonant winding 19 for changing the magnetic properties of said transformer core in response to said switching output 29; It has a configuration as an iron-resonant power supply that provides

Alternatively, the timing circuits 27, 41
is a monostable circuit 41 responsive to the clock 39.
and a voltage charging network R2, C, T, R1 responsive to the monostable circuit 41.

Alternatively, the output means 43 includes: an error amplifier 23 responsive to the output of the secondary winding 13; and an error amplifier 23 responsive to the error amplifier 23 and the timing circuits 27, 41;
a comparator circuit 4 which provides a pulse width modulated output signal G to
It has a configuration as a ferro-resonant power source including 3.

Alternatively, the inhibition circuit 40 is responsive to the voltage reference circuit 25 and the timing circuits 27, 41 and the voltage reference circuit 25 to prevent the normal secondary winding 13 output signal from approaching an expected zero crossing. a comparator circuit 45 for providing the inhibit signal E of the clock 39 along with a signal that enables the clock 39 during times of , while disabling the clock 39 at all other times;
It has a configuration as a ferro-resonant power supply.

[Summary of the invention]

Briefly, the present invention is a controlled ferro-resonant power supply with improved feedback circuitry resulting in improved output stability. The controlled ferro-resonant power supply of the present invention includes a transformer, a low voltage secondary winding switch, a feedback circuit and a resonant winding circuit. A feedback circuit provides a variable output signal to activate the switch in response to the low voltage secondary winding output. A resonant winding circuit changes the magnetic properties of the transformer core in response to switch activation. The improved feedback circuit responds to the low voltage secondary winding output only during a portion of the frequency period of the AC signal input to the ferro-resonant power supply. The feedback circuit includes a synchronizer circuit and a clock responsive to the low voltage secondary winding output, a timing circuit responsive to the clock, and an output means responsive to the timing circuit. Since the timing circuit provides a signal to the clock's inhibit input in the time frame, the clock (and therefore the feedback circuit) is connected to the ferroresonant power supply.
It is activated only for a small time window during each half cycle of AC input.

[Brief explanation of the drawing]

Figure 1 shows closed-loop ferroresonance as a prior art
FIG. 3 is a block diagram of a DC power supply.

FIG. 2 is a circuit diagram of the prior art pulse width modulator of FIG.

FIG. 3 is a timing diagram of various signals associated with the circuit diagram of FIG. 2.

FIG. 4 is a block diagram of a controlled ferro-resonant power supply according to the present invention.

FIG. 5 is a circuit diagram of a portion of a feedback circuit for a controlled ferro-resonant power supply in accordance with the present invention.

FIG. 6A is a timing waveform diagram of various major signals associated with the pulse width modulator shown in FIG.

FIG. 6B is a comparison diagram of the two waveforms of FIG. 6A, the first waveform representing the input signal A to the feedback circuit of the ferro-resonant power supply shown in FIG. represents signal E defining the time window during which the feedback circuit of FIG. 5 is activated.

〔Example〕

FIG. 4 is a block diagram of a closed loop ferro-resonant power supply according to the present invention. With the exception of clock 33 of FIG. 1, the block diagram of FIG. 4 of the present invention is functionally the same as the block diagram of the prior art controlled ferro-resonant power supply of FIG. Accordingly, each component block in FIG. 4 is numbered the same as in FIG. 1, with the sole exception of the block 39. By modifying the operation of the clock 33 block of FIG. 1, the present invention eliminates the need for the bleeder load 31 block shown in FIG.

Clock 39 in FIG. 4 has an inhibit function responsive to a control signal from inhibit circuit 40. Clock 39 in FIG. This inhibit circuit 40 only allows clock 39 to respond to synchronization pulses from synchronizer circuit 32 during short time intervals that are very close in time to the expected synchronization pulses from synchronizer circuit 32. The ferro-resonant power supply according to the invention therefore rejects all spurious spurious synchronization pulses from the synchronizer circuit 32;
Only the synchronization signal with the correct problem is clock39
This high stability can be achieved by making it as recognized by Therefore, the closed loop ferro-resonant power supply of FIG. 4 does not require a minimum load to be maintained on the power supply output and corresponding power consumption. By eliminating this bleeder load, the ferro-resonant power supply of the present invention is free to send all of its available power to its output load. This has the effect of substantially increasing the operating efficiency and thus substantially reducing the operating cost of the controlled fero-resonant power supply of the present invention.

The controlled ferro-resonant power supply of FIG. 4 consists of five major building blocks. The first block is an input circuit consisting of the transformer primary winding 11 and the AC input signal. The second block is a secondary winding including a low voltage secondary winding 13, a full wave rectifier 15 and a filter network 17. The third main component block is a compensation circuit 21, an error amplifier 23, and a reference voltage 2.
5. A feedback network (circuit) consisting of a synchronizer circuit 32, a clock 39, a pulse width modulator 27 and an inhibit circuit 40. The building block of FIG. 4 is a switch including a triax 29. The fifth component block is the resonant winding 19.
This is a magnetic flux control circuit consisting of:

FIG. 5 is a circuit diagram of a portion of the feedback network of the ferro-resonant power supply of FIG.
The dashed block is the pulse width modulator 27 from FIG.
and the range of the suppression circuit 40 is shown in a limited manner. Clock 39 of FIG. 5 may be a zero-crossing detector clock that switches to a low state upon detecting a zero-crossing at its input. Excluding the inhibit input, clock 39 is the same as clock 3 in FIG. 2 of the prior art.
3 and is of a configuration well known to those skilled in the art. The output B of clock 39 of FIG. 5 is input to monostable circuit 41, also of conventional construction. In the preferred embodiment of the invention, this monostable circuit 41 is constructed from an operational amplifier in a manner well known to those skilled in the art.

The pulse width modulator 27 includes a timing network of a monostable circuit 41, a capacitor discharging transistor T, a capacitor C and a resistor R2, and has a characteristic charging rate defined by a time constant CR2. The timing network with time constant CR2 is charged via the reference voltage V _REF . The pulse output C of the monostable circuit 41 is sent to the base of the capacitor discharge transistor T via the resistor R1. The pulse output C from the monostable circuit 41 turns on the capacitor discharging transistor T, so that any voltage appearing across the capacitor C is discharged. The cathode of the capacitor C and the emitter of the capacitor discharging transistor T are both grounded. The collector of the capacitor discharge transistor T is connected to the anode of the capacitor C and the first terminal of the resistor R2. 2nd of capacitor C
The terminal is connected to a reference voltage V _REF . The signal at the anode of capacitor C serves as the input signal to comparator 43 and comparator 45. The reference voltage V _REF is connected to voltage divider networks R3 and R4.
is applied to the positive input of comparator 45 by. The negative input of comparator 45 receives the voltage from the anode of capacitor C. The output of the comparator 45 is connected to the protection diode D.
1 to the inhibit input of clock 39.
Comparators 43 and 45 are conventional comparators, preferably made from operational amplifiers. Comparator 43 is part of pulse width modulator 27 of FIG. 4 and has as its positive input the voltage on the anode of capacitor C and as its negative input the variable DC voltage from error amplifier 23. The output of comparison 43 is the fourth
This is a pulse width modulated signal used as a control signal for the triax 29 shown in the figure.

6A and 6B illustrate waveforms associated with the operation of the invention shown in FIG. Waveforms A-G of FIG. 6A appear at various inputs and outputs of the circuit components shown in FIG. Waveform A is the output from full-wave rectifier 15. Waveform A is a full wave rectified signal of the AC input to the transformer primary winding 11. Waveform A provides an input signal to clock 39 in FIG. Waveform B is the output signal from clock 39 in FIG. 5, and this output signal is output from monostable circuit 4 in FIG.
Serves as an input signal to 1. The output of monostable circuit 41 is waveform C. Waveform C is applied to the base of capacitor discharge transistor T in FIG. 5, enabling the lamps of waveforms D and F. Waveform D of FIG. 6A shows the two voltages applied to comparator 45 of FIG. 1st
The voltage is a ramp voltage created by reference voltage V _REF , resistor R and capacitor C in response to signal waveform C from monostable circuit 41 . The second signal is a steady DC reference voltage created by voltage divider networks R3 and R4. When the lamp input voltage applied to the comparator 45 becomes higher than the reference DC voltage, the output waveform E of the comparator 45 changes from a positive state to a negative state. This can be known by comparing waveform E and waveform D.

Waveform F in FIG. 6A shows two voltage signals at the inputs to comparator 43. Waveform F in FIG. Lamp voltage is comparator 4
This is the input to the positive input of No.3. The negative input of comparator 43 is supplied by a variable DC voltage from error amplifier 23 (shown in FIG. 4). As can be seen, the output of comparator 43, shown as waveform G in FIG. It changes suddenly.

Waveform A in FIG. 6A has several transient pulses present at the output of full wave rectifier 15. These transient pulses can appear in response to line interruptions to the power source or load transients. As can be seen by comparing FIG. 6A and FIG. 3, both the prior art circuit of FIGS. 1 and 2 and the circuit according to the invention shown in FIGS. However, the input waveform A is the same. As seen in waveform D of FIG. 3, the transients in waveform A produce undesirable effects on the output of prior art pulse width modulator 27.
This instability occurs because the pulses from the synchronizer circuit 32 to the prior art clock 33 of FIG. 2 become unstable when the ferro-resonant transformer begins to oscillate. Such unstable pulses cause the feedback circuit to respond out of step, locking the entire power supply into an uncontrollable sustained oscillation.

Waveform E of FIG. 6A provides an inhibit signal to clock 39 of FIG. This inhibit pulse prevents clock 39 from responding to false zero crossing detections caused by transient conditions. The period of operation of the square wave in waveform E of FIG. 6A is determined by the DC voltage level of the reference voltage input at the positive input of comparator 45. This can be easily seen by examining waveform D in FIG. 6A. Waveform E is generated by clock 39 of FIG.
Since it only releases the inhibited state, its short uninhibited period provides a time window during which the input to clock 39 is sensitive to its input signal (waveform A). Therefore, clock 39 is not sensitive to all transients on waveform A. In fact, if the operating period of waveform E is sufficiently high, the circuit of FIG.

FIG. 6B shows a comparison of waveforms A and E to better illustrate the time window during which clock 39 is able to examine its input voltage from full-wave rectifier 15. ing. The timing circuit removes the inhibit signal from the inhibit input of clock 39 only for a brief period of time near the expected zero crossing of the rectified AC signal. Transient zero crossings that occur during the time between zero crossings caused by transformer vibrations are ignored by the feedback circuit. This is because clock 39 is inhibited during all but a small portion of the rectified secondary voltage period. The charging time of the lamp voltage and the setting of the reference voltage to comparator 45 are adjusted so that the inhibit input to clock 39 is set to a desired interval close in time to the next expected zero crossing caused by the normal input signal. It is released only for a period of time.

In summary, the feedback circuit through the timing circuit, clock 39, and its inhibit input is:
It is operative to sample the output of the power supply in periodic time windows corresponding to expected zero crossings of the power supply output.

〔Effect of the invention〕

According to the ferroresonant power supply of the present invention, all false and spurious synchronization pulses from the synchronizer circuit are rejected,
High stability can be achieved by ensuring that only properly spaced synchronization signals are recognized by the clock. Therefore, the closed loop ferro-resonant power supply of the present invention does not require a minimum load to be maintained on the power supply output and corresponding power consumption. By eliminating this bleeder load, the ferro-resonant power supply of the present invention is free to send all of its available power to its output load. This has the effect of substantially increasing the operating efficiency and therefore substantially reducing the operating cost of the controlled fero-resonant power supply of the present invention.