JPH0563735A - Multilink processing unit - Google Patents

Abstract

PURPOSE:To implement multilink processing to a link employing an optional single link protocol. CONSTITUTION:Multilink processing units 1, 15 are provided with plural single link protocol circuits 2-1 to 2-3, 10-1 to 10-3 accommodating links 1-1 to 1-3, 9-1 to 9-3 according to the CCITT X.25 and with in-equipment common buses 4, 12 connecting the signal and multilink protocol circuits and plural address addition collation circuits 3-1 to 3-4, 11-1 to 11-4 located between the single and multilink protocol circuits and the in-equipment common buses and collating data on the in-equipment common buses with a destination address added thereto with its own address to fetch data, with repeater circuits 7-1, 7-2 connecting the in-equipment common buses 4, 12 and an in-equipment common bus 8, which connect the link of the single link protocol in the equipment and at the outside of equipment and the multilink protocol circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a multilink procedure (ML
P) That is, distributing a valid DTE or DCE single link procedure (SLP) packet sent to the data terminal equipment DTE or data circuit terminating equipment DCE, and receiving the packet received from the DTE or DCE SLP at the DTE or DCE packet level. The present invention relates to a multi-link processing device that realizes a function of reordering for transfer to a network.

[0002]

2. Description of the Related Art In a conventional multi-link processing device, as shown in FIG. 3, an S that accommodates SLP links 19-1 to 19-3 input to a multi-link processing device 19.
It is connected to the MLP circuit 22 via the LP circuits 20-1 to 20-3. MLP link 2 connected to MLP circuit 22
3 is output from the multilink processing device 19.

[0003]

In the above-mentioned conventional multi-link processing device, only the multi-link processing for a fixed SLP link is performed, an arbitrary SLP link cannot be selected, and the number of subscribers who receive the MLP service is increased. There is a problem that is not easy.

It is an object of the present invention to provide a multilink processing device capable of performing multilink processing on an arbitrary SLP link.

[0005]

The present invention is a CCITT
X. 25. In a multilink processing device for processing a multilink procedure according to 25, a plurality of single link procedure circuits respectively accommodating links of a single link procedure, a multilink procedure circuit accommodating links of a multilink procedure, Common bus in device connecting between the link procedure circuit and the multi-link procedure circuit, and a destination address is added between each of the single-link procedure circuit and the multi-link procedure circuit and the common bus. A plurality of address adding / verifying circuits for transmitting the data to the common bus and adding the destination address to the data on the common bus to collate the data with its own address, and the common bus within the device and the common bus between devices. And a repeater circuit for connecting between the link and the master of any of the single link procedures inside and outside the device. Connecting the Chirinku procedure circuit.

Therefore, the multilink processing device of the present invention, when sending from an arbitrary single link procedure (SLP) link to an arbitrary multilink procedure (MLP) circuit, S
The address addition / collation circuit connected to the LP circuit sends the SLP link data to which the destination MLP address is added to the common bus, and the address addition / connection connected to the plurality of MLP circuits connected to the common bus is performed. Data can be transmitted to an arbitrary MLP circuit by fetching data addressed to itself by the matching circuit and ignoring it if not addressed to itself. Conversely, data can be transmitted from any MLP circuit to any SLP circuit. In this way, it is possible to perform multilink processing on an arbitrary SLP link.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1 showing the configuration of an embodiment of the present invention, SLP circuits 2-1 to 2- that accommodate SLP links 1-1 to 1-3 input to a multilink processing device 1.
3 adds the address of the MLP circuit 5 as a destination address by the address adding / collating circuits 3-1 to 3-3, and also adds its own address as a source address to transfer data to the in-device common bus 4. send. The address adding / collating circuit 3-4 determines that the address is addressed to itself based on the destination address, and sends the data to the MLP circuit 5. In this case, the packet having MLP is the MLP circuit 5
SLP links placed under the control of the MLP circuit 5 are in the same device,
It is output from the LP link 6. On the other hand, since the multi-link processing device 15 has the same configuration as the multi-link processing device 1, an internal description will be omitted, but the multi-link processing device 1 and the same device 15 are different from the repeater circuits 7-1 and 7 in FIG. −
2 are connected by a common bus 8 between devices. In this way, the common buses 4 and 12 in the device are connected to the repeater circuits 7-1 and
The SLP circuit 2-1 accommodated in the MLP circuits 5 and 13 by connecting to the common bus 8 between devices via 7-2.
~ 2-3, 10-1 to 10-3 can be arbitrarily selected.

The frame structure is shown in FIG. 2, which is shown in FIG.
CCITTX. It has a flume structure of 25 level 2 and is composed of an address field A, a control field C, an SLP field by a data field DATA, and a frame check sequence FCS, and a flag F exists so as to wrap it. 2B shows a frame structure on the common buses 4, 8 and 12, and is composed of a destination address DA, a source address SA and the SLP described in FIG. 2A. 2C shows a frame structure on the MLP link, which includes the SLP described in FIG. 2A and has a multilink control field MLC. Regarding MLC, CCITT X. Details are given in 25 Recommendations.

[0010]

As described above, according to the present invention, the CCI
TT X. In the realization of the multi-link procedure (MLP) according to 25, the ML is implemented without being restricted by the mounting position of an arbitrary single-link procedure (SLP) link inside and outside the apparatus.
Connect to P circuit via common bus. Therefore, when sending from any SLP circuit to any MLP circuit, S
The data of the SLP link to which the destination MLP address is added is sent from the LP circuit to the common bus, and if it is the data destined for itself by the address addition / collation circuit among the plurality of MLP circuits connected on the common bus, it is taken in and addressed to itself. If not, it can be transmitted to any MLP circuit by ignoring it. On the contrary, data can be transmitted from any MLP circuit to any SLP circuit. As a result, it is possible to perform multilink processing on any SLP link, select any SLP link, and easily add subscribers to receive the MLP service.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a frame structure of the embodiment.

FIG. 3 is a configuration diagram showing a conventional example.

[Explanation of symbols]

1,15 Multilink processing device 1-1 to 1-3, 9-1 to 9-3 SLP link 2-1 to 2-3, 10-1 to 10-3 SLP circuit 3-1 to 3-4, 11 -1 to 11-4 Address addition / verification circuit (ADRF) 4,12 In-apparatus common bus 8 Inter-apparatus common bus 5,13 MLP circuit 6,14 MLP link 7-1, 7-2 Repeater circuit (RPT)

Claims (1)

[Claims] 1. CCITT X. 25. In a multilink processing device for processing a multilink procedure according to 25, a plurality of single link procedure circuits respectively accommodating links of a single link procedure, a multilink procedure circuit accommodating links of a multilink procedure, A common bus in the device connecting between the link procedure circuit and the multi-link procedure circuit, and a destination address added between each of the single-link procedure circuit and the multi-link procedure circuit and the common bus. A plurality of addresses are added to fetch the data by collating the data on the common bus, which is transmitted to the common bus and to which the destination address is added, with its own address.
A collation circuit and a repeater circuit for connecting the intra-device common bus and the inter-device common bus are provided, and the arbitrary single-link procedure link inside and outside the apparatus and the multi-link procedure circuit are connected. A multi-link processing device characterized by: