JPH0563068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic noise reduction device using field correlation, which stops cyclic noise reduction at least during an equivalent pulse period.

[Prior Art] A magnetic recording/reproducing apparatus 1 shown in FIG. 2 uses a luminance system that emphasizes high-frequency components during signal recording in order to remove triangular noise, which is characteristic of frequency modulation/demodulation methods and increases as the frequency increases. A method is adopted in which the high-frequency emphasis of the signal is canceled by the de-emphasis circuit 2 when the signal is reproduced. That is, the reproduction outputs of the pair of magnetic heads 3a and 3b with different azimuths are supplied to the demodulator 5 via the reproduction amplifier circuit 4, and the luminance signal is FM demodulated and then sent to the low frequency circuit 6 via the de-emphasis circuit 2. It is designed to remove unnecessary components there.

However, since the luminance signal that has passed through the de-emphasis circuit 2 also contains noise, a cyclic noise reduction device 7 shown in the same figure is connected to the low frequency circuit 6 to reduce noise by using the field correlation of the video signal. It is designed to do so. The cyclic noise reduction device 7 suppresses noise components by utilizing the difference in properties between a video signal with high field correlation and a noise component with no field correlation. It is called cyclic type because it is added to the input video signal Vi(t) cyclically with a delay. Input video signal
Vi(t) is supplied to an adder 10 via a coefficient multiplier 9 with a coefficient of 1-K. Then, from the adder 10, an output video signal Vo(t) with reduced noise contained in the input video signal Vi(t) is taken out, while an integer line period (262 or 263 lines) that is closest to one field period is Due to signal delay, delay device 8
Supply to the delay digital memory 12 is performed in parallel via the AD converter 11 in the internal circuit. The delay digital memory 12 has a time difference τ between writing and reading RAM (random read-out memory).
gives a delay time, and the data read from it passes through the DA converter 13, so the delay device 8 outputs an analog delayed output video signal.
Vo(t-τ) is output. The delayed output video signal Vo(t-τ) obtained in this way is further processed by a coefficient multiplier 9.
KVo(t-
τ) to the adder 10, where it is added to the input video signal Vi(t).

Therefore, the output video signal Vo(t) is expressed as (1-K)Vi(t)+KVo(t-τ), where the input video signal Vi(t) and the delayed output video signal Vo(t-τ) The sum of signals obtained by multiplying K by a complementary coefficient 1-K whose sum value is 1 becomes the output video signal Vo(t). In this case, it is known that as the coefficient K of the coefficient unit 9 approaches 1 and the number of fields subject to correlation increases, a higher SN ratio improvement can be obtained. The closer it gets to , the better the SN ratio improves, but as the number of fields subject to correlation increases, afterimages become more noticeable for fast-moving videos. For this reason, an appropriate coefficient value K is normally selected depending on the degree of deterioration of the original video signal.

By the way, when the delay digital memory 12 is used as a delay means in the cyclic noise reduction device 7 as in this example, the delay digital memory 12
In general, an operation clock that is an integral multiple of the horizontal synchronization signal is required as an operation clock for data writing and reading, or for the AD converter 11 and DA converter 13 before and after that. In the case of this example, as a circuit for generating this operating clock, a synchronous separation circuit 15 is connected to the low-frequency circuit 6 at the front stage of the cyclic noise reduction device 7.
The operating clock generating circuit 16, which operates using the horizontal synchronizing signal obtained from the reference signal as a target value, is configured to obtain the required operating clock by multiplying the horizontal frequency using a phase-locked loop. In this example, the operating clock generation circuit 16 includes a phase comparison circuit 18 that compares the phases of the horizontal synchronization signal separated by the synchronization separation circuit 15 and the signal obtained by dividing the operating clock by the 1/N frequency divider circuit 17. , a low-frequency circuit 19 that removes harmonic components contained in the error output of the phase comparison circuit 18, and a voltage-controlled oscillator 20 that oscillates at a frequency corresponding to the error output that has passed through the low-frequency circuit 19. The oscillation output of the voltage controlled oscillator 20 is supplied to the delay device 8 as an operating clock, while being fed back to the phase comparator circuit 18 via the 1/N frequency divider circuit 17.

The luminance signal that has passed through the cyclic noise reduction device 7 is frequency-converted and reproduced in the demodulator 5, and is added to the color signal in an adder 21, and is sent to the outside via an amplifier circuit 22 as a reproduced video signal. is output to.

[Problems to be Solved by the Invention] The conventional cyclic noise reduction device 7 described above is configured to perform cyclic noise reduction using field correlation, but the delay digital memory 12 in the delay unit 8
However, in reality, in order to perform a delay of an integer line period as close as possible to one field period, strictly speaking, the vertical synchronization signal included in the video signal is such that the one delayed by the delay device 8 and the one before the delay are 1 As a result of being added by the adder 10 with a shift of /2 line period,
Regarding the vertical synchronization signal, cyclic noise reduction had the opposite effect, causing problems such as a blunting of the signal waveform and a tendency to disrupt the synchronization of the reproduced image. In addition, in the playback signal of a home VTR, the phase of the horizontal synchronization signal of the current field and the next field may be shifted, and the operation clock generation circuit 16
It takes time for the phase-locked loop to lock, and it may extend beyond the equivalent pulse period of the video signal and reach the video period. If the cyclic noise reduction device is operated in such a state, the video signals are added with a shift in the horizontal direction, which results in disturbing the video.

[Means for Solving the Problems] The present invention solves the above problems, and provides a video signal obtained by delaying a video signal using a delay device having a delay time of an integer line period as close as possible to one field period. A cyclic noise reduction device that cyclically reduces noise contained in a video signal by adding a pre-delayed video signal to a delayed video signal and then subjecting the signal to delay by the delay device again. The equalization pulse period includes addition stop means for stopping addition of the delayed video signal, and the delay device performs a delay operation according to an operation clock generated by a phase-locked loop that follows a horizontal synchronization signal in the video signal. The addition stop means is configured to stop addition of the delayed video signal for a period until the error output in the phase-locked loop stabilizes below a certain value. It is something to do.

[Operation] The present invention eliminates noise signals contained in video signals by
The addition of the delayed video signal to the video signal, which is the basis of reduction using the presence or absence of field correlation, is stopped at least during the equalization pulse period of the video signal, and the vertical synchronization signal having no field correlation is By adding these signals together, the vertical synchronization signal waveform becomes dull and the synchronization of the reproduced image is prevented from being disturbed. By stopping the addition of the delayed video signal, it is possible to prevent the cyclic noise reduction from having the opposite effect and disturbing the video.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1. FIG. 1 is a circuit diagram showing an embodiment of a cyclic noise reduction device of the present invention.

In FIG. 1, a cyclic noise reduction device 11 has a synchronous separation circuit 15 that supplies a horizontal synchronization signal to an operating clock generation circuit connected to the input side of an adder 21, and performs cyclic noise reduction processing. The operating clock is generated based on a horizontal synchronizing signal that is less contaminated by noise in the reproduced video signal. Note that it is also possible to connect the synchronous separation circuit 15 to the output side of the low frequency circuit 6 as before.
The connection point of the synchronous separation circuit 15 in this case is not directly related to the gist of the present invention.

In addition, in order to stop cyclic noise reduction for vertical synchronization signals for which no field correlation can be obtained, an equivalent pulse period detection circuit 22 connected to the synchronization separation circuit 15 detects the equivalent pulse period from the delayed output video signal.
The configuration is such that the output of Vo(t-τ) is stopped. That is, the equivalent pulse period detection circuit 22 is
During the equivalent pulse period, set K to 0 so that the coefficients 1-K and K of coefficient multipliers 9 and 14 become 1 and 0, respectively.
It acts to force Therefore, during the equivalent pulse period, the signal supply from the DA converter 13 to the adder 10 is stopped, thereby stopping the addition of the delayed output video signal Vo(t-τ) to the input video signal Vi(t). , cyclic noise reduction would also be interrupted. In this embodiment, the equivalent pulse period detection circuit 22 constitutes addition stopping means. Further, the error output in the phase-locked loop of the operating clock generation circuit 16 is taken out by the voltage comparator 33 and input to the coefficient multipliers 9 and 14 through the OR circuit 34, so that the error output in the phase-locked loop is stabilized below a certain value. Until then, it operates as an addition stop means.

In this way, the cyclic noise reduction device 31
During the equivalent pulse period and until the error output in the phase-locked loop stabilizes below a certain value, the addition of the delayed output video signal Vo(t-τ) to the input video signal Vi(t) is stopped. , it is possible to prevent deterioration of the vertical synchronization signal waveform due to the addition of vertical synchronization signals with no field correlation,
This makes it possible to easily and reliably avoid deterioration of the vertical synchronization signal, which is a problem in cyclic noise reduction processing using field correlation using the delay digital memory 12.

In addition, in the above embodiment, in order to stabilize the pull-in operation in the phase-locked loop in the operating clock generation circuit 16, the coefficient switching period by the equivalent pulse period detection circuit 32 is extended, and the phase jump of the synchronization signal in the video signal is The delayed output video signal by the delay device 8, including the period until the error output in the phase-locked loop stabilizes below a certain value.
It is also possible to configure the output of Vo(t-τ) to be stopped. In this case, the operating clock generating circuit 16 generates the operating clock for the delay device 8 based on the horizontal synchronizing signal with less noise pollution, and also during the base period until the error output in the phase-locked loop stabilizes below the above-mentioned constant value. Since stable operation is guaranteed, better cyclic noise reduction is possible.

Furthermore, the addition of the delayed output video signal Vo(t-τ) to the input video signal Vi(t) can be stopped by a method other than changing the coefficient values in the coefficient units 9 and 14.
For example, an on-off switch (not shown) that is normally closed is provided between the adder 10 and the coefficient unit 14,
It is also possible to do this by opening this on/off switch.

[Effects of the Invention] As explained above, the present invention solves the problem of adding a delayed video signal to a video signal, which is the basis for reducing a noise signal included in a video signal by utilizing the presence or absence of field correlation. Since it is configured to stop at least during the equalization pulse period of the video signal,
By adding vertical synchronization signals that have no field correlation, it is possible to prevent the vertical synchronization signal waveform from becoming dull and the synchronization of the reproduced image to be disrupted, further enhancing the effect of cyclic noise reduction using field correlation. It has excellent effects such as:

Further, in the present invention, the delay device performs a delay operation according to an operation clock generated by a phase-locked loop that follows a horizontal synchronization signal in a video signal, and furthermore, the error output in this phase-locked loop is kept below a certain value. By stopping the addition of the delayed video signal to the video signal until the video signal stabilizes, it is possible to generate the operating clock of the delay device based on the horizontal synchronization signal separated from the video signal that has undergone cyclic noise reduction. In such a case, it is possible to stably supply the operating clock, thereby stabilizing the delay operation by the delay device, and achieving even better cyclic noise reduction.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of a cyclic noise reduction device of the present invention, and FIG. 2 is a circuit configuration diagram showing an example of a conventional cyclic noise reduction device. 8...Delay device, 31...Cyclic noise reduction device,
32... Equivalent pulse period detection circuit.

Claims (1)

[Claims] 1. Delaying a video signal by a delay device having a delay time of an integer line period as close as possible to one field period, adding the obtained delayed video signal to the video signal before delay, and then subjecting the signal to delay by the delay device again. The cyclic noise reduction device cyclically reduces noise contained in a video signal, the device comprising an addition stop means for stopping addition of the delayed video signal during at least an equivalent pulse period of the video signal, The circuit is composed of a delay digital memory that performs a delay operation according to an operating clock generated by a phase-locked loop that follows a horizontal synchronization signal in a video signal, and the addition stop means is arranged so that the error output in the phase-locked loop is A cyclic noise reduction device characterized in that the addition of the delayed video signal is stopped for a period until the signal stabilizes below a certain value.