JPH056265A - Digital multiplication circuit - Google Patents

Abstract

PURPOSE:To reduce current consumption during the operation of the used CMOS type digital multiplier and to reduce power consumption in the entire digital multiplication circuit as well. CONSTITUTION:A zero discriminating means 10 discriminates that the value of a multiplier X or a multiplicand Y is zero at least. When the zero discriminating means 10 discriminates that the value is zero, a timing means 12 stops calculation at a CMOS type digital multiplier 20. When the zero discriminating means 10 discriminates that the value is zero, a multiplied result zero means 14 forcedly turns the multiplied result to zero. Therefore, when the value of the multiplier X or the multiplicand Y is zero at least, no calculation is executed at the CMOS type digital multiplier 20 with large power consumption. Thus, the power consumption in the entire digital multiplication circuit can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplication circuit using a CMOS type digital multiplier for inputting a binary number multiplier and a binary multiplicand and outputting a multiplication result of the multiplier number and the multiplicand. In particular, the present invention relates to a digital multiplication circuit capable of reducing power consumption.

[0002]

2. Description of the Related Art Currently, serial-parallel type multipliers and parallel type multipliers are known as digital multipliers for inputting a binary number multiplier and a binary number multiplicand and outputting a multiplication result of the multiplier number and the multiplicand. Has been.

Some serial-parallel type multipliers use, for example, a full adder for the number of bits of the multiplicand, input a multiplier bit by bit, and sequentially add and shift the multiplication results. Further, this serial-parallel type multiplier uses a full adder for the number of bits of the multiplicand, shifts the multiplier in the shift register, inputs one bit at a time for multiplication, and sequentially adds the multiplication results at this time. In some cases, the final multiplication result is obtained by

The parallel type multiplier includes, for example, a parallel multiplier unit circuit, which is composed of an AND circuit for obtaining a partial product and a full adder for obtaining a partial sum, arranged in an array.

Such a digital multiplier is constructed by using many gate circuits.

In particular, as the number of bits of the multiplier and the number of bits of the multiplicand increase, the number of gates used becomes very large,
This increases the power consumption of the digital multiplier and the entire digital multiplier circuit using the digital multiplier.

In recent years, in order to reduce the power consumption of such a digital multiplication circuit, CMOS (complementary metal-
CMOS using oxide-semiconductor process technology
Type digital multipliers have been developed.

This CMOS type digital multiplier consumes almost zero power when it is not performing calculations.

FIG. 11 is a logic circuit diagram of a conventional digital multiplication circuit using a CMOS type digital multiplier.

In FIG. 11, the CMOS type multiplier 2
0 is a parallel type multiplier that multiplies a 4-bit binary number multiplier X and a 4-bit binary number multiplicand Y.

In the digital multiplication circuit shown in FIG. 11, the D-type flip-flop F that holds the multiplier X (X0 to X3) during the calculation in the CMOS type multiplier 20.
X0 to FX3 and D holding the multiplicand Y (Y0 to Y3)
Type flip-flops FY0 to FY3 are used.

The multiplication result z (z0 to z7) from the CMOS type multiplier 20 is the D type flip-flop FZ0.
Up to FZ7, the output of the next multiplication result z (z0 to z7) is held.

The D-type flip-flops FX0 to FX3
Hold the multipliers X0 to X3 at the positive edge of the clock CK (rising from the L state to the H state),
The multipliers x0 to x3 are output to the CMOS type multiplier 20, respectively.

The D-type flip-flops FY0 to FY3
Hold the multiplicands Y0 to Y3 at the positive edge of the clock CK and output the multiplicands y0 to y3 to the CMOS type multiplier 20.

The D-type flip-flops FZ0 to FZ7
Are C at the positive edge of the clock CK.
The multiplication results z0 to z7 output from the MOS type multiplier are held, and the multiplication results Z0 are respectively stored as final operation results.
~ Outputs Z7.

FIG. 12 is a time chart of the above-mentioned conventional digital multiplication circuit.

In FIG. 12, the clock CK, the multiplier X (X0 to X3), the multiplicand Y (Y0 to Y3), and the multiplier x (x0 to x3) described above with reference to FIG. Multiplicand y (y 0 to y 3) and multiplication result z (z 0 to z 7)
, Multiplication result Z (Z0 to Z7), and CMOS type multiplier 2
The mutual timing relationship with the consumption current (absolute value) of 0 is shown.

In FIG. 7, the n-th clock CK
Multiplier X0 to X3 at the positive edge of the first pulse
Are held in the D-type flip-flops FX0 to FX3, respectively.

At this time, the multiplicands Y0 to Y3 are also held in the D-type flip-flops FY0 to FY3.

Thereafter, by the negative edge (falling from the H state to the L state) of the (n-1) th pulse of the clock CK, the outputs of the D-type flip-flops FX0-FX3 are respectively at the (n-1) th pulse. It outputs the (n-1) th multiplier x0 to x3 according to the th multiplier X0 to X3.

At this time, the D-type flip-flop FY
0 to FY3 are the n-1th multiplicand Y, respectively.
According to 0 to Y3, the (n-1) th multiplicands y0 to y3 are output.

When the outputs of the D type flip-flops FX0 to FX3 and FY0 to FY3 change according to the held bit data, the output of the CMOS type multiplier 20 changes accordingly.

By the positive edge of the nth pulse of the clock CK, the nth-1th of the CMOS type multiplier 20 is
The outputs of the th multiplication result z 0 to z 7 are determined.

Further, the D-type flip-flop FZ0 is provided at the positive edge of the nth pulse of the clock CK.
-FZ7 hold multiplication results z0-z7, respectively, and thereafter output multiplication results Z0-Z7, respectively.

As shown at the bottom of FIG. 12, the current consumption of the CMOS type digital multiplier 20 is almost zero in the vicinity of the positive edge of the clock CK where the multiplication results z0 to z7 are fixed. ..

As described above, by using the CMOS type digital multiplier using the CMOS process technology as the digital multiplier of the digital multiplication circuit, it is possible to reduce the power consumption.

[0027]

However, even if the digital multiplier is constructed by using the CMOS process technology as described above, the power consumption during the calculation of multiplication according to the input multiplier and multiplicand is reduced. It cannot be reduced significantly.

For example, as shown at the bottom in FIG. 12, the consumption current of the CMOS type digital multiplier 20 is calculated according to the input multipliers x0 to x3 and the multiplicands y0 to y3. It has a peak near the negative edge of the clock CK.

FIG. 2 is a circuit diagram of an example of a CMOS type gate forming a CMOS type digital multiplier, that is, a CMOS type inverter gate.

In FIG. 2, the CMOS type inverter gate is composed of a P channel MOS transistor TP and an N channel MOS transistor TN.

In FIG. 2, the input signal voltage Vi is applied to the input portion A. An output signal voltage Vo is output from the output portion B.

When the input signal voltage Vi is in the L state, that is, 0V, the P channel MOS transistor TP is turned on and the N channel MOS transistor TN is turned off.

Therefore, the output signal voltage Vo at this time is
The H state, that is, the power supply voltage VDD is reached, and the electrostatic capacitance C is charged with electric charges.

On the other hand, when the input signal voltage Vi is in the H state, that is, the power supply voltage VDD, the P channel MOS transistor TP is turned off and the N channel MOS transistor TN is turned on.

Therefore, the output signal voltage Vo at this time is
It becomes almost 0 V, and the electric charge stored in the electrostatic capacitance C is discharged.

Reference numeral I1 is a current flowing through the power supply side transistor, that is, the P-channel MOS transistor TP. Reference numeral I2 is a current flowing through the ground side transistor, that is, the N-channel MOS transistor TN. Reference numeral I is an output current flowing from the output portion B to the electrostatic capacitance C.

The capacitance C is the sum of the wiring capacitance and the gate input capacitance of the next stage, which is the load on the output portion B of the inverter gate.

FIG. 3 is a graph of the voltage and current of each part of the CMOS type inverter gate described above with reference to FIG. 2 according to the elapsed time.

In the graph of FIG. 3, as described above with reference to FIG.
Input signal voltage Vi, output signal voltage Vo, power supply side transistor current I1, and ground side transistor current I2
And a graph according to the elapsed time of the output current I is shown.

In FIG. 3, immediately after the positive edge of the input signal voltage Vi, a discharge current id flowing from the capacitance C to the N-channel MOS transistor TN is generated in the ground side transistor current I2.

The discharge current id is a current for causing the charge stored in the electrostatic capacitance C to flow into the N-channel MOS transistor TN because the output signal voltage Vo changes from the power supply voltage VDD to 0V.

Immediately after the positive edge of the input signal voltage Vi, the power supply side transistor current I1 is
A through current ik flows.

This through-current ik is a current which is generated in a short time immediately after the positive edge of the input signal voltage Vi and is caused by both the P-channel MOS transistor TP and the N-channel MOS transistor TN being turned on. is there.

On the other hand, at the negative edge of the input signal voltage Vi, the power supply side transistor current I1 is set as the charging current.
ic flows.

This charging current ic has an output signal voltage Vo of 0.
In order to change from V to power supply voltage VDD, P channel M
This is a current for generating a charging current from the OS transistor TP to the electrostatic capacitance C.

At the negative edge of the input signal voltage Vi, a through current ik flows as the ground side transistor current I2.

This through current ik is a current generated when both the P-channel MOS transistor TP and the N-channel MOS transistor TN are turned on in a short time immediately after the negative edge of the input signal voltage Vi.

The output current I flowing from the output portion B to the electrostatic capacitance C is the sum of the power source side transistor current I1 and the ground side transistor current I2.

The output current I is the input signal voltage Vi.
Immediately after the positive edge of
The positive peak immediately after the negative edge of the input signal voltage Vi.

As described above, in the CMOS type gate such as the CMOS type inverter gate, the consumption current reaches its peak when the output changes.

Therefore, the CMOS type multiplier using such a CMOS type gate generates current consumption during the operation,
In the steady state, the current consumption is almost zero.

The present invention has been made in order to solve the above-mentioned conventional problems. A C which inputs a multiplier of a binary number and a multiplicand of the binary number and outputs a multiplication result of the multiplier and the multiplicand is output.
In a digital multiplication circuit using a MOS digital multiplier, it is possible to reduce the current consumption of the CMOS digital multiplier during the calculation of multiplication according to the multiplier and the multiplicand, and thus the consumption of the entire digital calculation circuit. An object of the present invention is to provide a digital multiplication circuit capable of reducing the amount of power.

[0053]

According to the present invention, there is provided a digital multiplication circuit using a CMOS digital multiplier for inputting a binary number multiplier and a binary multiplicand and outputting a multiplication result of the multiplier and the multiplicand. , Zero discriminating means for discriminating that at least one of the multiplier and the multiplicand is zero, and if the zero discriminating means discriminates zero, the multiplication result is forcibly set to zero. The above-described object is achieved by providing a multiplication result zero means and a timing means for stopping the calculation in the CMOS type digital multiplier when the zero determination means determines that the result is zero. is there.

[0054]

In the present invention, the above-mentioned C, which has been described with reference to FIGS.
This is done by paying attention to the characteristic of the CMOS type gate that constitutes the MOS type digital multiplier regarding the current consumption.

The invention was made by analyzing the nature of the operation of multiplication.

That is, in the multiplication of the multiplier and the multiplicand,
This is done by finding that the multiplication result becomes zero when the value of at least one of the multiplier and the multiplicand is zero, without any calculation.

FIG. 1 is a block diagram showing the gist of the present invention.

In FIG. 1, the CMOS type digital calculator 20 performs a multiplication operation on a multiplier X and a multiplicand Y and outputs a multiplication result Z.

The zero discriminating means 10 discriminates that at least one of the multiplier X and the multiplicand Y is zero.

When the zero discriminating means discriminates that the timing is zero, the timing means 12 stops the operation in the CMOS type digital multiplier.

The multiplication result zero means 14 forcibly sets the multiplication result Z to zero when the zero judgment means determines that the multiplication result is zero.

This is because when the value of at least one of the multiplier X and the multiplicand Y is zero, the value "0" of the multiplication result Z can be obtained without performing the calculation in the CMOS digital multiplier 20. Because you can.

In the present invention, the zero discriminating means 10, the timing means 12, and the multiplication result zero means 14 must be newly provided.

However, the number of gates used in these newly provided structures is much smaller than the number of gates used in the CMOS digital multiplier 20.

Therefore, even if the present invention is provided with such a new structure, the problems such as the increase in the current consumption and the decrease in the integration degree due to the new structure are extremely small.

On the other hand, according to the present invention, the multiplier X and the multiplicand Y
If the value of at least one of the two is zero, the current consumption can be reduced because the CMOS digital multiplier 20 using a large number of CMOS gates does not perform the operation.

Particularly, in the field where the value of at least one of the multiplier and the multiplicand is zero, it is relatively frequent, and when a large number of digital multiplication circuits to which the present invention is applied are used, the power consumption of the entire electronic circuit is increased. The amount can be effectively reduced.

The zero discriminating means of the present invention may discriminate only that the value of the multiplier X is zero, or discriminate only that the value of the multiplicand Y is zero. May be. This is because even a digital multiplication circuit using such a zero determination means can effectively reduce power consumption depending on the field of use of the digital multiplication circuit. That is, when the frequency of only the value of the multiplier X is zero, or the frequency of only the value of the multiplicand Y is zero, etc., the action and effect of the present invention can be detected even by such zero determination means. be able to.

The multiplication result zero means 14 of the present invention is
It may operate according to the output of the zero determination means 10, or may operate according to the output of the timing means 12, that is, indirectly according to the output of the zero determination means 10.

[0070]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a logic circuit diagram of an embodiment of the present invention.

In FIG. 4, reference numeral 20, FX0-F
X3, FY0 to FY3, FZ0 to FZ7, X0 to X3,
x0 to x3, Y0 to Y3, y0 to y3, Z0 to Z7, z
0 to z7 and CK are the same as those having the same reference numerals in FIG.

The digital multiplication circuit to which the present invention is applied in FIG. 4 is particularly provided with a zero discriminating means 10, a timing means 12, and a multiplication result zero means 14.

The zero discriminating means 10 comprises a total of two 4-input NOR gates 10a and 10b and one NOR gate 10c.

The 4-input NOR gate 10a has multipliers X0 to X0.
When X3 is all in the L state, the output is in the H state.

The 4-input NOR gate 10b has a multiplicand Y0.
When Y3 are all in the L state, the output is in the H state.

The output of the NOR gate 10c receiving the outputs of the 4-input NOR gate 10a and the output of 10b is in the L state when at least one of the multiplier X and the multiplicand Y is zero. ..

The timing means 12 includes two Ds in total.
Type flip-flops 12a and 12b and AND gate 1
2c, an inverter gate 12d, and a delay element 12e.

Inverter gate 12d and delay element 1
2e is a signal a which is the delayed and inverted clock CK.
Is output.

The total delay time of the inverter gate 12d and the delay element 12e is the clock CK.
This is about 1/4 of the cycle.

The D-type flip-flop 12a holds the output of the NOR gate of the zero discriminating means 10 at the positive edge of the signal a and outputs it as the signal c.

The AND gate 12c outputs a logical product of the signal c and the clock CK as a signal d.

The D flip-flop 12b holds the state of the signal c at the positive edge of the signal a and outputs it as the signal e.

Therefore, this D-type flip-flop 12b
The signal e output by is the D-type flip-flop 12 described above.
The signal c output by a is delayed by one cycle of the signal a. That is, at the positive edge of signal a, the state of signal c shifts to signal e.

The signal d output from the timing means 12 is the D-type flip-flops FX0 to FX3 and F.
Input to Y0 to FY3.

This signal d is substantially the same as the clock CK when the value of the multiplier X and the value of the multiplicand Y are not zero. Therefore, in this case, the D-type flip-flops FX0 to FX3, FY0 to FY3, and the CMOS type multiplier 20 perform almost the same operation as the digital multiplying circuit of FIG.

On the other hand, when the value of at least one of the multiplier X and the multiplicand Y is zero, the signal d is in the L state. Therefore, in this case, the D-type flip-flop FX
The outputs of 0 to FX3 and FY0 to FY3 do not change even if the values of the multiplier X and the multiplicand Y change, and the CMOS multiplier 20
Consumes almost zero current.

The signal e output from the timing means 12 is input to the multiplication result zero means 14 which is composed of a total of eight AND gates.

The signal e is in the L state when at least one of the multiplier X and the multiplicand Y has a value of zero, and accordingly, the multiplication result Z or ZA having a value of zero is output.

Therefore, at this time, each AND gate of the multiplication result zero means 14 has the CMOS type multiplier 2
The multiplication results ZA0 to ZA7 in the L state are output regardless of the respective logic states of the multiplication results z0 to z7 output by 0.

The multiplication results ZA0 to ZA7 output from the multiplication result zero means 14 are input to a total of eight D-type flip-flops FZ0 to FZ7.

FIG. 5 is a time chart of each signal according to the embodiment of the present invention.

In FIG. 5, the clock CK, the signals a to e, and the multiplier X (X0 to X) shown in FIG.
3), multiplicand Y (Y0 to Y3), multipliers x0 to x3, multiplicands y0 to y3, multiplication results z0 to z7, multiplication results ZA0 to
A time chart of ZA7, multiplication result Z (Z0 to Z7, and current consumption of the CMOS type multiplier 20 is shown.

In the time chart of FIG. 5, the nth
-2nd to nth + 5th multiplier X (X0 to X3) and n-2nd to nth + 5th multiplicand Y (Y0 to Y
In 3), only the value of the n-th multiplier X (X0 to X3) is zero.

Therefore, the nth multiplication result ZA0 to ZA
The values of 7 and the n-th multiplication result Z0 to Z7 are zero.

In the digital multiplication circuit of this embodiment, the multiplier X
When both the multiplicand Y and the multiplicand Y are not zero, the signal d input to each of the D-type flip-flops FX0 to FX3 and FY0 to FY3 is substantially the same as the clock CK.

Further, when both the multiplier X and the multiplicand Y are not zero in this way, the signal e is in the H state, and the multiplication results ZA0 to ZA7 output from the multiplication result zero means 14 are output.
Are equal to the logical states of the multiplication results z0 to z7 output from the CMOS type multiplier 20, respectively.

Therefore, in the digital multiplication circuit of this embodiment, when the multiplier X and the multiplicand Y are not zero, the multiplier X, the multiplicand Y, the multiplier x, the multiplicand y, and the multiplication result z.
, And the timing of the multiplication result Z (= multiplication result ZA) is substantially the same as the timing of the same reference sign in FIG. 12 described above.

On the other hand, in the digital multiplication circuit of this embodiment,
When at least one of the multiplier X and the multiplicand Y has a value of zero, for example, in the case of the nth multiplier X having a value of zero in FIG. 5, the operation peculiar to the present embodiment is performed, and C
The current consumption of the MOS type multiplier 20 can be reduced.

In the time chart of FIG. 5, the nth
For the n th multiplier X (having a value of zero) and the n th multiplicand Y, the signal b 1 output from the zero discriminating means 10 is in the L state.

Further, the D-type flip-flop 12a which inputs the signal b holds the L state of the signal b at the positive edge of the nth pulse of the signal a and outputs the signal c in the L state.
Is output.

When the signal c is in the L state, the signal d output from the AND gate 12c is always in the L state regardless of the state of the clock CK.

Therefore, the n-th multiplier X whose value is zero
And the nth multiplicand Y are multiplied, the D-type flip-flops FX0 to FX3 use the nth-1th multiplier X of the previous time.
Holds, and the value of the multiplier x becomes the value of the (n-1) th multiplier X.

Further, in the case of multiplication with the nth multiplier X and the nth multiplicand Y whose values are zero, the D-type flip-flops FY0 to FY3 are the nth-1th multiplicand Y of the previous time. The value remains unchanged, and the value of the multiplicand y is the n-1th
It becomes the value of the th multiplicand Y.

Therefore, the n-th multiplier X whose value is zero is
The input to the CMOS type multiplier 20 does not change during the multiplication of the nth multiplicand Y and the CMOS type multiplier 20.
The multiplication operation is not performed, and the current consumption of the CMOS type multiplier 20 is almost zero.

After this, the next n + th value whose value is not zero
According to the inputs of the first multiplier X and the (n + 1) th multiplicand Y, the signal b output from the zero discriminating means 10 is in the H state.

At the positive edge of the (n + 1) th pulse of the signal a, the D-type flip-flop 12a receiving the signal b holds the H state and outputs the signal c in the H state. At the positive edge of the (n + 1) th signal a, the D-type flip-flop 12b outputs the signal c immediately before the (n + 1) th positive edge of the signal a.
Holds the L state of and outputs the L state signal e.

Therefore, when the multiplication operation is performed by the CMOS type multiplier 20, the multiplication result zero means 14 is output at the timing when the multiplication result z is output from the CMOS type multiplier 20.
The signal e in the L state is input to a total of eight AND gates of the multiplication result Z output from the multiplication result zero means 14.
All of A0 to ZA7 are zero.

Therefore, the D-type flip-flops FZ0 to FZ
Z7 is a positive edge of the (n + 1) th clock CK, and outputs a multiplication result Z having a value of zero between the nth multiplier X having a value of zero and the nth multiplicand Y.

Also, as shown in the time chart of FIG. 5, in the period from the vicinity of the positive edge of the nth pulse of the clock CK to the vicinity of the positive edge of the (n + 1) th pulse, the CMOS type The current consumption of the multiplier 20 is almost zero.

As described above, according to this embodiment, when at least one of the multiplier X and the multiplicand Y is zero, the current consumption of the CMOS digital multiplier can be made substantially zero, and therefore, It is possible to reduce the power consumption of the entire digital multiplication circuit.

The digital multiplying circuit to which the present invention is applied reduces power consumption when used in a field in which at least one of the multiplier and the multiplicand of the digital multiplying circuit used is frequently zero. The effect can be exerted more.

As an application field in which such an effect can be more exerted, the inventor has used a digital signal used in a ghost canceller for improving a ghost screen by removing a ghost signal which has been superimposed on a television reception signal together with an original signal. Finding application areas for filters.

It is conventionally known that the transfer function of a predetermined frequency response can be realized by a certain kind of impulse response. In addition, various theories are known for obtaining an impulse response of a transfer function having such a predetermined frequency response and using it in an electronic device or the like.

According to such a theory, in order to obtain a predetermined frequency response, a plurality of delay elements are used and a plurality of delay signals having different delay times are combined with different signal levels of the respective delay signals. There is a digital filter for obtaining an output signal, which realizes a corresponding impulse response filter.

A digital filter using such a plurality of delay elements has a finite impulse response (finite impul)
se response (FIR) filter (hereinafter called FIR filter) and infinite impulse response (infinite impulse r)
An espouse (IIR) filter (hereinafter referred to as an IIR filter) is known.

FIG. 6 is a block diagram of the FIR filter.

In FIG. 6, a total of n delay elements D are provided.
1 to Dn are connected in series, and each connection portion is provided with a total of n + 1 taps for obtaining delayed signals of various delay times. The filter input signal input from the input terminal IN is a multiplier M0 that multiplies the delay element D1 and the coefficient C0.
To be entered for each input of and. Furthermore, these n + 1
A total of n + 1 multipliers M1 to Mn capable of multiplying the respective delay signal inputs having different delay times by the respective coefficients C0 to Cn to obtain the delayed output signals of arbitrary signal levels are provided. It is arranged for each tap. The delayed output signals from the n + 1 multipliers M0 to Mn in total are added by the adders AD1 to ADn and output to the output terminal OUT as a filter output signal.

In such an FIR filter, a delay signal is obtained from the tap on the output side of the delay element at a predetermined position (predetermined delay time) from the input terminal IN, and these predetermined delay signals are arranged for each tap. A multiplier outputs a delayed output signal having a desired signal level, and all the delayed output signals are added by an adder to obtain a final filter output.

As a result, in such an FIR filter, a filter output signal having a desired impulse response of the filter input signal input to the input terminal IN can be obtained.

Also, conventionally, there has been disclosed a technique of removing a ghost signal from a received signal of a television and improving a ghost screen by using various filters.

FIG. 7 is an explanatory diagram of a ghost screen based on a ghost signal that has been superimposed on the received signal together with the original signal.

In FIG. 7, the image I0 is a real image based on the original signal, and the image I1 is a ghost based on the ghost signal superimposed on the original signal in the received signal.

FIG. 8 is a radio wave propagation diagram for explaining the ghost generation process.

In FIG. 8, the direct wave B of the broadcast radio wave radiated from the broadcasting station 120 reaches the receiving antenna 124 by the shortest distance. On the other hand, part of the broadcast radio waves radiated from the broadcasting station 120 arrives at the receiving antenna 124 as reflected waves C and D reflected by the reinforced concrete buildings 122a and 122b. These reflected waves C and D
Will propagate over a distance longer than that of the direct wave B, so that the propagation time will be longer than that of the direct wave B. Further, since the reflecting surfaces of the broadcast radio waves of these reinforced concrete buildings 122a and 122b have a certain width, these reflected waves C and D
The propagation time of each of the two has a width, and the reflected waves C and D become a composite signal of a large number of reflected waves having close propagation times.

Therefore, the reception signal generated at the reception antenna 124 becomes a reception signal in which, in addition to the original signal, a ghost signal with a time delay is superimposed.

FIG. 9 is a waveform diagram of the original signal and the received signal in which the ghost signal is superimposed on the original signal.

In FIG. 9, the original signal Sx (t) is
It is represented by a square wave of height 1. The received signal Sy (t) in FIG. 9 includes a square wave g0 having a height of 1 due to a direct wave and a square wave of a ghost signal due to a plurality of reflected waves.
g1 to g5 are overlapped.

Further, the square waves g1, g2, g3, g4, and g5 of the ghost signal due to the reflected waves that have been superimposed are delayed by Δt1 and Δt2, respectively, compared with the square waves g0 of the original signal due to the direct wave. , Δt3, Δt4, and Δt5 have been delayed. Also, the square waves g1, g2, g3, g of these ghost signals
The signal levels of 4 and g5 are a1, -a2, a3, a4, and
It is -a5.

The received signal Sy (t) shown in FIG. 9 is expressed by the following equation.

Sy (t) = x (t) + a1 x (t−Δt1) −a2 x (t−Δt2) + a3 x (t−Δt3) + a4 x (t−Δt4) −a5 x (t−Δt5) ... …… (1)

The equation (1) is modified to obtain Sx (t) as follows.

Sx (t) = y (t) −a1 x (t−Δt1) + a2 x (t−Δt2) −a3 x (t−Δt3) −a4 x (t−Δt4) + a5 x (t−Δt5) ……… (2)

That is, the ghost signal superimposed on the received signal Sy (t) can be removed by the calculation of the equation (2).

Conventionally, the above FIR filter has been used to effectively remove the ghost signal from the received signal by performing the calculation of the equation (2).

Although this FIR filter can be realized by a digital filter, various ghost cancellers by the FIR filter constituted by the digital filter have been developed in recent years with the price reduction of the digital filter.

FIG. 10 is a block diagram showing a ghost canceller using an FIR filter.

In FIG. 10, the input signal (received signal) input from the input terminal IN passes through the FIR filter of the digital filter composed of 64 stages of delay elements, and out of the two inputs of the adder AD. Is input to one input of.

The output of the adder AD is the FI of a digital filter having delay elements of 576 stages.
The FIR filter 11 is input to the R filter 112.
The output of 2 is input to the other input of the two inputs of the adder AD. That is, this FIR filter 1
12 and the adder AD constitute an IIR filter,
The output of the adder AD is also connected to the output terminal OUT of the ghost canceller.

In FIG. 10, the FIR filter 11
Reference numeral 0 constitutes an equalizer section for correcting waveform distortion due to a coaxial cable or the like between the receiving antenna and the ghost canceller.

Further, the IIR filter composed of the adder AD and the FIR filter 112 calculates the above-mentioned expression (2), that is, if a plurality of delay signals having different delay times are used, if the respective delay signals have different signal levels. A ghost removing unit that removes the ghost signal by adding them.

The FIR filter 112 of FIG. 10 has a clock frequency fck (= 4fsc = 4 × 3.58 MHz) of 15.32 MHz, so 600 taps are required to remove a ghost in the range of about 44 μs. Degree required.

Therefore, the FIR filter 11 shown in FIG.
2 has 576 taps. That is, in the FIR filter 112 of FIG. 10, n of the FIR filter of FIG. 6 is 575.

In such a ghost canceller shown in FIG. 10, a square wave g1 to ghost signal of a ghost signal by a reflected wave from the received signal Sy (t) shown in FIG.
In order to eliminate g5, the coefficients of the taps corresponding to the delay times Δt1 to Δt5 corresponding to these square waves g1 to g5 and the multipliers M0 to Mn of the taps corresponding to the delay times corresponding to the spread of the ghost, respectively. Is non-zero.

Therefore, when removing the ghost, 57
Most multiplication coefficients of the six multipliers M0 to Mn (n = 575) are zero.

Therefore, when the digital multiplication circuit of the present invention is applied to the ghost canceller using such a digital filter, the power consumption of the entire ghost canceller can be greatly reduced.

In the digital filter used in the ghost canceller or the like, the number of gates per multiplier used is usually 1,000 or more.

Therefore, it is difficult to form a digital filter used for a ghost canceller or the like into one chip,
It is manufactured by dividing it into multiple chips.

In recent years, the operation speed of LSIs (large scale integrated circuits) has been improved due to the miniaturization of semiconductor manufacturing technology. Therefore, for example, by further quadrupling the clock frequency of the multiplier, one multiplier is used for four and the number of multipliers used is reduced to ¼.

However, since the power consumption of the multiplier is determined not by the number of multipliers but by the number of multiplication operations, the power consumption cannot be reduced, which is a problem of high integration.

However, by using the multiplier to which the present invention is applied in the digital filter, the power consumption of the digital filter can be reduced and higher integration can be achieved.

[0152]

As described above, according to the present invention, 2
In a digital multiplication circuit using a CMOS type digital multiplier that inputs a multiplier of a base number and a multiplicand of a binary number and outputs a multiplication result of the multiplier and the multiplicand, during a multiplication operation according to the multiplier and the multiplicand. It is possible to obtain the excellent effect that the current consumption of the CMOS type digital multiplier can be reduced, and the power consumption of the entire digital multiplication circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a circuit diagram of a CMOS type inverter gate which is an example of a CMOS type gate used in a CMOS type digital multiplier.

FIG. 3 is a schematic diagram of the CMOS type inverter gate;
It is a graph of the voltage and current of each part according to the elapsed time.

FIG. 4 is a logic circuit diagram of an embodiment of the present invention.

FIG. 5 is a time chart of signals of various parts of the embodiment.

FIG. 6 is a block diagram of an FIR filter to which the embodiment can be applied.

FIG. 7 is an explanatory diagram of a ghost screen based on a ghost signal that is superimposed on a television reception signal together with an original signal.

FIG. 8 is a radio wave propagation diagram for explaining a ghost generation process.

FIG. 9 is a waveform diagram of an original signal and a received signal in which a ghost signal is superimposed on the original signal.

FIG. 10 is a block diagram of a ghost canceller using an FIR filter.

FIG. 11 is a logic circuit diagram of a conventional digital multiplication circuit using a CMOS type digital multiplier.

FIG. 12 is a time chart of signals of respective parts of the conventional digital multiplication circuit.

[Explanation of symbols]

10 ... Zero discriminating means, 10a, 10b ... 4-input NOR gate, 10c ... NOR gate, 12 ... Timing means, 12a, 12b, FX0-FX3, FY0-FY3, FZ0-FZ7 ... D-type flip-flop, 12c ... AND gate , 12d ... Inverter gate, 12e ... Delay element, 14 ... Multiplication result zero means, 20 ... CMOS type multiplier, TP ... P channel MOS transistor, TN ... N channel MOS transistor, Vi ... Input signal voltage, Vo ... Output signal voltage , C ... Capacitance, I1 ... Power supply side transistor current, I2 ... Ground side transistor current, I ... Output current, VDD ... Power supply voltage, a to e ... Signal, CK ... Clock, X, X0 to X3, x, x 0-x3 ... Multiplier, Y, Y0-Y3, y, y0-y3 ... Multiplicand, Z, Z0-Z7, z, z0-z7, Z , ZA0~ZA
7 ... Multiply result, AD, AD1-ADn ... Adder, D, D1-Dn ... Delay element, M, M0-Mn ... Multiplier.

Claims (1)

Claim: What is claimed is: 1. A CMO for inputting a binary multiplier and a binary multiplicand and outputting a multiplication result of the multiplier and the multiplicand.
In a digital multiplication circuit using an S-type digital multiplier, a zero discriminating unit that discriminates that at least one of the multiplier and the multiplicand is zero, and the zero discriminating unit determines that the value is zero. Includes a multiplication result zero means for forcibly setting the multiplication result to zero, and a timing means for stopping the operation in the CMOS type digital multiplier when the zero determination means determines that the result is zero.
A digital multiplication circuit characterized by comprising.