JPH0562349B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a display controller used in a computer terminal or a video game device, and particularly relates to a display controller that increases the number of moving image patterns that can be displayed on one horizontal scanning line. [Prior Art] In recent years, display devices such as video game machines have become capable of displaying moving images and still images together. For example, when displaying a video of a bird flying, the bird pattern (this pattern itself is constant) is composed of a dot pattern of about 8 x 8 pixels, and this is stored in memory in advance as a display unit. , a moving image is obtained by sequentially shifting the display position. Further, the background can be displayed as a still image. By the way, in conventional display controllers, the number of moving image patterns that can be displayed on one horizontal scanning line is small (for example, four patterns), which is a constraint on the screen configuration. The reason for this will be explained below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a conventional display controller. In this diagram,
1 is the CPU, display controller 2
A desired screen display is performed on the CRT display device 3 via the CRT display device 3. In addition, 4 is a memory that provides various programs and work areas, etc. to the CPU 1;
is VRAM (video RAM). This VRAM5
As shown in FIG. 2, there is a still image pattern table 5a that stores still image patterns in the form of a dot pattern, a still image control table 5b that stores the display position of the still image pattern, and a still image control table 5b that stores the display position of each still image pattern. It has a still image color table 5c that stores codes (4 bits), a video pattern table 5d that stores video patterns, and a video control table 5e that stores display positions of video patterns. Here, the video pattern table 5d is
As shown in Figure 3 A, it is composed of 8 by units.
Consisting of 256 moving image patterns P0, P1, P2...P255, the moving image control table 5e is composed of 32 tables C each consisting of 4 bytes, as shown in FIG.
It consists of 0, C1, C2...C31. Each video control table Ck (k=0, 1...31) contains the selected video pattern Pi (i=0, 1, 2).
...255) name (third byte), the X coordinate (second byte) and Y coordinate (first byte) of the display position of this video pattern Pi, and the color code that specifies the color of the video pattern Pi, which will be described later. The EC bit (4th byte) is stored. As shown in Fig. 4, the above display position (X, Y) has the upper left corner of the screen as the origin (0, 0), and with this origin as a reference, the number of pixels in the horizontal right direction is X, and the number of pixels in the vertical downward direction is This is the position where the number of pixels is Y, and it points to the upper left corner of the displayed video pattern Pi. Next, the display controller 2 will be explained. First, the timing signal generating circuit 6 generates a basic clock, forms horizontal and vertical synchronizing signals based on this, and supplies them to the CRT display device 3, and also supplies head clock pulses to the horizontal counter 7. This horizontal counter 7 determines the display position of the display pixel in the horizontal direction, and each time the count value NH increases by 1, the display position of the pixel moves to the right by one dot. And count value NH=
When NH=0, pixels are displayed at the left end of the screen, when NH=255, pixels are displayed at the right end of the screen, and between NH=256 and 340 there is a horizontal non-display period. Also, count value NH=
A pulse is supplied to the vertical counter 8 every time it reaches 340. This vertical counter 8 determines the vertical position of the display pixel, that is, the number of the horizontal scanning line, and each time the count value NV increases by 1, the horizontal scanning line moves down by one line. Then, when the count value NV=0, NV=
When 191, pixels are displayed at the bottom of the screen,
The period between VH=192 and 261 is a vertical non-display period. Next, the image data processing circuit 9 is connected to the CPU 1 via the interface circuit 10, while
It is connected to the VRAM 5, writes data supplied from the CPU 1 to each table in the VRAM 5, reads the written data according to commands from the CPU 1, and performs various display controls. That is, in the case of still image display, the still image pattern name, display position, and color code written in the still image control table 5b during the vertical non-display period are read out immediately before display (8 pixels before), and the display is performed based on these. The bit data to be displayed is extracted from the still image pattern table 5a, set in a shift register in the image data processing circuit 9, and when the display position is reached, this shift register is shifted one bit at a time, and the output "1" is set. /Supplies the color code corresponding to "0" to the color palette 11. color palette 1
1, this color code is R (red), G (green), B
(blue) and displayed on a CRT display device 3 via a DAC (digital/analog converter) 12. On the other hand, moving image display is performed by cooperative processing between the image data processing circuit 9 and the moving image processing circuit 13.
That is, in response to a command from the CPU 1, the image data processing circuit 9 determines the name, display position, and
The color code and EC bit are set in the video control table Ck in sequence, and in each horizontal scanning period, the Y coordinate of this video control table Ck is sequentially checked to determine whether there is a video pattern to be displayed in the next horizontal scanning period. Examine and register the video control table Ck with the video pattern to be displayed in a predetermined register,
During each horizontal non-display period, the X coordinate of the registered video control table Ck is transferred to the X counter of the video processing circuit 13, and one line of dot data to be displayed in the next horizontal scan is transferred to the video pattern table 5d. Extracted from a predetermined location (which is obtained from the count value NV of the vertical counter 8 and the Y coordinate of the video control table Ck), the video processing circuit 13
Set to the pattern shifter inside. In this way, the pattern shifter and the X counter in each moving image processing circuit 13 are sequentially set with one line of dot data of the moving image pattern to be displayed during the next horizontal scan and its display start position X. At the same time,
The color code of each moving image pattern is also transferred to each moving image processing circuit 13 from the fourth byte of the moving image control table Ck. Then the next horizontal scan starts,
Each time the count value NH of the horizontal counter 7 increases by 1, the value of each X counter is decreased by 1, and this value becomes 0.
When it reaches , the pattern shifter sequentially outputs one bit at a time in synchronization with the count-up of the horizontal counter 7, and this is displayed on the CRT screen.
In this case, when the output is a "1" signal, a color code is supplied from the video processing circuit 13 to the color palette 12, and the corresponding color is sent to the DAC.
The signal is displayed on the CRT screen via 12, and since nothing is supplied when the signal is "0", the screen becomes the background color. By the way, in the above-mentioned conventional device, if a part of the video pattern is hidden on the left side of the screen, the X of the display position (X, Y) of this video pattern becomes negative, and the X counter value becomes negative. Even if you decrease the value by 1, it will not become 0, and you will not be able to specify the correct position. Therefore, in such a case, as shown in FIG. 5, by shifting the screen to the left by a predetermined pixel m (for example, m=32) and starting counting with the X counter from the left end of this virtual screen, The position (X, Y) is shifted to the position (X-m, Y), and thereby the moving image is shifted to the left by m pixels and displayed. This is specified by the EC bit in the video control table Ck mentioned above. That is, when the EC bit is on, the start of down-counting of the X counter is advanced by m counts, and the above processing is performed. According to this method, although the above-mentioned inconvenience can be eliminated, since the start of down-counting of the X counter must be advanced by the shift number m, the data set to the X counter and pattern shifter of the video processing circuit 13 is It must be completed by. Therefore, the time within the horizontal non-display period that can be used for the data set is reduced by this amount. For example, 16
Considering the case where a ×16 pixel video is enlarged twice and displayed, the number of shifts must be m = 32,
In this case, the horizontal non-display period (this is the count value NH of horizontal counter 7 between 256 and 340, 85 counts)
Approximately 1/3 or more of this will be taken away for the above shift. As a result, the number of data that can be set in the moving image processing circuit 13 is reduced, and the number of moving images that can be displayed on one horizontal scanning line is also reduced. [Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its object is to provide a display controller that can increase the number of moving image patterns that can be displayed on one horizontal scanning line. . [Features of the Invention] In order to achieve the above-mentioned object, the present invention includes a horizontal counter that counts dot clock pulses at a speed corresponding to the display pixels, and a horizontal display start position data of a moving image pattern to be displayed. a display start position specifying means for specifying a display start position; a storage means for storing specific information indicating whether or not a part of the video pattern is hidden at the left end of the screen; Therefore, a latch means for adding a predetermined number of bits to the display start position data stored by the display start position specifying means at the start of horizontal scanning and latching it as a display start bit;
A decoder decodes the output of the latch means and specifies the display start bit, and when the value of the horizontal counter and the value of the display start position designation means match, the output of the decoder specifies the video pattern from the bit designated by the output of the decoder. It is equipped with a shift register that sequentially outputs the dot data of Features. [Example] Hereinafter, an example of the present invention will be described based on the drawings. FIG. 6 is a block diagram showing the configuration of the image data processing circuit 9 (see FIG. 1). In the figure, pulse CW (8 bits) is the bus for writing data from CPU1, and bus CR (8 bits) is the bus for writing data from CPU1.
Buses AH (10 bits) and AL (8 bits) for reading data are buses for addressing the VRAM 5, with bus AH specifying the upper 10 bits and bus AL specifying the lower 8 bits. Bus VW is VRAM5
Bus for writing data to, bus VRL is VRAM5
The bus Clr, which is a bus for reading data from the printer, is a bus on which a color code is carried, and is connected to the color palette 11 shown in FIG. Next, the register group B1 consists of registers B1a to B1e that store the start addresses of each table type. And these registers B1a to B1e
includes a still image control table 5b, a still image color table 5c, a still image pattern table 5a, a moving image control table 5e, and a moving image pattern table 5.
Each start address of d is stored and can be rewritten from the CPU 1 via the bus CW.
The color information register B2 stores two types of still image color codes read from the still image color table in the VRAM 5, and is output from the pattern shifter B3. One of them is selectively outputted by a "1"/"0" signal and placed on the color bus Clr. The pattern shifter B3 is connected to the bus VRL.
This is a shift register that converts the image data read from the VRAM 5 from VRAM 5 to parallel to serial, and supplies its output "1"/"0" to the color information register B2 to determine the display color. Next, the video number counter B4 calculates the number (video number) k of each video control table Ck and the Y coordinate storage address (0 in this embodiment) in this table Ck.
This is a 7-bit counter that stores the byte number (see Figure 3 B), the upper 5 bits represent the video number k, and the lower 2 bits represent whether it is the Y or X pattern name or color information. , when searching the moving image table 5e to detect a moving image to be displayed on the next horizontal scanning line, the moving image number k is sequentially incremented. At this time, the lower two bits are always "0" and indicate only the Y coordinate of the moving image table. During the display period, this search
The Y coordinate of each video control table Ck is investigated and this is compared with the count value NV of the vertical counter 8. When a video to be displayed is detected, the content of the video number counter B4 at that time is set to the video number.
Register in FIF0, B5. In this case, video number k(0
- 31) in descending order, and once eight are registered, no further entries will be accepted. In this way, during the horizontal display period, up to eight video numbers k to be displayed on the next horizontal scanning line are registered in video numbers FIF0 and B5, and then these are sequentially read out during the horizontal non-display period to control the video. Y coordinate of video from table Ck, X
Coordinates, video pattern Pi name, color code,
This is the address when reading the EC bit, etc.
The data read from each video control table Ck is transferred to and set in a video processing circuit 20 (8 sets are provided), which will be described later, via the bus VRL. Note that the 9th video number that was not entered into video FIF0, B5 is registered in register B6. Next, the ALU (arithmetic unit) B7 compares the count value NV of the vertical counter 8 with the Y coordinate, calculates the address of the video image data, etc.
The calculation result is supplied to decoder B9 via status B8. The decoder B9 operates under the control of the mode register B10.
ROM (hereinafter referred to as μ program ROM) B11
It decodes the commands supplied from the bus and controls the sequence of data transferred to each bus. This μ
The program ROMB11 includes a horizontal counter 7,
A vertical counter 8 is connected to specify the read address of the instruction. Next, FIG. 7 is a block diagram showing the configuration of the moving image processing circuit 20. This video processing circuit 20 is
This circuit is provided in place of the conventional video processing circuit 13 shown in FIG. It is connected to the color palette 11 via Clr. Here, the bus VRL has eight lines VRL0 to
These lines VRLj (j=0,
1...7) are connected to the data input terminal Di of each bit 21j of the 8-bit (256 base)
The data input terminals Di of the storage elements 23j and 24j of the shift registers 23 and 24 are connected to each other. Then, before each horizontal scan line begins to be displayed,
That is, during the horizontal non-display period, the load signal XL is applied to the load terminal LD of each bit 21j of the X counter 21, and the signal CL is applied to the clock terminal CK of each latch element 22j of the latch circuit 22. When signals LL and RL are sequentially applied to the load terminals LD of the 24 storage elements 23j and 24j,
Each data is set via the lines VRL0 to VRL7. First, the X counter 21 has a video control table.
The value X (which, as mentioned above, indicates the display start position of the moving image pattern) is inverted and supplied from Ck by the inverter INV, and is set as the initial value _NX0 . In this case, the X counter 21 is
Since it is a 256 hexadecimal counter, the initial value NX ₀
is NX ₀ =255−X...(1). Next, the latch circuit 22 includes a video control table.
From the 4th byte of Ck, color code and EC
The bit is supplied and the color code is set to latch element 2.
20 to 223, the EC bit is the latch element 227
are set respectively. Further, the shift registers 23 and 24 are supplied with dot data to be displayed from the moving image pattern table 5d shown in FIG. 3A, and set therein. Note that dot data is set in the shift register 24 only when the size of the video pattern is 16 x 16 pixels, and only in this case the load signal is set.
RL is now applied. In this way, before the horizontal display starts, the X counter 21
The initial value _NX0 is set in the latch circuit 22, the color code and EC bit are set in the shift registers 23 and 24, and the dot data of the moving image pattern to be displayed is set in the shift registers 23 and 24. Then, when horizontal display is started, parallel processing is performed in eight sets of moving image processing circuits 20, and moving image display is performed using the data set above. First, in the video processing circuit 20 with the EC bit turned off, the X counters 21 start counting up all at once (this up counting is done in synchronization with the horizontal counter 7), and the display positions of the pixels change as shown in FIG. When the position (X, Y) shown in is reached, shifting of the shift registers 23 and 24 is started, and the dot data set therein is displayed. That is, the X counter 2 of each video processing circuit 20
The input terminal Ci of each bit 21j of 1 is connected to the carry output terminal _Cp of the previous stage bit, and the input terminal Ci of the least significant bit 210 is connected to an SR flip-flop (hereinafter referred to as SRFF) set by the count start signal CS.
) 25, the carry output terminal C _p of the most significant bit 217 is connected to the Q output terminal of
Each is connected to the set end S of SRFF27, and the count start signal CS is applied to SRFF2 at the start of horizontal display.
5, the X counter 21 sequentially counts up starting from the initial value NX ₀ (=255-X) shown in equation (1). As described above, this up-count is performed in synchronization with the up-count of the horizontal counter 7, and when the pixel display position reaches X, the count value NX becomes 255. At this time,
The outputs of all the bits 210 to 217 become "1" and the output of the AND gate 28 becomes "1", which is supplied to the shift controller 29 and shifting of the shift registers 23 and 24 is started. On the other hand, in the video processing circuit 20 with the EC bit on, the value 32 is first added to the initial value NX ₀ of the X counter 21 to update the initial value, and an up count is performed from the updated initial value NX ₀ . be exposed.
As a result, the moving image pattern Pi moves 32 pixels to the left from the position (X, Y) and is displayed from the position (X-32, Y). More specifically, the bits of the X counter 21
An OR gate 30a is inserted between the carry output terminal _Cp of the bit 214 and the input terminal Ci of the bit 215, and the output of the AND gate 30b is supplied to the other input terminal of the OR gate 30a. The AND gate 30b takes the AND of the start signal H _p supplied at the start of horizontal display and the EC bit, and when the EC bit is on, the start signal
When H _p is supplied, a "1" signal is supplied to the input terminal Ci of the bit 215, and the value 32 is added to the X counter 21.
In this case, the initial value NX ₀ of the X counter 21 is 255-
Since it was X, the initial value NX ₀ after 32 addition is NX ₀ =255−X+32 (2). Therefore, when X≧32, the initial value
NX ₀ becomes 255 or less, and the same processing as when the EC bit is off is performed. Further, when X≦31, the initial value NX ₀ becomes 256 or more. Here, in the X counter 21,
Considering that "256" = "0", NX ₀ becomes NX ₀ = 256 - X + 31 = 31 - X ... (3) Therefore, when the _value
It can be seen that the value is 0. This corresponds to a case where a part of the video pattern is hidden on _the left side of the screen.
A signal is output, and the SRFF 27 is set via the AND gate 26 which is in an open state due to the "1" output of the AND gate 30b. When the SRFF 27 is set, a "1" signal is supplied from the Q output terminal to the shift controller 29, and dot data is sent from intermediate bits of the shift registers 23 and 24, as will be described later. Note that the above-mentioned components 30a, 30b, and 215 constitute the adding means 30. Next, the lower 4 bits 210 to 213 of the X counter 21
The output of each bit of the 4-bit selector 31 is
The outputs of the lower four bits excluding the least significant bit 210 are supplied to the second input terminals D2 of the bits 310 to 313. This selector 31 switches the input data according to the signal MAG supplied to the selector terminal S of each bit 310 to 313.
MAG is "1" when the video pattern is enlarged (2x enlargement), and when it is not enlarged (normal display)
becomes “0”. When the signal MAG is "0", the lower 4 bits 210 to 213 of the X counter 21
When the output is "1", the outputs of the lower 4 bits 211-214 excluding the least significant bit 210 are supplied to the input terminal D of each latch element 320-323 of the 4-bit latch circuit 32. The latch circuit 32 latches the data supplied from the selector 31 in response to the signal CSa supplied to its clock terminal CK. Signal CSa
is output from the shift controller 29 based on the count start signal CS when the Q output of the SRFF 27 is "1" (that is, when the EC bit is on and X≦31). And X counter 21
The count value NX is the initial value NX ₀ given by equation (3)
(=31 - Here, when the signal MAG is "0", the output of the selector 31 is the count value NX (=32-X)
When the signal MAG is "1", it is the lower 4 bits excluding the least significant bit of this count value NX, so the value n set in the latch circuit 32 corresponds to the value It will look like Table 1. The value n once set in the latch circuit 32 is determined by the reset signal CSb outputted from the shift controller 29 based on the next count start signal CS to each latch element 320 to 323.
It is held until it is applied to the reset end R of . In this way, the value n latched in the latch circuit 32 in the form of a binary code is converted into a hexadecimal code by the decoder 33, and output corresponding to each value of n=0, 1, 2...15. The signals F0, F1, F2...F15 are sent from the decoder 33 to AND gates A0, A1, A2...A
15 first input terminals. On the other hand, each second gate of AND gates A0, A1, A7, A8...A15
Each output of the storage elements 237, 236...230, 247...240 of the shift registers 23, 24 is supplied to the input terminal. Also, and gate

【table】

[Table] Each output of A0 to A7 is supplied to each input terminal of OR gate 34a, each output of AND gates A8 to A15 is supplied to each input terminal of OR gate 34b, and each output of OR gates 34a and 34b is supplied to each input terminal of OR gate 34c. It is supplied to the input end Di of the storage element 35.
As a result, the AND gate An opened corresponding to the above value n becomes the gate for taking out the dot data, and the dot data stored in the shift registers 23 and 24 is transferred from the AND gate An to the OR gate 3.
4a, 34b→OR gate 34c→memory element 35
The serial signal PT is output from this memory element 35 through
is output as Then, in response to "1"/"0" of this signal PT, the latch elements 220 to 2
The color code latched in DAC 23 is turned on/off, and this is supplied to the color palette 11 shown in FIG.
2 to be displayed on the CRT display device 3. The shift registers 23 and 24 are for storing 8-bit or 16-bit dot data.
When the dot data is 8 bits (when the video pattern is 8 x 8 pixels), the shift register 23 is used alone, and when the dot data is 16 bits (when the video pattern is 16 x 16 pixels), it is connected to the shift register 23. It is used together with the shift register 24. As already mentioned, during the horizontal non-display period, the shift controller 29 sends the shift register 23 to the shift controller 29.
By the load signal LL supplied to the load terminal LD of each of the memory elements 230 to 237, the dot data to be displayed in the next horizontal display period is transferred to the memory element 2.
30 to 237 (hereinafter, the dot data set in the memory elements 230 to 237 at this point will be referred to as D0 to D7), and similarly, each memory element 240 to 247 of the shift register 24 is set to each load. By the load signal RL supplied to the terminal LD, the 8 data displayed following the above dot data is displayed.
Bit dot data is set (hereinafter, the dot data set in the memory elements 240-247 at this point will be referred to as E0-E7). Then, when entering the horizontal display period, these dot data D0
~D7, E0~E7 are the shift signal S and hold signal H supplied from the shift controller 29
are sequentially output from the take-out gate An while being controlled by the First, when the Q output of the SRFF 27 is "0", that is, when the entire video pattern is displayed on the screen, the value n latched by the latch circuit 32 is 0.
Then, the decoder 33 outputs a signal F0.
Therefore, the AND gate A0 becomes open and serves as a gate for extracting dot data. Then, the X counter 21 counts X, and when the count value NX reaches 255, a "1" signal is supplied from the AND gate 28 to the shift controller 29. As a result, when the signal MAG is "0", the shift signal S is output from the shift controller 29 in synchronization with the count of the horizontal counter 7, and when the signal MAG is "1", the count value NX of the X counter 21 is output. A shift signal S/hold signal H is alternately outputted from the shift controller 29 depending on whether the signal is even or odd. As a result, the signal MAG
When signal MAG is "0", dot data D7, D6...D0, E7, E6...E0 are sequentially output from AND gate A0 and displayed in order from position X on one horizontal scanning line, and when signal MAG is "1", , dot data D7, D from AND gate A0
7, D6, D6, ...D0, D0, E7, E7, E
6, E6...E0, E0 are sequentially output and displayed. Next, when the Q output of the SRFF 27 is "1", that is, when a part of the moving image pattern is hidden on the left side of the screen, the value n (n=0) is latched in the latch circuit 32, and a signal is sent from the decoder 33. Fn is output. Therefore, the AND gate An is in an open state,
This becomes the gate for extracting dot data. Then, each time the count value NX of the X counter 21 increases by 1, a shift signal S is output from the shift controller 29 when the signal MAG is "0".
When the signal MAG is “1”, the shift signal S/hold signal H corresponds to the even/odd of the count value NX.
are alternately output from the shift controller 29. As a result, when the signal MAG is “0”,
The dot data shown in Table 2 is sequentially output from the AND gate An, and these are displayed sequentially from the left edge of the screen.

〔Effect of the invention〕

As described above, the present invention includes a horizontal counter that counts dot clock pulses at a speed corresponding to display pixels, and a display start position specifying means that stores horizontal display start position data of a moving image pattern to be displayed. a storage means for storing specific information indicating whether or not a part of the video pattern is hidden at the left edge of the screen; a latch means for adding a predetermined number of bits to the display start position data stored by the display start position specifying means and latching it as a display start bit; a decoder for decoding the output of the latch means to specify the display start bit; A shift register is provided for sequentially outputting the dot data of the moving image pattern from the bit specified by the output of the decoder when the value of the counter matches the value of the display start position specifying means. By displaying according to the dot data, it is now possible to display video patterns that are partially hidden at the left edge of the screen, increasing the number of video patterns that can be set within the horizontal non-display period. An advantage is obtained that the number of moving images that can be displayed on a horizontal scanning line can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional display device, and FIG. 2 is a block diagram showing an example of the configuration of a conventional display device.
A memory map showing the contents of the VRAM 5. FIG. 3A is a conceptual diagram showing an example of the storage contents of the moving image pattern table 5d shown in FIG. Fig. 4 is a conceptual diagram showing an example of the display position (X, Y) of the video pattern Pi, Fig. 5 is a conceptual diagram illustrating the screen shift when specifying the EC bit, and Fig. 6 is a conceptual diagram showing the display position (X, Y) of the video pattern Pi. , a block diagram showing the configuration of an image data processing circuit according to an embodiment of the present invention, and FIG. 7 is a block diagram showing the configuration of a moving image processing circuit 20 according to the same embodiment. 21...X counter (counter), 23, 24
...shift register, 30...addition circuit (addition means), 32...latch circuit (latch means), 33...
...Decoder, EC...EC bit (specific bit).

Claims (1)

[Scope of Claims] 1. A horizontal counter that counts dot clock pulses at a speed corresponding to display pixels; Display start position specifying means that stores horizontal display start position data of a moving image pattern to be displayed; a storage means for storing specific information indicating whether or not a part of the pattern is a moving image pattern hidden at the left edge of the screen; a latch means that adds the data to the display start position data stored by the display start position designation means and latches it as a display start bit; a decoder that decodes the output of the latch means and designates the display start bit; and a value of the horizontal counter. and a shift register that sequentially outputs the dot data of the moving image pattern from the bit specified by the output of the decoder when the value of the display start position specifying means matches, and the dot data output from the shift register is Accordingly, a display controller is characterized in that by displaying, it is possible to display even a moving image pattern whose part is hidden at the left end of the screen.