JPH0561772A - Information processing system - Google Patents

Abstract

PURPOSE:To accelerate address translation. CONSTITUTION:This system is equipped with a translation requesting means to transmit a virtual address and an address translating request to a system controller 200 when the translation from the virtual address to a real address is failed by an address translation memory 110, translation memory updating means to write the real address translated from the virtual address in the address translation memory together with the virtual address corresponding to address translation end information transmitted from the system controller, address translating mechanism 220 to execute the translation to the real address by successively retrieving an address translation table developed on a main memory 300 while using the virtual address at the system controller corresponding to the address translating request transmitted from an operation processor 100, and memory data return part 230 to transmit the real address translated by the address translating mechanism to the operation processor together with the address translation end information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system having an arithmetic processing unit and a system control unit for controlling access to a main memory according to a memory access request of the arithmetic processing unit.

[0002]

2. Description of the Related Art An example of a conventional information processing system of this type is shown in FIG.

In FIG. 3, the salt processing apparatus 1 has an address translation memory 1 having a translation pair of a virtual address and a real address.
0, a register 11 for holding a virtual address for performing address translation, a virtual address read out by indexing the address translation memory 10 by a part of the register 11 and the register 1.
Comparator 12 for comparing the virtual address stored in 1; register 13 for holding the result of the comparator 12; address translation mechanism 1 for address translation failure by address translation memory 10
7, a register 14 for holding a virtual address to be sent to 7, an address translation mechanism 15 for sequentially indexing the virtual address sent from the register 14 into an address translation table expanded in the main memory, and translating it to a real address, an address translation memory A memory access control unit 17 for sending a memory access request to the system control device 3 in response to an instruction from the register 16 for holding the real address translated by using the address translation mechanism 15. The memory access control unit 7 also has a function of sending the memory read data sent from the system control device 3 to the address translation storage 10.

The arithmetic processing unit 2 also has the same configuration as the arithmetic processing unit 1.

The system control unit 3 receives the memory access request sent from the memory access control unit 17 or 27 of the arithmetic processing unit 1 or 2 and sends the access request to the main memory 4 to receive the memory request.
0, and a memory data return unit 31 that sends the read data sent from the main memory 4 to the memory access control units 17 and 27 of the arithmetic processing units 1 and 2.

The operation of converting a virtual address into a real address in this example will be described below. In the virtual address, the upper part is an address conversion part, the lower part is an address non-translation part, and the address conversion part is composed of a comparison part and an index part. The upper part is a comparison part and the lower part is an index part.

When the virtual address to be subjected to the address conversion is accepted by the register 11, the index conversion section of the register 11 is used to index the address translation memory 10 and read the comparison section and the comparison section of the register 11 from the comparator 12. Compare with
The result is set in the register 13. In parallel with this, the real address read from the address translation memory 10 is set in the register 1
Set to 6.

In the next cycle, if the contents of the register 13 indicate that the comparison result in the comparator 12 indicates a match, the address set in the register 16 is sent to the address translation request source and the address translation is completed. On the other hand, if the result shows a mismatch, the virtual address A stored in the register 14 is sent to the address translation mechanism 15.

When the address translation mechanism 15 receives the virtual address A from the register 14, it uses this to start the address translation. For example, the description will be made assuming that the address conversion unit of the virtual address is divided into fields of X, Y, and Z from the higher order to index three tables. The address translation mechanism 15 first generates a first memory address obtained by adding the base address of the first table and X to obtain the second table base address, and sends it to the memory access control unit 17 to send it to the memory access control unit. Upon receiving the first memory address, the memory 17 sends a memory read request together with the first memory address to the memory request receiving unit 30 in the system control device 3.

Upon receiving the first memory address and the memory read request, the memory request acceptance unit 30 in the system control device 3 sends the first memory address and the read request to the main memory 4. The main memory 4 receives the first memory address and the read request, and sends the content of the first memory address to the memory data return unit 31 of the system control device 3. The memory data return unit 31 of the system control device 3 sends the content of the received first memory address to the memory access control device 17 of the arithmetic processing device 1.

The memory access controller 17 of the arithmetic processing unit 1 receives the content of the first memory address and sends it to the address translation mechanism 15. The address translation mechanism 15 adds the contents of the first memory address (the base address of the second table) and Y to generate a second memory address. The content of the second memory address is the base address of the third table. The contents of the second memory address are read to the address translation mechanism 15 by the same procedure as when reading the second tail address from the main memory 4.

Subsequently, when the address translation mechanism 15 receives the contents of the second memory address, the contents of the second memory address (base address of the third table) and Z are added to store the real address. The third memory address is generated, and the contents of the third memory address are read by the same procedure as described above.

When the address translation mechanism 15 receives the contents of the third memory address, that is, the real address, it sends it to the address translation memory 10. Before the real address is sent to the address translation memory 10, the contents of the registers 11 and 14 are exchanged, and the virtual address A stored in the register 11 and the real address are written in the address translation memory 10. After that, the real address is read from the address translation memory 10 by the virtual address A of the register 11 and set in the register 16. Then, the real address of the register 16 is sent to the address translation request source, and the address translation is completed.

The address conversion of the arithmetic processing unit 2 is performed in the same manner as in the arithmetic processing unit 1 described above.

Further, at the address of the third request address, a control fee is provided in addition to the real address, and access to this address requires exclusive use between access request sources. Therefore, the address translator will read this address from reading to writing the control field.
Access from other access requesters must be suppressed. For example, when reading the third request address,
A method is adopted in which this address is locked (however, if the lock is unsuccessful, the address is read again), and the lock at this address is released at the time of writing the third request address.

The address translation mechanism 15 sends a lock request for this address to the memory access controller 17 together with the third request address. Thereafter, the contents of the third request address are read in the same procedure as the first request address. However, the lock success / failure information is also added to the content of the third request address. If the lock success / failure information indicates that the lock is unsuccessful, the address translation mechanism 15 sends the request again, and if the lock is successful, sends the unlock request together with the write request of the third request address to the memory access control unit 17. Register 1
After the 1 and the register 14 are exchanged, the real address is written in the address translation memory 10 together with the comparison unit of the virtual address A stored in the register 11. After that, the real address read from the address conversion memory 10 is set in the register 16. The real address stored in the register 16 is sent to the address translation source to complete the address translation.

[0017]

In the above-mentioned conventional information processing system, since the address translation mechanism exists in the arithmetic processing unit, the address translation mechanism 15 and the memory access control are performed when the virtual address is translated into the real address. Part 1
7. The data read loop consisting of the memory request receiving unit, the main memory, the memory data returning unit, the memory access control unit and the address conversion mechanism is repeated several times. In recent years, the number of loops and the number of system locks required for data transfer between devices are increasing, and a large number of system clocks are required for address translation. That is, there is a drawback that the address translation performance is lowered.

Further, in the above-described conventional information processing system, each information processing device must have an address conversion mechanism, and there is a drawback that the amount of metal money consumed for the entire system increases. In addition, it is necessary to equip the arithmetic processing unit with means for performing exclusive control at the time of address conversion between the respective units of the address where the real address on the main memory is stored, which makes address conversion of each arithmetic processing unit complicated. There was a flaw.

[0019]

An information processing system according to a first aspect of the present invention is an information processing system including an arithmetic processing unit and a system control unit for controlling access to data to a main storage unit in response to a request from the arithmetic unit. The arithmetic processing unit has an address translation memory that stores an address translation pair of a virtual address used in a program of a computer system and a real address that refers to a main memory, and from the virtual address by the address translation memory to the real address. If the translation of the virtual address fails, the virtual address is translated from the virtual address in response to the translation request means for sending the virtual address and the address translation request to the system controller, and the address translation end notification sent from the system controller. A translation memory update procedure for writing the real address to the address translation memory together with the virtual address Then, in response to the address translation request sent from the arithmetic processing unit, the system control unit sequentially searches the address translation table expanded in the main memory using the virtual address to execute the actual translation. It is characterized by comprising an address translation mechanism for translating into an address and an end notification reporting means for sending the real address translated by the address translation mechanism to the arithmetic processing unit together with an address translation end notification.

An information processing system according to a second aspect of the present invention is an information processing system comprising a plurality of arithmetic processing devices and a system control device for controlling access to data to a main memory in response to a request from each arithmetic processing device. The arithmetic processing unit of (1) has an address translation memory that stores an address translation pair of a virtual address used in a program of the computer system and a real address that refers to the main memory, and the address translation memory converts the virtual address to the real address. If the translation fails, the virtual address is translated in response to the translation request means for sending the virtual memory address and the address translation request to the system controller, and the address translation end notification sent from the system controller. The real address is written into the address translation memory together with the virtual address. Means, a translated address queue for the system controller to sequentially store the virtual addresses added to the address translation request in response to the address translation request sent from each of the arithmetic processing units, and the translated address An address translation mechanism that sequentially translates virtual addresses read in sequence from the queue into an address translation table that is expanded on the main memory and translates the real addresses into an actual address, and translates the real addresses translated by the address translation mechanism. And an end reporting means for sending together with the address translation end notification to the requested arithmetic processing unit.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the first present invention.

In FIG. 1, the arithmetic processing unit 100 includes an address conversion memory 110, a register 120, and a comparator 13.
0, register 140, register 150, memory access controller 16 and register 170.

The address translation memory 110 stores address translation pairs of virtual addresses and real addresses. In the address translation storage 110, part of the register 120 is input as an address, part of the register 120 and the output of the memory access control unit 16 are input as write data.

The register 120 is a register for receiving the virtual address from the address translation request source, and also receives the output of the register 150. The comparator 130 compares the comparing unit of the register 120 with the comparing unit read from the address translation storage 110. The register 140 is the comparator 13
It is a register for storing the result of comparison at 0.

The register 150 is used for the address translation storage 11
It is a register that holds the virtual address to be sent to the memory request receiving unit 210 in the system control device 200 when the address conversion by 0 fails, and the output of the register 120 is input. The memory access control unit 160 sends the virtual address sent from the register 150 when the address translation fails to the memory request receiving unit 210 together with the address translation request. Further, it receives the address translation end notification and the translated real address sent from the memory data return unit 230 of the system control device 200 and registers them in the address translation storage 110. Memory request control unit 16
0 receives the output from the register 150, the register 140, and the memory data return unit 230.

The system controller 200 comprises a memory request receiving section 210, an address conversion mechanism 220 and a memory data returning section 230.

The memory request receiving unit 210 receives a memory access request, a request address and an access command from the memory access control unit 160 in the arithmetic processing unit 100 and sends them to the main memory 300. When the access command is an address translation, Address translation mechanism 21
A request address (virtual address) and an address translation request are sent to 0. It also receives a request address, a request command, and a memory access request from the address translation mechanism 220 and sends them to the main memory 300.

The address translation mechanism 220 receives the address translation request and the request address (virtual address) from the memory request acceptance section 210, and the main memory 300
The index address of the table expanded above is generated, and the memory access request, the access command, and the request address are sent to the memory request receiving unit 210.

The memory data return unit 230 is provided in the main memory 30.
The read data sent from 0 is the arithmetic processing unit 100.
It is sent to the memory access control unit 160 and the address translation mechanism 220 in the inside.

In the following, the operation of converting a virtual address to a real address in the present embodiment is such that the virtual address is composed of an address translation unit and an address non-translation unit, the upper address is the address translation unit, and the lower address is the address non-translation unit. The case where the address conversion unit is composed of a comparison unit and an index unit, and the higher order is the comparison section and the lower order is the index section will be described.

When the register 120 receives the virtual address A for which the address conversion is performed from the address conversion request source, the address conversion memory 1 is stored in the index section of the register 120.
10, the read comparison unit and the comparison unit of the register 120 are compared by the comparator 130, and the result is set in the register 140. At the same time, the contents of the register 120 are transferred to the register 150, and the real address read from the address translation memory 110 is set in the register 170.

In the next cycle, the contents of the register 140 are referred to, and if the comparison result in the comparator 130 indicates a match, the real address stored in the register 170 is sent to the address translation request source, The address conversion process ends. If the result shows a mismatch, the virtual address A stored in the register 150 is sent to the memory access control unit 160.

When the memory access control unit 160 receives the virtual address A from the register 150, the memory access control unit 160 instructs the memory request reception unit 210 in the system control device 200 to
Send memory request request, access command (address conversion), request address (virtual address A).

When the memory request accepting unit 210 in the system controller 200 receives the memory request request, the access command, and the request address from the memory access controller 160, the address translation mechanism 220 receives the address translation instruction and the request address (virtual address). Send address A).

When the address translation mechanism 220 receives the address translation instruction and the request address, it executes the address translation. For example, the description will proceed assuming that the address conversion unit of the virtual address is composed of X, Y, and Z fields from the higher order. The address translation mechanism 220 uses the main memory 3
00 is added to the base address of the first table expanded on 00 to generate a request address for obtaining the base address of the second table. First
Of the request address, the request command, and the memory request request to the memory request receiving unit 210.

The memory request acceptance section 210 sends this request to the main memory 300. The main memory 300 sends the contents of the request address of the sent request to the read memory data returning unit 230. The memory data return unit 230 sends the contents stored in the first request address sent from the main memory 300 to the address translation mechanism 220.

The address translation mechanism 220 adds the contents stored in the first request address (with the base address of the second table) and Y to obtain the base address of the third table. Is generated, and the content stored in the second request address (the base address of the third table) is read by the same procedure as that in which the content stored in the first request address is read.

When the address translation mechanism 220 receives the contents stored in the second request address, the contents stored in the second request address (the base address of the third table) and Z are added to obtain the real address. A third request address for generating a real address is obtained by the same procedure as described above.

Upon receiving the real address, the address translation mechanism 220 sends the translated real address and the address translation notification to the memory data return unit 230. Upon receiving the real address and the address translation end notification, the memory data return unit 230
The real address and the address translation end notification are sent to the arithmetic processing unit 10
0 to the memory access control unit 160.

Upon receiving the real address and the address translation end notification, the memory access control section 160 receives the register 120.
The register 150 is replaced and the real address is sent to the address translation storage 110, and the real address is registered together with the virtual address A stored in the register 120. afterwards,
Register the real address from the address translation memory 110 to the register 17
Set to 0. After that, the real address stored in the register 170 is sent to the address translation request source and the address translation is completed.

FIG. 2 is a diagram showing an embodiment of the second invention. The information processing system of this embodiment is composed of two arithmetic processing units 400 and 500, a system control unit 600 and a main memory 700.

The arithmetic processing unit 400 includes an address conversion memory 410, a register 420, a comparator 430, and a register 44.
0, a register 450, a memory access control unit 460, and a register 470, and each component includes the address translation memory 110, the register 120, the comparator 130, the register 140, the register 150, and the memory access control unit 160 shown in FIG. And has the same function as the register 170. Further, the arithmetic processing device 500 is also the arithmetic processing device 400.
It has the same structure as.

The system control unit 600 comprises a memory request receiving unit 610, a translated address 620, an address translation mechanism 630 and a memory data return unit 640. The memory request receiving unit 610 is the processing unit 4
Memory request controller 46 of each of 00 and 500
The memory access request, the request address, and the access command are received from 0 and 560 and are sent to the main memory 700 in the order of priority. When the access command is address translation, the request address (virtual address to be translated) is registered in the address translation queue 620. Also, the request address from the address translation mechanism 630,
The request command and the memory access request are received and sent to the main memory 700.

The address translation mechanism 630 sequentially reads request addresses (virtual addresses to be translated) from the address translation queue 620, generates index addresses of tables expanded on the main memory 700, and requests memory access, access commands and requests. The address is sent to the memory request receiving unit 610.

The memory data return unit 640 is provided in the main memory 70.
The read data sent from 0 is sent to the memory request request source (memory access control units 460 and 560 of the arithmetic processing devices 400 and 500, the address translation mechanism 630).

The operation of converting a virtual address to a real address in this embodiment will be described below. The virtual address is composed of a virtual address conversion unit and an address non-translation unit, the upper address is the address translation unit and the lower address is the address non-translation unit. There will be described a case where the address conversion unit is composed of the comparison unit and the index unit, and the upper part is the comparison part and the lower part is the index part.

When the register 420 receives the virtual address A for which an address translation request is made from the address translation request source, the index translation section 410 of the register 420 indexes the address translation storage 410, and the read comparison section and the comparison section of the register 420 are read. The comparator 430 performs comparison, and the comparison result is set in the register 440. In parallel with this, the register 420
Is transferred to the register 450, and the real address read from the address translation storage 410 is set in the register 470.

In the next cycle, the contents of the register 440 are referred to. If the result of comparison in the comparator 430 indicates a match, the real address stored in the register 470 is sent to the address translation request source, The address conversion process ends. If the result shows a mismatch, the virtual address A stored in the register 450 is sent to the memory access control unit 460.

When the memory access control unit 460 receives the virtual address A from the register 450, the memory access control unit 460 requests the memory request receiving unit 610 in the system control device 600 to request a memory request, access command (address conversion), and request address (virtual). Send address A).

When the memory request receiving unit 610 in the system control device 600 receives the memory request request, access command, and request address from the memory access control unit 460, this request is ordered according to the priority order of this request and requests from other devices. Is processed, the request command is registered in the translated address queue 620 when the access command is interpreted and address translation is performed.

The address translation mechanism 630 reads the registered request address (virtual address A) from the translation address queue 630, indexes the address translation table developed in the main memory, and executes the address translation. For example, the address translation unit of the virtual address is X,
The description will proceed assuming that the field is divided into Y and Z fields.

The address translation mechanism 530 uses the main memory 700.
X is added to the base address of the first table developed above to generate a first request address for obtaining the base address of the second table. An access command and a memory request request are added to the first request address and the result is sent to the memory request accepting unit 610. The memory request receiving unit 610 receives these and sends them to the main memory 400.

The main memory 700 is a memory request request,
The access command and the request address are received, and the contents of the request address are sent to the memory data return unit 640 in the system controller 600.

The memory data return unit 640 receives the content of the first request address (base address of the second tape) from the main memory 700 and sends it to the address conversion mechanism 630.

The address conversion mechanism 630 receives the contents of the first request address, adds Y, and generates a second request address for obtaining the base address of the third table. After that, the contents of the second request address (the base address of the third table) are read by the same procedure as in the case of reading the contents of the first request address.

Next, the address translation mechanism 630 adds the contents of the second request address (base address of the third table) and Z to generate a third request address in which the real address corresponding to the virtual address A is stored. To do. At the address of the third request address, a control field is provided in addition to the real address, and access to this address requires exclusive use between access request sources. Therefore, the address translation mechanism 630 must suppress the access of another access request source during the reading of this address and the rewriting of the control field. For example,
When reading the third request address, the address is locked (however, if the lock is unsuccessful, the address is read again), and when writing the third request address, the address is unlocked.

When the third request address is generated, the address translation mechanism 630 sends an access command (read lock command),
The memory request reception unit 61 receives the memory request request.
Send to 0. The memory request acceptance unit 610 receives these and sends them to the main memory 700. Main memory 70
0 is the content of the third request address and lock success /
The unsuccessful information is sent to the memory data return unit 640. The memory data return unit 640 uses the contents of the third request address and the lock success / failure information as the address conversion mechanism 6.
Send to 30.

The address translation mechanism 630 reissues the request if the lock of the address of the third request address is unsuccessful. If the lock is successful, the address conversion mechanism 630 updates the control field of the address with the third request address and the access command. (Write unlock command), memory request request write data is sent to the memory request accepting unit 6
10 and sends the translated real address and the address translation end notification to the memory data return unit 640.
The memory data return unit 640 is used by the memory access control unit 4
The real address translated from the virtual address A and the address translation end notification are sent to 60.

When the memory access control unit 460 of the arithmetic processing value 400 receives this real address and the address translation end notification, it exchanges the contents of the register 450 (virtual address A) with the contents of the register 420, and then the register 420.
This real address is written into the address translation memory 410 together with the address translation unit of the virtual address 420 stored in. After that, the address conversion memory 410 is read out and the real address is set in the register 470. Then register 470
The real address stored in is sent to the address translation request source and the address translation is completed.

[0061]

As described above, according to the first aspect of the present invention, the address translation mechanism provided in the arithmetic processing unit is moved to the system control unit, and the address translation mechanism, the memory request receiving unit, the main memory, and the memory data return unit. The number of system clocks required for table indexing can be reduced by forming a memory read loop called a part and address translation mechanism.
This has the effect of speeding up address conversion.

In the second aspect of the present invention, the virtual address corresponding to the address translation request sent from each arithmetic processing unit is stored in an edge or an address queue, and the virtual addresses are sequentially translated into real addresses. The address translation mechanism can be shared by each arithmetic processing unit, and the amount of hardware in the entire system can be reduced.

In addition, since the conversion virtual address sent from each arithmetic processing unit is stored in the conversion address queue and processed sequentially, exclusive control of the real address storage address at the time of address conversion of each arithmetic processing unit is possible. The effect is to

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the first present invention.

FIG. 2 is a diagram showing an embodiment of the second invention.

FIG. 3 is a diagram showing a conventional example.

[Explanation of symbols]

1, 2, 100, 400, 500 Operation processing device 3, 200, 600 System control device 10, 20, 110, 410, 510 Address conversion storage 12, 22, 130, 430, 530 Comparator 15, 25, 220, 630 Address translation mechanism 17, 27, 160, 460, 560 Memory access control unit 30, 210, 610 Memory request reception unit 31, 230, 640 Memory data return unit 11, 13, 14, 16, 21, 23, 24, 26, 1
20, 140, 150, 170, 420, 410, 45
0,470,520,540,550,570 registers

Claims (2)

[Claims] 1. An information processing system comprising an arithmetic processing unit and a system control unit for controlling access to data to a main memory according to a request of the arithmetic unit, wherein the arithmetic processing unit is used in a computer system program. An address translation memory that stores an address translation pair of a virtual address and a real address that refers to the main memory is provided, and if the translation from the virtual address to the real address by the address translation memory fails, the virtual address and the address translation request are issued. In response to the translation requesting means to be sent to the system control device and the address translation end notification sent from the system control device, the real address translated from the virtual address is written to the address translation storage together with the virtual address. Conversion memory updating means, and whether the system control device is the arithmetic processing device An address translation mechanism that sequentially retrieves an address translation table expanded in the main memory and translates it into the real address by using the virtual address in response to the address translation request sent, and the address translation. An information processing system comprising: an end notification reporting means for sending the real address converted by the mechanism to the arithmetic processing unit together with an address conversion end notification. 2. An information processing system comprising a plurality of arithmetic processing units and a system control unit for controlling access to data to a main memory according to a request from each arithmetic processing unit, wherein each of the arithmetic processing units is a computer system. An address translation memory that stores an address translation pair of a virtual address used in a program and a real address that refers to the main memory, and if the translation from the virtual address to the real address fails due to the address translation memory, the virtual memory Translation requesting means for sending an address and an address translation request to the system controller, and a real address translated from the virtual address to the address translation memory in response to an address translation end notification sent from the system controller. Conversion memory updating means for writing together with the virtual address, and the system control device In response to the address translation request sent from each of the arithmetic processing units, a translated address queue that sequentially stores the virtual addresses added to the address translation request, and a virtual address that is sequentially read from the translated address queue. An address translation mechanism for sequentially indexing an address translation table developed in the main memory and translating it into a real address, and the real address translated by the address translation mechanism is addressed to the arithmetic processing unit requesting the address translation. An information processing system, comprising: an end report means for sending together with a conversion end notification.