JPH0561718A - Software evaluating system - Google Patents

Abstract

PURPOSE:To automatize software evaluation without using any special device by generating an interruption signal and deciding the timing of the generation in the control of an evaluation program. CONSTITUTION:This system is equipped with a means to generate the interruption signal and a means to change the execution sequence of the program and in the case of coming to a position to insert the interrupting signal on the half-way of executing the evaluation program, the interruption signal is generated by moving control to the means for generating the interruption signal. Thus, the evaluating method can be automatized, artificial error can be prevented, the reproducibility of evaluation is guaranteed, and the reliability of evaluation can be improved. Further, since functions required for the evaluation system are limited to a function for loading the program and a function for executing the loaded program only, the evaluation system can be constructed at extremely low cost.

Description

Detailed Description of the Invention

[0001]

The present invention relates to software inspection /
The present invention relates to an evaluation method, and particularly to an asynchronous evaluation.

[0002]

2. Description of the Related Art Conventional software inspection / evaluation will be described with reference to an example of real-time operating system inspection / evaluation.

Inspection items of a real-time operating system (hereinafter abbreviated as RTOS) are roughly classified into two types: basic evaluation and asynchronous evaluation. Further, the asynchronous evaluation can be divided into a case where an asynchronous signal comes in during task processing and a case where an asynchronous signal comes in during kernel processing.

The evaluation items used in this conventional example are a task management table of a task generated by an initial task with a priority lower than that of the initial task, activated by an interrupt handler, and generated / activated by the initial task. Is an asynchronous evaluation item for checking.

FIG. 9 is a diagram showing a work process of a conventional asynchronous evaluation.

FIG. 10 is a block diagram of an evaluation environment used conventionally. An interrupt controller (100 in FIG. 10)
4) is based on the μPD71059, and the interrupt event generator (1007 in FIG. 10) is based on a pulse generator capable of outputting an arbitrary signal.

First, before starting the asynchronous evaluation, the evaluation operator connects the interrupt event generator and the interrupt controller. In this conventional example, the output terminal of the pulse generator (1007 in FIG. 10) is connected to the IR1 terminal of the interrupt controller (1004 in FIG. 10).

Next, the evaluation operator operates the in-circuit emulator or the like to check the address to which the asynchronous signal is input ((1) in FIG. 9). In this conventional example, since the asynchronous signal is input after issuing the task generation system call, the address is the address where the task generation system call returns to the task processing.

The evaluation worker is the in-circuit
A break point, which is one of the functions of the emulator or the like, is set for this address ((2) in FIG. 9).

Up to this point, the evaluation operator must perform the work before executing the asynchronous evaluation program.

Then, the in-circuit emulator is operated to execute the asynchronous evaluation program ((3) in FIG. 9).

When the asynchronous evaluation program is executed, first an initial task is created and activated.

The initial task first defines an interrupt handler corresponding to an interrupt signal coming from IR1 of the interrupt controller, and opens the interrupt mask of IR1 ((4) in FIG. 9).

Then, a system call for task generation is issued with a task priority lower than that of the initial task ((5) in FIG. 9). At the point where task creation is completed, the breakpoint set earlier is reached.

When the break point is reached, the program is suspended from execution and returns to the command mode of the in-circuit emulator ((6) in FIG. 9).

The address at which the program is interrupted is the address at which the asynchronous signal is input. Therefore, the evaluation operator operates the pulse generator to generate an asynchronous signal ((7) in FIG. 9). The asynchronous signal generated by the pulse generator enters the IR1 terminal of the interrupt controller that was connected before running the evaluation program.

The evaluator confirms that an asynchronous signal is input from the in-circuit emulator, operates the in-circuit emulator, and restarts the suspended asynchronous evaluation program (FIG. 9). (8)).

When the asynchronous evaluation program is restarted, the previously input asynchronous signal is transferred from the interrupt controller to the CPU.
Be transmitted to. Then, the RTOS activates and executes the interrupt handler corresponding to the terminal of IR1 of the interrupt controller defined in the initial task ((9) in FIG. 9).

The interrupt handler issues a system call that activates the task created in the initial task ((10) in FIG. 9). In the interrupt handler, RT
Check the OS information table. Then, the process ends. When the interrupt handler ends, the process returns to the initial task ((11) in FIG. 9).

When returning to the initial task, the information in the task management table of the created / started task is based on the expected value, so that comparison and inspection are performed with the expected value embedded in the program in advance (see FIG. 9). (12)).

Next, the generated / started task is forcibly terminated ((13) in FIG. 9). Now that all the checks for this asynchronous item have been completed, the initial task itself is also completed ((14) in FIG. 9).

This completes the evaluation work for one asynchronous evaluation item.

[0023]

In the above-described conventional asynchronous evaluation method of RTOS, the evaluation operator uses an in-circuit emulator or the like to break the program from the start to the end of one evaluation program. You must set the points, operate the pulse generator to generate the asynchronous signal, and restart the evaluation program that was interrupted at the previously set break point.

Therefore, one worker is left alone for the evaluation work, and other work cannot be performed. Also, by operating the in-circuit emulator to set break points and restart the program, it takes a huge amount of time to execute all the asynchronous evaluation programs.

Further, since the operator has to operate the in-circuit emulator or the like, there is a possibility that a human error such as an error in setting a break point is made.

[0026]

SUMMARY OF THE INVENTION The present invention comprises means for generating a controllable interrupt signal on an evaluation board in asynchronous evaluation of software, means for changing the execution sequence of the program itself in the evaluation program, and A means for controlling the interrupt signal generating means is provided, and the means for changing the execution sequence is arranged in advance at the position where the interrupt signal should be inserted, or further, the original instruction and the means for changing the execution sequence are exchanged. Means and a means for storing the original instruction, the means for changing the execution sequence of the program is arranged by replacing the original instruction, and the execution position of the program reaches the position where the interrupt signal should be inserted. When this happens, the execution sequence is transferred to the control means and an interrupt signal is generated. That using means, characterized in that generating an asynchronous signal.

[0027]

[Embodiment 1] Next, the present invention will be described with reference to the drawings by taking an evaluation of a real-time operating system as an example.

FIG. 1 is a flowchart of an asynchronous evaluation program used in the first embodiment, and FIG. 5 is a flowchart of an asynchronous signal generation routine for generating an asynchronous signal used in the first embodiment. FIG. 8 is a block diagram of an evaluation environment for performing asynchronous evaluation.

In this embodiment, a parallel I / O, μPD71055 (803 in FIG. 8) is used as an asynchronous signal generator.
To use. In addition, the μPD7 is used as the interrupt controller.
1059 (804 in FIG. 8) is used. Then, the 0th terminal of the parallel I / O data bit is connected to the IR1 terminal of the interrupt controller in advance.

The evaluation worker executes the asynchronous evaluation program by using an in-circuit emulator or the like.

When the asynchronous evaluation program is executed, first, in the initial task, an interrupt handler corresponding to the asynchronous signal of the terminal IR1 of the interrupt controller is defined ((1) in FIG. 1).

Then, the task is generated using the task generation system call ((2) in FIG. 1).

Next, the asynchronous signal generation routine is called by the call instruction ((3) in FIG. 1). At this time, the pattern of the signal output from the parallel I / O is designated. In the case of this embodiment, a signal pattern that outputs a signal from data bit 0 of parallel I / O is designated. The pattern of this signal is described in the program as a value unique to this evaluation item when the asynchronous evaluation program is created.

In the called asynchronous signal generation routine, first, the interrupt disabled state is set ((1) in FIG. 5). This is to prevent an interrupt signal from entering in this asynchronous signal generation routine. Next, the pattern of the signal designated when calling the asynchronous signal generation routine is output from the parallel I / O ((2) in FIG. 5).

The output signal is input to the IR1 terminal of the interrupt controller which is connected in advance. That is, the output signal of the parallel I / O becomes the input signal of the interrupt controller, that is, the interrupt signal.

When an interrupt signal is input to IR1 of the interrupt controller and the asynchronous signal generation routine returns to the asynchronous evaluation program by the RET instruction, the interrupt disabled state previously disabled by the asynchronous signal generation routine is released ((4 in FIG. 1). )).

Then, the interrupt handler defined previously is activated by enabling the interrupt ((5) in FIG. 1).

In the interrupt handler, the task previously generated by the initial task is activated using the task generation system call ((6) in FIG. 1). Then, necessary checks are performed and the process returns to the initial task ((7) in FIG. 1).

In the initial task, the values of various tables and the expected values are compared / inspected, and the task that is generated / started last is forcibly terminated and the initial task itself is also terminated ((8) and (9 in FIG. 1). )).

This completes the evaluation work for one asynchronous evaluation item.

[0041]

[Embodiment 2] Similar to the embodiment described above, the evaluation of a real-time operating system will be described as an example with reference to the drawings.

FIG. 2 is a flowchart of the asynchronous evaluation program used in the second embodiment.

FIG. 3 is a flowchart of a break instruction embedding function for embedding a brk instruction, FIG. 4 is a flowchart of a code exchanging function for exchanging an original code and a brk instruction, and FIG. 6 is an asynchronous signal used in this embodiment. In the flow chart of the generation routine B, FIG. 7A is a part of the original code of the task generation system call, and FIG. 7B is the same location as FIG. 7A of the task generation system call. FIG. 6C is a list of the brk instruction restored to the original code in the asynchronous signal generation routine after the brk instruction is embedded.

FIG. 8 is a block diagram of an evaluation environment for performing asynchronous evaluation.

Similar to the above embodiment, it is assumed that a parallel I / O (803 in FIG. 8) is used as an asynchronous signal generator. The μPD71055 is assumed for the parallel I / O, and the μPD71059 is assumed for the interrupt controller. Then, as in the first embodiment, the 0th terminal of the data bit of the parallel I / O is connected to the IR1 terminal (804 in FIG. 8) of the interrupt controller.

In-circuit Asynchronous Evaluation Program
Run using an emulator.

In the asynchronous evaluation program used in the second embodiment, first, the interrupt handler corresponding to the asynchronous signal of the IR1 terminal of the interrupt controller is defined ((1) in FIG. 2).

Next, the information in the table relating to the current task, kernel, etc. is copied to the temporary area for evaluation ((2) in FIG. 2).

Then, the break instruction embedding function is called ((3) in FIG. 2). At this time, the address in which the break instruction is embedded and the pattern of the signal output from the parallel I / O are passed as arguments. In the case of this embodiment, the break instruction must be embedded at the address where the asynchronous signal is desired to be input. Therefore, the address where the brk instruction is to be embedded is passed as an argument to the break instruction embedding function. At this time, a unique label is embedded throughout the RTOS at the address where the asynchronous signal of the RTOS to be evaluated is to be inserted. In the case of this embodiment, it is embedded in the task generation system call. Then, the address value can be easily obtained by referring to the information of this unique label. Also in the case of the second embodiment, the pattern of the signal to be passed to the break instruction embedding function and the address to which the asynchronous signal is input are unique to the asynchronous evaluation item, as in the first embodiment.
Describe the asynchronous evaluation program in the program at the time of creation.

In the called break instruction embedding function, the brk instruction is embedded at the passed address.

When embedding the brk instruction, the original code must be saved in order to replace it with the original code. Therefore, in the break instruction embedding routine, the code replacement function is called ((2) in FIG. 3).

The code at the brk instruction embedded position in the task generation system call at this time is as shown in FIG.

In the code exchange function, first, the interrupt disabled state is set ((1) in FIG. 4), and the number of bytes of the brk instruction to be embedded is calculated from the address passed as an argument.
It is saved in another memory ((3) in FIG. 4). Here, the interrupt is prohibited in order to prevent an erroneous operation when an original signal and a brk instruction are replaced with each other because an asynchronous signal comes in during the code replacement.

Then, the brk instruction is embedded ((3) in FIG. 4). Further, an asynchronous signal generation routine is registered as a processing routine to be processed after the execution of the brk instruction ((4) in FIG. 4). Finally, the interrupt enabled state is set ((5) in FIG. 4) and the process returns to the task that called the break instruction embedding function.

Brk in the task generation system call when returning to the task from the break instruction embedding function
The code at the instruction embedding position is as shown in FIG.

Return to the initial task and continue processing. Then, a system call for task generation is issued ((5) in FIG. 2). In the task generation system call, processing is normally performed, but br is the address in which the brk instruction is embedded.
The k instruction is executed ((6) in FIG. 2). Then, the asynchronous signal generation routine registered as the processing routine after the execution of the brk instruction is executed ((7) in FIG. 2).

In the asynchronous signal generation routine, the interrupt disabled state is first set ((1) in FIG. 6). Here, interrupts are intended to mean that an asynchronous signal comes in during the processing of the RTOS that is the evaluation target.
When an asynchronous signal comes in in the evaluation routine,
This is because the original purpose of the evaluation cannot be achieved.

After the interrupt is disabled in the asynchronous signal generation routine, the embedded brk instruction is returned to the original instruction code ((2) in FIG. 6).

At this time, the task generation system call b
The code of the address in which the rk instruction is embedded is shown in FIG.
It looks like. Then, an asynchronous signal is generated.

In the asynchronous signal generation processing, the parallel I /
The signal pattern set when the break instruction embedding function is called from O is output ((3) in FIG. 6).

When the brk instruction is embedded, it is necessary to restart the execution from the instruction replaced with the brk instruction when generating the asynchronous signal and returning.

Therefore, the program is restarted from the instruction replaced with the brk instruction. The signal output from the parallel I / O in the previous asynchronous signal generation routine becomes the input signal of the interrupt controller, and the registered interrupt handler is activated ((7) in FIG. 2).

The interrupt handler processes the asynchronous signal that has entered the interrupt controller (see FIG. 2).
(8)).

After the processing for the asynchronous signal is performed, the process returns to the task generation system call in which the interrupt occurred ((9) in FIG. 2).

The remaining processing of the task generation system call is performed to generate the task ((10) in FIG. 2).

The initial task ends after checking the management table of the generated task ((1 in FIG. 2
1)).

[0067]

As described above, in the process of executing a software program, parallel I / O
An output terminal of a device capable of outputting an arbitrary bit pattern such as O is connected to a signal input terminal of an interrupt controller, and a bit pattern specified in the program is executed by a parallel I / O during execution of the asynchronous evaluation program. By inputting the output signal from the etc. to the interrupt controller as an asynchronous signal, deleting and automating the operation of stopping the program, generating an asynchronous signal, and resuming the program, which conventionally depended on human operation. This has made it possible to simplify the work and reduce the time.

Further, since the operation of the in-circuit emulator (setting of breakpoints, resumption of execution of the asynchronous evaluation program) and the operation of the pulse generator (generation of asynchronous signal) are eliminated, human error during operation is deleted. It also becomes.

Furthermore, when an asynchronous signal is input during the processing of the software to be evaluated as in the second embodiment,
By exchanging the brk instruction and the original code and generating an asynchronous signal, it is possible to evaluate and inspect without changing the original code.

As a means for generating an asynchronous signal, a parallel I / O or the like may be used to provide a pattern generator, a function to develop a program on a memory, and a function to execute the program, and an in-circuit emulator or the like. There is also the effect that multiple evaluation environments can be constructed at low cost without the need for special equipment.

[Brief description of drawings]

FIG. 1 is a flowchart of an asynchronous evaluation program used in Example 1.

FIG. 2 is a flowchart of an asynchronous evaluation program used in the second embodiment.

FIG. 3 is a flowchart of a break instruction embedding function used in the second embodiment.

FIG. 4 is a code replacement function flowchart used in the second embodiment.

FIG. 5 is a flowchart of an asynchronous signal generation routine A used in the first embodiment.

FIG. 6 is a flowchart of an asynchronous signal generation routine B used in the second embodiment.

FIG. 7 is a list of system calls for task generation used in the second embodiment, (A) is a list before embedding a brk instruction, (B) is a list when a brk instruction is embedded,
(C) is a list when the code is returned to the original.

FIG. 8 is an evaluation environment configuration used in Examples 1 and 2.

FIG. 9 is a conventional workflow of asynchronous evaluation.

FIG. 10 shows a conventional evaluation environment configuration.

Claims (3)

[Claims] 1. In asynchronous evaluation of software, means for generating a controllable interrupt signal on the evaluation board, means for changing the execution sequence of the program itself in the evaluation program, and control the interrupt signal generating means. Means for arranging the means for changing the execution sequence at a position where an interrupt signal should be inserted, and when the execution position of the program reaches the position, means for transferring the execution sequence to the control means and generating an interrupt signal A software evaluation method characterized by generating an asynchronous signal using. 2. The software evaluation method according to claim 1, wherein the means for changing the execution sequence of the program is arranged in advance when the evaluation program is created. 3. A program to be evaluated, comprising means for exchanging an original instruction and a means for changing an execution sequence, and means for storing an original instruction, wherein the means for changing the execution sequence of the program is an evaluation target. 2. The software evaluation method according to claim 1, wherein the software evaluation method is arranged by replacing the original instruction with the original instruction before execution of, and returning to the original instruction after changing the execution sequence.